testsuite/synth/issue1442/fixed_round_crash_correct.vhdl

   1 library IEEE;
   2 use IEEE.STD_LOGIC_1164.ALL;
   3 use IEEE.NUMERIC_STD.ALL;
   4 use IEEE.FIXED_PKG.ALL;
   5
   6 entity fixed_round_crash_correct is
   7     Port (
   8         input_fixed: in SFIXED(3 downto -2);
   9         output_signed: out SIGNED(7 downto 0)
  10     );
  11 end entity;
  12
  13 architecture Behavioral of fixed_round_crash_correct is
  14     -- real * sfixed(a downto b) -> sfixed(2a+1 downto 2b)
  15     signal intermediate: SFIXED(7 downto -4);
  16 begin
  17     intermediate <= 1.5*input_fixed;
  18     output_signed <= to_signed(input_fixed, 8);
  19 end Behavioral;