verilog: add sv_maps iterators

[ghdl-vlg.git] / testsuite / synth / issue1536 / ent1.vhdl

library ieee;
use ieee.std_logic_1164.all;

entity ent1 is
    port (
        i: in bit;
        o: out std_ulogic
    );
end entity;

architecture arch of ent1 is
begin
    o <= to_stdulogic(i);
end architecture;