testsuite/synth/issue1703/blinker.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3
   4 entity Blinker is
   5         port(
   6                 clk_i : in std_logic;
   7                 rst_i : in std_logic;
   8                 led_o : out std_logic
   9         );
  10 end Blinker;
  11
  12 architecture RTL of Blinker is
  13         constant N : natural := 25e6;
  14         signal count_reg : natural range 0 to N - 1;
  15 begin
  16         process(rst_i, clk_i)
  17         begin
  18                 if rst_i = '1' then
  19                         count_reg <= 0;
  20                 elsif rising_edge(clk_i) then
  21                         if count_reg = N - 1 then
  22                                 count_reg <= 0;
  23                         else
  24                                 count_reg <= count_reg + 1;
  25                         end if;
  26                 end if;
  27         end process;
  28
  29         led_o <= '1' when count_reg < N / 2 else '0';
  30 end RTL;