repo.or.cz
/
ghdl-vlg.git
/
blob
commit
grep
author
committer
pickaxe
?
search:
re
summary
|
log
|
graphiclog1
|
graphiclog2
|
commit
|
commitdiff
|
tree
|
refs
|
edit
|
fork
blame
|
history
|
raw
|
HEAD
verilog: add sv_maps iterators
[ghdl-vlg.git]
/
testsuite
/
synth
/
issue1948
/
test.vhdl
blob
ba8ee69d6d520937cb3ffe336641f940fe7dced1
1
package gen_pkg is
2
generic (type T);
3
4
procedure proc;
5
end gen_pkg;
6
7
package body gen_pkg is
8
procedure proc is
9
begin
10
null;
11
end proc;
12
end gen_pkg;
13
14
entity test is
15
end entity test;
16
17
architecture simple of test is
18
package pkg is new work.gen_pkg generic map (t => integer);
19
begin
20
end architecture simple;