verilog: add sv_maps iterators

[ghdl-vlg.git] / testsuite / synth / issue2025 / wb_standard_axi4_lite_bridge_rtl.vhd

ENTITY wb_standard_axi4_lite_bridge IS
END ENTITY wb_standard_axi4_lite_bridge;

ARCHITECTURE rtl OF wb_standard_axi4_lite_bridge IS
BEGIN
END ARCHITECTURE rtl;