verilog: add sv_maps iterators

[ghdl-vlg.git] / testsuite / synth / issue2053 / testsuite.sh

#! /bin/sh

. ../../testenv.sh

GHDL_STD_FLAGS=--std=08

synth generic_fifo_fwft.vhdl generic_fifo_fwft_inst.vhdl -e > syn_generic_fifo_fwft_inst

echo "Test successful"