verilog: add sv_maps iterators
[ghdl-vlg.git] / testsuite / synth / issue2077 / ent2.vhdl
blobf4f91f827e5b69360019d0d25c5717cbb5c9401f
1 library ieee;
2 use ieee.std_logic_1164.all;
3 use ieee.numeric_std.all;
5 entity ent2 is
6         generic (
7                 DEPTH : positive := 256;
8                 WAYS : positive := 4
9         );
10         port (
11                 clk: in std_logic;
13                 write_enable: in std_logic;
14                 active_way: in natural range 0 to WAYS-1;
15                 write_address: in natural range 0 to DEPTH-1;
16                 input: in std_logic;
18                 read_address: in natural range 0 to DEPTH-1;
19                 outputs: out std_logic
20         );
21 end entity;
23 architecture a of ent2 is
24 begin
25         process(clk)
26           type memory_t is array(0 to DEPTH-1) of std_logic;
27           type memories_t is array(0 to WAYS-1) of memory_t;
29           variable memories : memories_t;
30         begin
31           if rising_edge(clk) then
32             outputs <= memories(active_way)(read_address);
34             if write_enable then
35               memories(active_way)(write_address) := input;
36             end if;
37           end if;
38         end process;
39 end architecture;