2 use ieee.std_logic_1164.all;
3 use ieee.numeric_std.all;
7 DEPTH : positive := 256;
13 write_enable: in std_logic;
14 active_way: in natural range 0 to WAYS-1;
15 write_address: in natural range 0 to DEPTH-1;
18 read_address: in natural range 0 to DEPTH-1;
19 outputs: out std_logic
23 architecture a of ent2 is
26 type memory_t is array(0 to DEPTH-1) of std_logic;
27 type memories_t is array(0 to WAYS-1) of memory_t;
29 variable memories : memories_t;
31 if rising_edge(clk) then
32 outputs <= memories(active_way)(read_address);
35 memories(active_way)(write_address) := input;