testsuite/synth/issue2077/ent5.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4
   5 entity ent5 is
   6         generic (
   7                 WIDTH : positive := 8;
   8                 DEPTH : positive := 256;
   9
  10                 WAYS : positive := 4
  11         );
  12         port (
  13                 clk: in std_logic;
  14
  15                 write_enable: in std_logic;
  16                 active_way: in natural range 0 to WAYS-1;
  17                 write_address: in natural range 0 to DEPTH-1;
  18                 input: in std_logic_vector(WIDTH-1 downto 0);
  19
  20                 read_address: in natural range 0 to DEPTH-1;
  21                 output: out std_logic_vector(WIDTH-1 downto 0)
  22         );
  23 end entity;
  24
  25 architecture a of ent5 is
  26 begin
  27   process(clk)
  28     type memory_t is array(0 to DEPTH-1) of std_logic_vector(WIDTH-1 downto 0);
  29     type memories_t is array(0 to WAYS-1) of memory_t;
  30
  31     variable memories : memories_t;
  32   begin
  33     if rising_edge(clk) then
  34       output <= memories(active_way)(read_address);
  35
  36       if write_enable then
  37         memories(active_way)(write_address) := input;
  38       end if;
  39     end if;
  40   end process;
  41 end architecture;