testsuite/synth/issue2081/ent.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3
   4 entity ent is
   5 end entity;
   6
   7 architecture a of ent is
   8         signal foo : std_logic_vector(7 downto 0);
   9 begin
  10         process(foo)
  11         begin
  12                 if foo /= x"00" then
  13                         assert false;
  14                 end if;
  15         end process;
  16 end architecture;