testsuite/synth/issue2109/testsuite.sh

   1 #! /bin/sh
   2
   3 . ../../testenv.sh
   4
   5 synth --out=verilog bug.vhdl -e > syn_bug.v
   6
   7 if grep val syn_bug.v; then
   8   exit 1
   9 fi
  10
  11 echo "Test successful"