testsuite/synth/issue2113/testsuite.sh

   1 #! /bin/sh
   2
   3 . ../../testenv.sh
   4
   5 GHDL_STD_FLAGS=--std=08
   6 synth --out=verilog -Wno-nowrite a.vhdl -e > syn_a.v
   7
   8 if grep channel syn_a.v; then
   9   exit 1
  10 fi
  11 if grep "0'" syn_a.v; then
  12   exit 1;
  13 fi
  14
  15 synth --out=verilog -Wno-nowrite c.vhdl -e > syn_c.v
  16 if grep channel syn_c.v; then
  17   exit 1
  18 fi
  19
  20 echo "Test successful"