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verilog: add sv_maps iterators
[ghdl-vlg.git] / testsuite / synth / issue2129 / testsuite.sh
bloba8c21100f95dcaf3af87e1ae5d359671f444730a
1 #! /bin/sh
2
3 . ../../testenv.sh
4
5 GHDL_STD_FLAGS=--std=08
6
7 synth_only isx
8
9 echo "Test successful"
Experimental work