testsuite/synth/issue2140/bug.vhdl

   1 library IEEE;
   2 use IEEE.std_logic_1164.all;
   3 use IEEE.numeric_std.all;
   4
   5 entity sub is
   6         port (
   7                 clk       :  in std_ulogic;
   8                 reset_n   :  in std_ulogic;
   9
  10                 src_valid :  in std_ulogic;
  11                 src_ready : out std_ulogic
  12         );
  13 end sub;
  14
  15 architecture rtl of sub is
  16 begin
  17 end architecture;
  18
  19 library IEEE;
  20 use IEEE.std_logic_1164.all;
  21 use IEEE.numeric_std.all;
  22
  23 entity bug is
  24         port(
  25                 clk     : in std_ulogic;
  26                 reset_n : in std_ulogic
  27         );
  28 end bug;
  29
  30 architecture struct of bug is
  31         signal filtered_src_valid       : std_ulogic;
  32         signal filtered_src_ready       : std_ulogic;
  33
  34         signal pipeline_src_valid       : std_ulogic;
  35         signal pipeline_src_ready       : std_ulogic;
  36
  37         type state_t is (idle, active);
  38         signal state : state_t;
  39 begin
  40
  41 pipeline_src_valid <= filtered_src_valid when (state = idle) or (state = active) else '0';
  42
  43 process(clk, reset_n)
  44 begin
  45         if reset_n = '0' then
  46         elsif rising_edge(clk) then
  47                 if state = idle then
  48                         if filtered_src_valid = '1' and filtered_src_ready = '1'  then
  49                                 state <= active;
  50                         end if;
  51                 elsif state = active then
  52                         if pipeline_src_valid = '1' and pipeline_src_ready = '1'  then
  53                                 state <= idle;
  54                         end if;
  55                 end if;
  56         end if;
  57 end process;
  58
  59 pipeline : entity work.sub
  60         port map(
  61                 clk      => clk,
  62                 reset_n  => reset_n,
  63
  64                 src_valid => pipeline_src_valid,
  65                 src_ready => pipeline_src_ready
  66         );
  67
  68 end architecture;