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verilog: add sv_maps iterators
[ghdl-vlg.git]
/
testsuite
/
synth
/
issue2143
/
repro1.vhdl
blob
c51baf62c66c9607b057836bbf52cc81ffb5c8fe
1
entity repro1 is
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end repro1;
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architecture struct of repro1 is
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type entry_t is record
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a : bit;
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end record;
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type table_t is array (natural range<>, natural range<>) of entry_t;
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function fun return table_t is
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variable ret : table_t(0 to 7, 0 to 7);
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begin
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return ret;
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end function;
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constant entry : entry_t := fun(0, 0);
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begin
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end architecture;