testsuite/synth/issue972/test2.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4
   5 entity test2 is
   6     port(
   7         d_in: in std_ulogic_vector(63 downto 0);
   8         d_out: out std_ulogic_vector(63 downto 0)
   9         );
  10 end entity test2;
  11
  12 architecture behaviour of test2 is
  13 begin
  14     comb : process(all)
  15     begin
  16         d_out <= std_logic_vector(unsigned(d_in) + 4);
  17     end process;
  18 end architecture behaviour;