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HEAD
verilog: add sv_maps iterators
[ghdl-vlg.git]
/
testsuite
/
synth
/
module01
/
tb_fulladder2b.v
blob
298c84c112600a2eebb7a92924dccdd5b1a69715
1
module
tb_fulladder2b
;
2
reg
cin
;
3
reg
[
1
:
0
]
a
;
4
wire
[
1
:
0
]
res
;
5
wire
cout
;
6
7
fulladder2b
dut
(
.
sum
(
res
),
.
cout
(
cout
),
.
a
(
a
),
.
cin
(
cin
));
8
9
initial begin
10
a
<=
2'
h1
;
11
cin
<=
0
;
12
#
1
;
13
$display
(
"res=%b"
,
res
);
14
if
(
res
!==
4'
h1 || cout
!=
0
)
15
$fatal
(
1
,
"FAILURE"
);
16
17
cin
<=
1
;
18
#1
;
19
$display
(
"res=%b"
,
res
);
20
if
(
res
!==
4'
h2 || cout
!=
0
)
21
$fatal
(
1
,
"FAILURE"
);
22
23
$finish
;
24
end
25
endmodule