verilog: add sv_maps iterators
[ghdl-vlg.git] / testsuite / synth / module01 / tb_fulladder4.v
blob672d86b9f171421d49eadc28d4736beddd869cc5
1 module tb_fulladder4;
2 reg cin;
3 reg [3:0] a;
4 reg [3:0] b;
5 wire [3:0] res;
6 wire cout;
8 fulladder4 dut (.sum(res), .cout(cout), .a(a), .b(b), .cin(cin));
10 initial begin
11 a <= 4'h7;
12 b <= 4'h6;
13 cin <= 0;
14 # 1;
15 $display("res=%b", res);
16 if (res !== 4'hd || cout != 0)
17 $fatal(1, "FAILURE");
19 cin <= 1;
20 #1;
21 $display("res=%b", res);
22 if (res !== 4'he || cout != 0)
23 $fatal(1, "FAILURE");
25 $display("PASS");
26 $finish;
27 end
28 endmodule