testsuite/synth/module02/tb_module01.v

   1 module tb_module01b;
   2    reg clk;
   3    reg rst;
   4    wire [7:0] val;
   5    wire       one;
   6
   7    module01 dut (.clk(clk), .rst(rst), .val(val), .one(one));
   8
   9    initial begin
  10       rst <= 1;
  11
  12       clk <= 0;
  13       #1;
  14       clk <= 1;
  15       #1;
  16       $display("val=%b", val);
  17       if (val !== 8'h0 || one != 0)
  18         $fatal(1, "FAILURE");
  19
  20       rst <= 0;
  21       clk <= 0;
  22       # 1;
  23       clk <= 1;
  24       #1;
  25       if (val !== 8'h1 || one != 1)
  26         $fatal(1, "FAILURE");
  27
  28       clk <= 0;
  29       # 1;
  30       clk <= 1;
  31       #1;
  32       if (val !== 8'h2 || one != 0)
  33         $fatal(1, "FAILURE");
  34
  35       $display("PASS");
  36       $finish;
  37    end
  38 endmodule