testsuite/synth/module02/tb_module03.v

   1 module tb_module03;
   2    reg clk;
   3    reg rst;
   4    wire       two;
   5
   6    module03 dut (.clk(clk), .rst(rst), .two(two));
   7
   8    initial begin
   9       rst <= 1;
  10
  11       clk <= 0;
  12       #1;
  13       clk <= 1;
  14       #1;
  15       if (two != 0)
  16         $fatal(1, "FAILURE");
  17
  18       rst <= 0;
  19       clk <= 0;
  20       # 1;
  21       clk <= 1;
  22       #1;
  23       if (two != 0)
  24         $fatal(1, "FAILURE");
  25
  26       clk <= 0;
  27       # 1;
  28       clk <= 1;
  29       #1;
  30       if (two != 1)
  31         $fatal(1, "FAILURE");
  32
  33       $display("PASS");
  34       $finish;
  35    end
  36 endmodule