repo.or.cz
/
ghdl-vlg.git
/
blob
commit
grep
author
committer
pickaxe
?
search:
re
summary
|
log
|
graphiclog1
|
graphiclog2
|
commit
|
commitdiff
|
tree
|
refs
|
edit
|
fork
blame
|
history
|
raw
|
HEAD
verilog: add sv_maps iterators
[ghdl-vlg.git]
/
testsuite
/
synth
/
oper01
/
tb_snum04.vhdl
blob
97bb8975441c9c0ea70cdce4d0b3a429887b8d8a
1
entity tb_snum04 is
2
end tb_snum04;
3
4
library ieee;
5
use ieee.std_logic_1164.all;
6
7
architecture behav of tb_snum04 is
8
signal r : boolean;
9
begin
10
cmp04_1: entity work.snum04
11
port map (r);
12
13
process
14
begin
15
wait for 1 ns;
16
assert r severity failure;
17
18
wait;
19
end process;
20
end behav;