verilog: add sv_maps iterators
[ghdl-vlg.git] / testsuite / synth / psl02 / testsuite.sh
bloba45a0e0ffdd8c3b8c28dbf2713da858cff766611
1 #! /bin/sh
3 . ../../testenv.sh
5 GHDL_STD_FLAGS=--std=08
7 synth assert1.vhdl -e assert1 > syn_assert1.vhdl
8 analyze syn_assert1.vhdl
10 synth assert2.vhdl verif1.vhdl -e assert2 > syn_assert21.vhdl
11 analyze syn_assert21.vhdl
13 clean
15 synth assert2.vhdl verif2.vhdl -e assert2 > syn_assert22.vhdl
16 analyze syn_assert22.vhdl
18 clean
20 synth assert2.vhdl verif3.vhdl -e assert2 > syn_assert23.vhdl
21 analyze syn_assert23.vhdl
23 clean
25 synth assert2.vhdl verif4.vhdl -e assert2 > syn_assert24.vhdl
26 analyze syn_assert23.vhdl
28 clean
30 synth assert2.vhdl verif5.vhdl -e assert2 > syn_assert25.vhdl
31 analyze syn_assert25.vhdl
33 clean
35 echo "Test successful"