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verilog: add sv_maps iterators
[ghdl-vlg.git]
/
testsuite
/
synth
/
synth52
/
sample_pkg.vhdl
blob
3f47ca6c277a410e4955e363c876b7b8b1961d02
1
package sample_pkg is
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constant SAMPLE_CONSTANT : integer;
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end sample_pkg;
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package body sample_pkg is
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constant SAMPLE_CONSTANT : integer := 160;
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end sample_pkg;