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HEAD
verilog: add a first test for associative arrays
[ghdl-vlg.git]
/
src
/
verilog
/
tests
/
07_aggregate
/
07_08_associative
/
07_08_001.v
blob
700db77e93cca2823df286c16ab4d33bc2967d82
1
// NE
2
module
m1
;
3
int map
[
string
];
4
5
initial begin
6
map
[
"one"
] =
1
;
7
if
(
map
[
"one"
] !==
1
)
8
$fatal
(
0
,
"FAIL"
);
9
$display
(
"PASS"
);
10
end
11
endmodule