sysdeps/standalone/i960/nindy960/brdinit.c

   1 /* Copyright (C) 1994, 1997 Free Software Foundation, Inc.
   2    This file is part of the GNU C Library.
   3    Contributed by Joel Sherrill (jsherril@redstone-emh2.army.mil),
   4      On-Line Applications Research Corporation.
   5
   6    The GNU C Library is free software; you can redistribute it and/or
   7    modify it under the terms of the GNU Lesser General Public
   8    License as published by the Free Software Foundation; either
   9    version 2.1 of the License, or (at your option) any later version.
  10
  11    The GNU C Library is distributed in the hope that it will be useful,
  12    but WITHOUT ANY WARRANTY; without even the implied warranty of
  13    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14    Lesser General Public License for more details.
  15
  16    You should have received a copy of the GNU Lesser General Public
  17    License along with the GNU C Library; if not, write to the Free
  18    Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
  19    02111-1307 USA.  */
  20
  21 #include <standalone.h>
  22 #include "i960ca.h"
  23
  24 /*  _Board_Initialize()
  25
  26 This routine initializes the board.
  27
  28 NOTE: Only tested on a Cyclone CVME961 but should be OK on any i960ca board. */
  29
  30 void
  31 _Board_Initialize ()
  32 {
  33   struct i80960ca_prcb   *prcb;     /* ptr to processor control block */
  34   struct i80960ca_ctltbl *ctl_tbl;  /* ptr to control table */
  35
  36   static inline struct i80960ca_prcb *get_prcb()
  37   { register struct i80960ca_prcb *_prcb = 0;
  38     asm volatile( "calls 5; \
  39                    mov   g0,%0" \
  40                    : "=d" (_prcb) \
  41                    : "0" (_prcb) );
  42     return ( _prcb );
  43   }
  44
  45   prcb    = get_prcb ();
  46   ctl_tbl = prcb->control_tbl;
  47
  48   /*   The following configures the data breakpoint (which must be set
  49    *   before this is executed) to break on writes only.
  50    */
  51
  52   ctl_tbl->bpcon &= ~0x00cc0000;
  53   reload_ctl_group (6);
  54
  55    /*  bit 31 of the Register Cache Control can be set to
  56     *  enable an alternative caching algorithm.  It does
  57     *  not appear to help our applications.
  58     */
  59
  60    /* Configure Number of Register Caches */
  61
  62   prcb->reg_cache_cfg = 8;
  63   soft_reset (prcb);
  64 }