sysdeps/unix/sysv/linux/alpha/ioperm.c

   1 /* Copyright (C) 1992, 1996-1999, 2000 Free Software Foundation, Inc.
   2    This file is part of the GNU C Library.
   3    Contributed by David Mosberger.
   4
   5    The GNU C Library is free software; you can redistribute it and/or
   6    modify it under the terms of the GNU Lesser General Public
   7    License as published by the Free Software Foundation; either
   8    version 2.1 of the License, or (at your option) any later version.
   9
  10    The GNU C Library is distributed in the hope that it will be useful,
  11    but WITHOUT ANY WARRANTY; without even the implied warranty of
  12    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  13    Lesser General Public License for more details.
  14
  15    You should have received a copy of the GNU Lesser General Public
  16    License along with the GNU C Library; if not, write to the Free
  17    Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
  18    02111-1307 USA.  */
  19
  20 /* I/O access is restricted to ISA port space (ports 0..65535).
  21    Modern devices hopefully are sane enough not to put any performance
  22    critical registers in i/o space.
  23
  24    On the first call to ioperm, the entire (E)ISA port space is mapped
  25    into the virtual address space at address io.base.  mprotect calls
  26    are then used to enable/disable access to ports.  Per page, there
  27    are PAGE_SIZE>>IO_SHIFT I/O ports (e.g., 256 ports on a Low Cost Alpha
  28    based system using 8KB pages).
  29
  30    Keep in mind that this code should be able to run in a 32bit address
  31    space.  It is therefore unreasonable to expect mmap'ing the entire
  32    sparse address space would work (e.g., the Low Cost Alpha chip has an
  33    I/O address space that's 512MB large!).  */
  34
  35 /* Make sure the ldbu/stb asms below are not expaneded to macros.  */
  36 #ifndef __alpha_bwx__
  37 asm(".arch ev56");
  38 #endif
  39
  40 #include <errno.h>
  41 #include <fcntl.h>
  42 #include <stdio.h>
  43 #include <ctype.h>
  44 #include <stdlib.h>
  45 #include <string.h>
  46 #include <unistd.h>
  47
  48 #include <sys/types.h>
  49 #include <sys/mman.h>
  50 #include <sys/io.h>
  51
  52 #include <sysdep.h>
  53 #include <sys/syscall.h>
  54
  55 #define PATH_ALPHA_SYSTYPE      "/etc/alpha_systype"
  56 #define PATH_CPUINFO            "/proc/cpuinfo"
  57
  58 #define MAX_PORT        0x10000
  59 #define vip             volatile int *
  60 #define vuip            volatile unsigned int *
  61 #define vusp            volatile unsigned short *
  62 #define vucp            volatile unsigned char *
  63
  64 #define JENSEN_IO_BASE          (0x300000000UL)
  65 #define JENSEN_SPARSE_MEM       (0x200000000UL)
  66
  67 /* With respect to the I/O architecture, APECS and LCA are identical,
  68    so the following defines apply to LCA as well.  */
  69 #define APECS_IO_BASE           (0x1c0000000UL)
  70 #define APECS_SPARSE_MEM        (0x200000000UL)
  71 #define APECS_DENSE_MEM         (0x300000000UL)
  72
  73 /* The same holds for CIA and PYXIS, except for PYXIS we prefer BWX.  */
  74 #define CIA_IO_BASE             (0x8580000000UL)
  75 #define CIA_SPARSE_MEM          (0x8000000000UL)
  76 #define CIA_DENSE_MEM           (0x8600000000UL)
  77
  78 #define PYXIS_IO_BASE           (0x8900000000UL)
  79 #define PYXIS_DENSE_MEM         (0x8800000000UL)
  80
  81 /* SABLE is EV4, GAMMA is EV5 */
  82 #define T2_IO_BASE              (0x3a0000000UL)
  83 #define T2_SPARSE_MEM           (0x200000000UL)
  84 #define T2_DENSE_MEM            (0x3c0000000UL)
  85
  86 #define GAMMA_IO_BASE           (0x83a0000000UL)
  87 #define GAMMA_SPARSE_MEM        (0x8200000000UL)
  88 #define GAMMA_DENSE_MEM         (0x83c0000000UL)
  89
  90 /* NOTE: these are hardwired to PCI bus 0 addresses!!! */
  91 #define MCPCIA_IO_BASE          (0xf980000000UL)
  92 #define MCPCIA_SPARSE_MEM       (0xf800000000UL)
  93 #define MCPCIA_DENSE_MEM        (0xf900000000UL)
  94
  95 /* Tsunami and Irongate use the same offsets, at least for hose 0.  */
  96 #define TSUNAMI_IO_BASE         (0x801fc000000UL)
  97 #define TSUNAMI_DENSE_MEM       (0x80000000000UL)
  98
  99 /* Polaris has SPARSE space, but we prefer to use only DENSE
 100    because of some idiosyncracies in actually using SPARSE.  */
 101 #define POLARIS_IO_BASE         (0xf9fc000000UL)
 102 #define POLARIS_DENSE_MEM       (0xf900000000UL)
 103
 104 typedef enum {
 105   IOSYS_UNKNOWN, IOSYS_JENSEN, IOSYS_APECS, IOSYS_CIA, IOSYS_PYXIS, IOSYS_T2,
 106   IOSYS_TSUNAMI, IOSYS_MCPCIA, IOSYS_GAMMA, IOSYS_POLARIS,
 107   IOSYS_CPUDEP, IOSYS_PCIDEP
 108 } iosys_t;
 109
 110 typedef enum {
 111   IOSWIZZLE_JENSEN, IOSWIZZLE_SPARSE, IOSWIZZLE_DENSE
 112 } ioswizzle_t;
 113
 114 static struct io_system {
 115   unsigned long int bus_memory_base;
 116   unsigned long int sparse_bus_mem_base;
 117   unsigned long int bus_io_base;
 118 } io_system[] = { /* NOTE! must match iosys_t enumeration */
 119 /* UNKNOWN */   {0, 0, 0},
 120 /* JENSEN */    {0, JENSEN_SPARSE_MEM, JENSEN_IO_BASE},
 121 /* APECS */     {APECS_DENSE_MEM, APECS_SPARSE_MEM, APECS_IO_BASE},
 122 /* CIA */       {CIA_DENSE_MEM, CIA_SPARSE_MEM, CIA_IO_BASE},
 123 /* PYXIS */     {PYXIS_DENSE_MEM, 0, PYXIS_IO_BASE},
 124 /* T2 */        {T2_DENSE_MEM, T2_SPARSE_MEM, T2_IO_BASE},
 125 /* TSUNAMI */   {TSUNAMI_DENSE_MEM, 0, TSUNAMI_IO_BASE},
 126 /* MCPCIA */    {MCPCIA_DENSE_MEM, MCPCIA_SPARSE_MEM, MCPCIA_IO_BASE},
 127 /* GAMMA */     {GAMMA_DENSE_MEM, GAMMA_SPARSE_MEM, GAMMA_IO_BASE},
 128 /* POLARIS */   {POLARIS_DENSE_MEM, 0, POLARIS_IO_BASE},
 129 /* CPUDEP */    {0, 0, 0}, /* for platforms dependent on CPU type */
 130 /* PCIDEP */    {0, 0, 0}, /* for platforms dependent on core logic */
 131 };
 132
 133 static struct platform {
 134   const char       *name;
 135   iosys_t           io_sys;
 136 } platform[] = {
 137   {"Alcor",     IOSYS_CIA},
 138   {"Avanti",    IOSYS_APECS},
 139   {"Cabriolet", IOSYS_APECS},
 140   {"EB164",     IOSYS_PCIDEP},
 141   {"EB64+",     IOSYS_APECS},
 142   {"EB66",      IOSYS_APECS},
 143   {"EB66P",     IOSYS_APECS},
 144   {"Jensen",    IOSYS_JENSEN},
 145   {"Miata",     IOSYS_PYXIS},
 146   {"Mikasa",    IOSYS_CPUDEP},
 147   {"Nautilus",  IOSYS_TSUNAMI},
 148   {"Noname",    IOSYS_APECS},
 149   {"Noritake",  IOSYS_CPUDEP},
 150   {"Rawhide",   IOSYS_MCPCIA},
 151   {"Ruffian",   IOSYS_PYXIS},
 152   {"Sable",     IOSYS_CPUDEP},
 153   {"Takara",    IOSYS_CIA},
 154   {"Tsunami",   IOSYS_TSUNAMI},
 155   {"XL",        IOSYS_APECS},
 156 };
 157
 158 struct ioswtch {
 159   void          (*sethae)(unsigned long int addr);
 160   void          (*outb)(unsigned char b, unsigned long int port);
 161   void          (*outw)(unsigned short b, unsigned long int port);
 162   void          (*outl)(unsigned int b, unsigned long int port);
 163   unsigned int  (*inb)(unsigned long int port);
 164   unsigned int  (*inw)(unsigned long int port);
 165   unsigned int  (*inl)(unsigned long int port);
 166 };
 167
 168 static struct {
 169   unsigned long int hae_cache;
 170   unsigned long int     base;
 171   struct ioswtch *      swp;
 172   unsigned long int     bus_memory_base;
 173   unsigned long int     sparse_bus_memory_base;
 174   unsigned long int     io_base;
 175   ioswizzle_t           swiz;
 176 } io;
 177
 178 static inline void
 179 stb_mb(unsigned char val, unsigned long addr)
 180 {
 181   __asm__("stb %1,%0; mb" : "=m"(*(vucp)addr) : "r"(val));
 182 }
 183
 184 static inline void
 185 stw_mb(unsigned short val, unsigned long addr)
 186 {
 187   __asm__("stw %1,%0; mb" : "=m"(*(vusp)addr) : "r"(val));
 188 }
 189
 190 static inline void
 191 stl_mb(unsigned int val, unsigned long addr)
 192 {
 193   __asm__("stl %1,%0; mb" : "=m"(*(vip)addr) : "r"(val));
 194 }
 195
 196 /* No need to examine error -- sethae never fails.  */
 197 static inline void
 198 __sethae(unsigned long value)
 199 {
 200   register unsigned long r16 __asm__("$16") = value;
 201   register unsigned long r0 __asm__("$0") = __NR_sethae;
 202   __asm__ __volatile__ ("callsys"
 203                         : "=r"(r0)
 204                         : "0"(r0), "r" (r16)
 205                         : inline_syscall_clobbers, "$19");
 206 }
 207
 208 extern long __pciconfig_iobase(enum __pciconfig_iobase_which __which,
 209                                unsigned long int __bus,
 210                                unsigned long int __dfn);
 211
 212 static inline unsigned long int
 213 port_to_cpu_addr (unsigned long int port, ioswizzle_t ioswiz, int size)
 214 {
 215   if (ioswiz == IOSWIZZLE_SPARSE)
 216     return io.base + (port << 5) + ((size - 1) << 3);
 217   else if (ioswiz == IOSWIZZLE_DENSE)
 218     return port + io.base;
 219   else
 220     return io.base + (port << 7) + ((size - 1) << 5);
 221 }
 222
 223 static inline void
 224 inline_sethae (unsigned long int addr, ioswizzle_t ioswiz)
 225 {
 226   if (ioswiz == IOSWIZZLE_SPARSE)
 227     {
 228       unsigned long int msb;
 229
 230       /* no need to set hae if msb is 0: */
 231       msb = addr & 0xf8000000;
 232       if (msb && msb != io.hae_cache)
 233         {
 234           io.hae_cache = msb;
 235           __sethae (msb);
 236         }
 237     }
 238   else if (ioswiz == IOSWIZZLE_JENSEN)
 239     {
 240       /* HAE on the Jensen is bits 31:25 shifted right.  */
 241       addr >>= 25;
 242       if (addr != io.hae_cache)
 243         {
 244           io.hae_cache = addr;
 245           __sethae (addr);
 246         }
 247     }
 248 }
 249
 250 static inline void
 251 inline_outb (unsigned char b, unsigned long int port, ioswizzle_t ioswiz)
 252 {
 253   unsigned int w;
 254   unsigned long int addr = port_to_cpu_addr (port, ioswiz, 1);
 255
 256   asm ("insbl %2,%1,%0" : "=r" (w) : "ri" (port & 0x3), "r" (b));
 257   stl_mb(w, addr);
 258 }
 259
 260
 261 static inline void
 262 inline_outw (unsigned short int b, unsigned long int port, ioswizzle_t ioswiz)
 263 {
 264   unsigned long w;
 265   unsigned long int addr = port_to_cpu_addr (port, ioswiz, 2);
 266
 267   asm ("inswl %2,%1,%0" : "=r" (w) : "ri" (port & 0x3), "r" (b));
 268   stl_mb(w, addr);
 269 }
 270
 271
 272 static inline void
 273 inline_outl (unsigned int b, unsigned long int port, ioswizzle_t ioswiz)
 274 {
 275   unsigned long int addr = port_to_cpu_addr (port, ioswiz, 4);
 276
 277   stl_mb(b, addr);
 278 }
 279
 280
 281 static inline unsigned int
 282 inline_inb (unsigned long int port, ioswizzle_t ioswiz)
 283 {
 284   unsigned long int addr = port_to_cpu_addr (port, ioswiz, 1);
 285   int result;
 286
 287   result = *(vip) addr;
 288   result >>= (port & 3) * 8;
 289   return 0xffUL & result;
 290 }
 291
 292
 293 static inline unsigned int
 294 inline_inw (unsigned long int port, ioswizzle_t ioswiz)
 295 {
 296   unsigned long int addr = port_to_cpu_addr (port, ioswiz, 2);
 297   int result;
 298
 299   result = *(vip) addr;
 300   result >>= (port & 3) * 8;
 301   return 0xffffUL & result;
 302 }
 303
 304
 305 static inline unsigned int
 306 inline_inl (unsigned long int port, ioswizzle_t ioswiz)
 307 {
 308   unsigned long int addr = port_to_cpu_addr (port, ioswiz, 4);
 309
 310   return *(vuip) addr;
 311 }
 312
 313 /*
 314  * Now define the inline functions for CPUs supporting byte/word insns,
 315  * and whose core logic supports I/O space accesses utilizing them.
 316  *
 317  * These routines could be used by MIATA, for example, because it has
 318  * and EV56 plus PYXIS, but it currently uses SPARSE anyway. This is
 319  * also true of RX164 which used POLARIS, but we will choose to use
 320  * these routines in that case instead of SPARSE.
 321  *
 322  * These routines are necessary for TSUNAMI/TYPHOON based platforms,
 323  * which will have (at least) EV6.
 324  */
 325
 326 static inline unsigned long int
 327 dense_port_to_cpu_addr (unsigned long int port)
 328 {
 329   return port + io.base;
 330 }
 331
 332 static inline void
 333 inline_bwx_outb (unsigned char b, unsigned long int port)
 334 {
 335   unsigned long int addr = dense_port_to_cpu_addr (port);
 336   stb_mb (b, addr);
 337 }
 338
 339 static inline void
 340 inline_bwx_outw (unsigned short int b, unsigned long int port)
 341 {
 342   unsigned long int addr = dense_port_to_cpu_addr (port);
 343   stw_mb (b, addr);
 344 }
 345
 346 static inline void
 347 inline_bwx_outl (unsigned int b, unsigned long int port)
 348 {
 349   unsigned long int addr = dense_port_to_cpu_addr (port);
 350   stl_mb (b, addr);
 351 }
 352
 353 static inline unsigned int
 354 inline_bwx_inb (unsigned long int port)
 355 {
 356   unsigned long int addr = dense_port_to_cpu_addr (port);
 357   unsigned char r;
 358
 359   __asm__ ("ldbu %0,%1" : "=r"(r) : "m"(*(vucp)addr));
 360   return r;
 361 }
 362
 363 static inline unsigned int
 364 inline_bwx_inw (unsigned long int port)
 365 {
 366   unsigned long int addr = dense_port_to_cpu_addr (port);
 367   unsigned short r;
 368
 369   __asm__ ("ldwu %0,%1" : "=r"(r) : "m"(*(vusp)addr));
 370   return r;
 371 }
 372
 373 static inline unsigned int
 374 inline_bwx_inl (unsigned long int port)
 375 {
 376   unsigned long int addr = dense_port_to_cpu_addr (port);
 377
 378   return *(vuip) addr;
 379 }
 380
 381 /* macros to define routines with appropriate names and functions */
 382
 383 /* these do either SPARSE or JENSEN swizzle */
 384
 385 #define DCL_SETHAE(name, ioswiz)                        \
 386 static void                                             \
 387 name##_sethae (unsigned long int addr)                  \
 388 {                                                       \
 389   inline_sethae (addr, IOSWIZZLE_##ioswiz);             \
 390 }
 391
 392 #define DCL_OUT(name, func, type, ioswiz)               \
 393 static void                                             \
 394 name##_##func (unsigned type b, unsigned long int addr) \
 395 {                                                       \
 396   inline_##func (b, addr, IOSWIZZLE_##ioswiz);          \
 397 }
 398
 399 #define DCL_IN(name, func, ioswiz)                      \
 400 static unsigned int                                     \
 401 name##_##func (unsigned long int addr)                  \
 402 {                                                       \
 403   return inline_##func (addr, IOSWIZZLE_##ioswiz);      \
 404 }
 405
 406 /* these do DENSE, so no swizzle is needed */
 407
 408 #define DCL_OUT_BWX(name, func, type)                   \
 409 static void                                             \
 410 name##_##func (unsigned type b, unsigned long int addr) \
 411 {                                                       \
 412   inline_bwx_##func (b, addr);                          \
 413 }
 414
 415 #define DCL_IN_BWX(name, func)                          \
 416 static unsigned int                                     \
 417 name##_##func (unsigned long int addr)                  \
 418 {                                                       \
 419   return inline_bwx_##func (addr);                      \
 420 }
 421
 422 /* now declare/define the necessary routines */
 423
 424 DCL_SETHAE(jensen, JENSEN)
 425 DCL_OUT(jensen, outb, char,  JENSEN)
 426 DCL_OUT(jensen, outw, short int, JENSEN)
 427 DCL_OUT(jensen, outl, int,   JENSEN)
 428 DCL_IN(jensen, inb, JENSEN)
 429 DCL_IN(jensen, inw, JENSEN)
 430 DCL_IN(jensen, inl, JENSEN)
 431
 432 DCL_SETHAE(sparse, SPARSE)
 433 DCL_OUT(sparse, outb, char,  SPARSE)
 434 DCL_OUT(sparse, outw, short int, SPARSE)
 435 DCL_OUT(sparse, outl, int,   SPARSE)
 436 DCL_IN(sparse, inb, SPARSE)
 437 DCL_IN(sparse, inw, SPARSE)
 438 DCL_IN(sparse, inl, SPARSE)
 439
 440 DCL_SETHAE(dense, DENSE)
 441 DCL_OUT_BWX(dense, outb, char)
 442 DCL_OUT_BWX(dense, outw, short int)
 443 DCL_OUT_BWX(dense, outl, int)
 444 DCL_IN_BWX(dense, inb)
 445 DCL_IN_BWX(dense, inw)
 446 DCL_IN_BWX(dense, inl)
 447
 448 /* define the "swizzle" switch */
 449 static struct ioswtch ioswtch[] = {
 450   {
 451     jensen_sethae,
 452     jensen_outb, jensen_outw, jensen_outl,
 453     jensen_inb, jensen_inw, jensen_inl
 454   },
 455   {
 456     sparse_sethae,
 457     sparse_outb, sparse_outw, sparse_outl,
 458     sparse_inb, sparse_inw, sparse_inl
 459   },
 460   {
 461     dense_sethae,
 462     dense_outb, dense_outw, dense_outl,
 463     dense_inb, dense_inw, dense_inl
 464   }
 465 };
 466
 467 #undef DEBUG_IOPERM
 468
 469 /* Routine to process the /proc/cpuinfo information into the fields
 470    that are required for correctly determining the platform parameters.  */
 471
 472 struct cpuinfo_data
 473 {
 474   char systype[256];            /* system type field */
 475   char sysvari[256];            /* system variation field */
 476   char cpumodel[256];           /* cpu model field */
 477 };
 478
 479 static inline int
 480 process_cpuinfo(struct cpuinfo_data *data)
 481 {
 482   int got_type, got_vari, got_model;
 483   char dummy[256];
 484   FILE * fp;
 485   int n;
 486
 487   data->systype[0] = 0;
 488   data->sysvari[0] = 0;
 489   data->cpumodel[0] = 0;
 490
 491   /* If there's an /etc/alpha_systype link, we're intending to override
 492      whatever's in /proc/cpuinfo.  */
 493   n = __readlink (PATH_ALPHA_SYSTYPE, data->systype, 256 - 1);
 494   if (n > 0)
 495     {
 496       data->systype[n] = '\0';
 497       return 1;
 498     }
 499
 500   fp = fopen (PATH_CPUINFO, "r");
 501   if (!fp)
 502     return 0;
 503
 504   got_type = got_vari = got_model = 0;
 505
 506   while (1)
 507     {
 508       if (fgets (dummy, 256, fp) == NULL)
 509         break;
 510       if (!got_type &&
 511           sscanf (dummy, "system type : %256[^\n]\n", data->systype) == 1)
 512         got_type = 1;
 513       if (!got_vari &&
 514           sscanf (dummy, "system variation : %256[^\n]\n", data->sysvari) == 1)
 515         got_vari = 1;
 516       if (!got_model &&
 517           sscanf (dummy, "cpu model : %256[^\n]\n", data->cpumodel) == 1)
 518         got_model = 1;
 519     }
 520
 521   fclose (fp);
 522
 523 #ifdef DEBUG_IOPERM
 524   fprintf(stderr, "system type: `%s'\n", data->systype);
 525   fprintf(stderr, "system vari: `%s'\n", data->sysvari);
 526   fprintf(stderr, "cpu model: `%s'\n", data->cpumodel);
 527 #endif
 528
 529   return got_type + got_vari + got_model;
 530 }
 531
 532
 533 /*
 534  * Initialize I/O system.
 535  */
 536 static int
 537 init_iosys (void)
 538 {
 539   long addr;
 540   int i, olderrno = errno;
 541   struct cpuinfo_data data;
 542
 543   /* First try the pciconfig_iobase syscall added to 2.2.15 and 2.3.99.  */
 544
 545 #ifdef __NR_pciconfig_iobase
 546   addr = __pciconfig_iobase (IOBASE_DENSE_MEM, 0, 0);
 547   if (addr != -1)
 548     {
 549       ioswizzle_t io_swiz;
 550
 551       if (addr == 0)
 552         {
 553           /* Only Jensen doesn't have dense mem space.  */
 554           io.sparse_bus_memory_base
 555             = io_system[IOSYS_JENSEN].sparse_bus_mem_base;
 556           io.io_base = io_system[IOSYS_JENSEN].bus_io_base;
 557           io_swiz = IOSWIZZLE_JENSEN;
 558         }
 559       else
 560         {
 561           io.bus_memory_base = addr;
 562
 563           addr = __pciconfig_iobase (IOBASE_DENSE_IO, 0, 0);
 564           if (addr != 0)
 565             {
 566               /* The X server uses _bus_base_sparse == 0 to know that
 567                  BWX access are supported to dense mem space.  This is
 568                  true of every system that supports dense io space, so
 569                  never fill in io.sparse_bus_memory_base in this case.  */
 570               io_swiz = IOSWIZZLE_DENSE;
 571               io.io_base = addr;
 572             }
 573           else
 574             {
 575               io.sparse_bus_memory_base
 576                 = __pciconfig_iobase (IOBASE_SPARSE_MEM, 0, 0);
 577               io.io_base = __pciconfig_iobase (IOBASE_SPARSE_IO, 0, 0);
 578               io_swiz = IOSWIZZLE_SPARSE;
 579             }
 580         }
 581
 582       io.swiz = io_swiz;
 583       io.swp = &ioswtch[io_swiz];
 584
 585       return 0;
 586     }
 587 #endif
 588
 589   /* Second, collect the contents of /etc/alpha_systype or /proc/cpuinfo.  */
 590
 591   if (process_cpuinfo(&data) == 0)
 592     {
 593       /* This can happen if the format of /proc/cpuinfo changes.  */
 594       fprintf (stderr,
 595                "ioperm.init_iosys: Unable to determine system type.\n"
 596                "\t(May need " PATH_ALPHA_SYSTYPE " symlink?)\n");
 597       __set_errno (ENODEV);
 598       return -1;
 599     }
 600
 601   /* Translate systype name into i/o system.  */
 602   for (i = 0; i < sizeof (platform) / sizeof (platform[0]); ++i)
 603     {
 604       if (strcmp (platform[i].name, data.systype) == 0)
 605         {
 606           iosys_t io_sys = platform[i].io_sys;
 607
 608           /* Some platforms can have either EV4 or EV5 CPUs.  */
 609           if (io_sys == IOSYS_CPUDEP)
 610             {
 611               /* SABLE or MIKASA or NORITAKE so far.  */
 612               if (strcmp (platform[i].name, "Sable") == 0)
 613                 {
 614                   if (strncmp (data.cpumodel, "EV4", 3) == 0)
 615                     io_sys = IOSYS_T2;
 616                   else if (strncmp (data.cpumodel, "EV5", 3) == 0)
 617                     io_sys = IOSYS_GAMMA;
 618                 }
 619               else
 620                 {
 621                   /* This covers MIKASA/NORITAKE.  */
 622                   if (strncmp (data.cpumodel, "EV4", 3) == 0)
 623                     io_sys = IOSYS_APECS;
 624                   else if (strncmp (data.cpumodel, "EV5", 3) == 0)
 625                     io_sys = IOSYS_CIA;
 626                 }
 627               if (io_sys == IOSYS_CPUDEP)
 628                 {
 629                   /* This can happen if the format of /proc/cpuinfo changes.*/
 630                   fprintf (stderr, "ioperm.init_iosys: Unable to determine"
 631                            " CPU model.\n");
 632                   __set_errno (ENODEV);
 633                   return -1;
 634                 }
 635             }
 636           /* Some platforms can have different core logic chipsets */
 637           if (io_sys == IOSYS_PCIDEP)
 638             {
 639               /* EB164 so far */
 640               if (strcmp (data.systype, "EB164") == 0)
 641                 {
 642                   if (strncmp (data.sysvari, "RX164", 5) == 0)
 643                     io_sys = IOSYS_POLARIS;
 644                   else if (strncmp (data.sysvari, "LX164", 5) == 0
 645                            || strncmp (data.sysvari, "SX164", 5) == 0)
 646                     io_sys = IOSYS_PYXIS;
 647                   else
 648                     io_sys = IOSYS_CIA;
 649                 }
 650               if (io_sys == IOSYS_PCIDEP)
 651                 {
 652                   /* This can happen if the format of /proc/cpuinfo changes.*/
 653                   fprintf (stderr, "ioperm.init_iosys: Unable to determine"
 654                            " core logic chipset.\n");
 655                   __set_errno (ENODEV);
 656                   return -1;
 657                 }
 658             }
 659           io.bus_memory_base = io_system[io_sys].bus_memory_base;
 660           io.sparse_bus_memory_base = io_system[io_sys].sparse_bus_mem_base;
 661           io.io_base = io_system[io_sys].bus_io_base;
 662
 663           if (io_sys == IOSYS_JENSEN)
 664             io.swiz = IOSWIZZLE_JENSEN;
 665           else if (io_sys == IOSYS_TSUNAMI
 666                    || io_sys == IOSYS_POLARIS
 667                    || io_sys == IOSYS_PYXIS)
 668             io.swiz = IOSWIZZLE_DENSE;
 669           else
 670             io.swiz = IOSWIZZLE_SPARSE;
 671           io.swp = &ioswtch[io.swiz];
 672
 673           __set_errno (olderrno);
 674           return 0;
 675         }
 676     }
 677
 678   __set_errno (ENODEV);
 679   fprintf(stderr, "ioperm.init_iosys: Platform not recognized.\n"
 680           "\t(May need " PATH_ALPHA_SYSTYPE " symlink?)\n");
 681   return -1;
 682 }
 683
 684
 685 int
 686 _ioperm (unsigned long int from, unsigned long int num, int turn_on)
 687 {
 688   unsigned long int addr, len, pagesize = __getpagesize();
 689   int prot;
 690
 691   if (!io.swp && init_iosys() < 0)
 692     {
 693 #ifdef DEBUG_IOPERM
 694       fprintf(stderr, "ioperm: init_iosys() failed (%m)\n");
 695 #endif
 696       return -1;
 697     }
 698
 699   /* This test isn't as silly as it may look like; consider overflows! */
 700   if (from >= MAX_PORT || from + num > MAX_PORT)
 701     {
 702       __set_errno (EINVAL);
 703 #ifdef DEBUG_IOPERM
 704       fprintf(stderr, "ioperm: from/num out of range\n");
 705 #endif
 706       return -1;
 707     }
 708
 709 #ifdef DEBUG_IOPERM
 710   fprintf(stderr, "ioperm: turn_on %d io.base %ld\n", turn_on, io.base);
 711 #endif
 712
 713   if (turn_on)
 714     {
 715       if (!io.base)
 716         {
 717           int fd;
 718
 719           io.hae_cache = 0;
 720           if (io.swiz != IOSWIZZLE_DENSE)
 721             {
 722               /* Synchronize with hw.  */
 723               __sethae (0);
 724             }
 725
 726           fd = __open ("/dev/mem", O_RDWR);
 727           if (fd < 0)
 728             {
 729 #ifdef DEBUG_IOPERM
 730               fprintf(stderr, "ioperm: /dev/mem open failed (%m)\n");
 731 #endif
 732               return -1;
 733             }
 734
 735           addr = port_to_cpu_addr (0, io.swiz, 1);
 736           len = port_to_cpu_addr (MAX_PORT, io.swiz, 1) - addr;
 737           io.base =
 738             (unsigned long int) __mmap (0, len, PROT_NONE, MAP_SHARED,
 739                                         fd, io.io_base);
 740           __close (fd);
 741 #ifdef DEBUG_IOPERM
 742           fprintf(stderr, "ioperm: mmap of len 0x%lx  returned 0x%lx\n",
 743                   len, io.base);
 744 #endif
 745           if ((long) io.base == -1)
 746             return -1;
 747         }
 748       prot = PROT_READ | PROT_WRITE;
 749     }
 750   else
 751     {
 752       if (!io.base)
 753         return 0;       /* never was turned on... */
 754
 755       /* turnoff access to relevant pages: */
 756       prot = PROT_NONE;
 757     }
 758   addr = port_to_cpu_addr (from, io.swiz, 1);
 759   addr &= ~(pagesize - 1);
 760   len = port_to_cpu_addr (from + num, io.swiz, 1) - addr;
 761   return __mprotect ((void *) addr, len, prot);
 762 }
 763
 764
 765 int
 766 _iopl (int level)
 767 {
 768   switch (level)
 769     {
 770     case 0:
 771       return 0;
 772
 773     case 1: case 2: case 3:
 774       return _ioperm (0, MAX_PORT, 1);
 775
 776     default:
 777       __set_errno (EINVAL);
 778       return -1;
 779     }
 780 }
 781
 782
 783 void
 784 _sethae (unsigned long int addr)
 785 {
 786   if (!io.swp && init_iosys () < 0)
 787     return;
 788
 789   io.swp->sethae (addr);
 790 }
 791
 792
 793 void
 794 _outb (unsigned char b, unsigned long int port)
 795 {
 796   if (port >= MAX_PORT)
 797     return;
 798
 799   io.swp->outb (b, port);
 800 }
 801
 802
 803 void
 804 _outw (unsigned short b, unsigned long int port)
 805 {
 806   if (port >= MAX_PORT)
 807     return;
 808
 809   io.swp->outw (b, port);
 810 }
 811
 812
 813 void
 814 _outl (unsigned int b, unsigned long int port)
 815 {
 816   if (port >= MAX_PORT)
 817     return;
 818
 819   io.swp->outl (b, port);
 820 }
 821
 822
 823 unsigned int
 824 _inb (unsigned long int port)
 825 {
 826   return io.swp->inb (port);
 827 }
 828
 829
 830 unsigned int
 831 _inw (unsigned long int port)
 832 {
 833   return io.swp->inw (port);
 834 }
 835
 836
 837 unsigned int
 838 _inl (unsigned long int port)
 839 {
 840   return io.swp->inl (port);
 841 }
 842
 843
 844 unsigned long int
 845 _bus_base(void)
 846 {
 847   if (!io.swp && init_iosys () < 0)
 848     return -1;
 849   return io.bus_memory_base;
 850 }
 851
 852 unsigned long int
 853 _bus_base_sparse(void)
 854 {
 855   if (!io.swp && init_iosys () < 0)
 856     return -1;
 857   return io.sparse_bus_memory_base;
 858 }
 859
 860 int
 861 _hae_shift(void)
 862 {
 863   if (!io.swp && init_iosys () < 0)
 864     return -1;
 865   if (io.swiz == IOSWIZZLE_JENSEN)
 866     return 7;
 867   if (io.swiz == IOSWIZZLE_SPARSE)
 868     return 5;
 869   return 0;
 870 }
 871
 872 weak_alias (_sethae, sethae);
 873 weak_alias (_ioperm, ioperm);
 874 weak_alias (_iopl, iopl);
 875 weak_alias (_inb, inb);
 876 weak_alias (_inw, inw);
 877 weak_alias (_inl, inl);
 878 weak_alias (_outb, outb);
 879 weak_alias (_outw, outw);
 880 weak_alias (_outl, outl);
 881 weak_alias (_bus_base, bus_base);
 882 weak_alias (_bus_base_sparse, bus_base_sparse);
 883 weak_alias (_hae_shift, hae_shift);