(ELF_MACHINE_NO_RELA): Define unconditionally to defined RTLD_BOOTSTRAP.
[glibc-ports.git] / sysdeps / hppa / hppa1.1 / mul_1.s
blob00c770f27230b2e1d2ba1b05eb5a7bea652ad6f9
1 ;! HP-PA-1.1 __mpn_mul_1 -- Multiply a limb vector with a limb and store
2 ;! the result in a second limb vector.
4 ;! Copyright (C) 1992, 1993, 1994 Free Software Foundation, Inc.
6 ;! This file is part of the GNU MP Library.
8 ;! The GNU MP Library is free software; you can redistribute it and/or modify
9 ;! it under the terms of the GNU Lesser General Public License as published by
10 ;! the Free Software Foundation; either version 2.1 of the License, or (at your
11 ;! option) any later version.
13 ;! The GNU MP Library is distributed in the hope that it will be useful, but
14 ;! WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 ;! or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
16 ;! License for more details.
18 ;! You should have received a copy of the GNU Lesser General Public License
19 ;! along with the GNU MP Library; see the file COPYING.LIB. If not, write to
20 ;! the Free Software Foundation, Inc., 59 Temple Place - Suite 330, Boston,
21 ;! MA 02111-1307, USA.
24 ;! INPUT PARAMETERS
25 ;! res_ptr r26
26 ;! s1_ptr r25
27 ;! size r24
28 ;! s2_limb r23
30 ;! This runs at 9 cycles/limb on a PA7000. With the used instructions, it can
31 ;! not become faster due to data cache contention after a store. On the
32 ;! PA7100 it runs at 7 cycles/limb, and that can not be improved either, since
33 ;! only the xmpyu does not need the integer pipeline, so the only dual-issue
34 ;! we will get are addc+xmpyu. Unrolling would not help either CPU.
36 ;! We could use fldds to read two limbs at a time from the S1 array, and that
37 ;! could bring down the times to 8.5 and 6.5 cycles/limb for the PA7000 and
38 ;! PA7100, respectively. We don't do that since it does not seem worth the
39 ;! (alignment) troubles...
41 ;! At least the PA7100 is rumored to be able to deal with cache-misses
42 ;! without stalling instruction issue. If this is true, and the cache is
43 ;! actually also lockup-free, we should use a deeper software pipeline, and
44 ;! load from S1 very early; (The loads and stores to -12(sp) will surely be
45 ;! in the cache.)
47 .text
48 .export __mpn_mul_1
49 __mpn_mul_1:
50 .proc
51 .callinfo frame=64,no_calls
52 .entry
54 ldo 64(%r30),%r30
55 fldws,ma 4(%r25),%fr5
56 stw %r23,-16(%r30) ;! move s2_limb ...
57 addib,= -1,%r24,L$just_one_limb
58 fldws -16(%r30),%fr4 ;! ... into fr4
59 add %r0,%r0,%r0 ;! clear carry
60 xmpyu %fr4,%fr5,%fr6
61 fldws,ma 4(%r25),%fr7
62 fstds %fr6,-16(%r30)
63 xmpyu %fr4,%fr7,%fr8
64 ldw -12(%r30),%r20 ;! least significant limb in product
65 ldw -16(%r30),%r28
67 fstds %fr8,-16(%r30)
68 addib,= -1,%r24,L$end
69 ldw -12(%r30),%r1
71 ;! Main loop
72 L$loop:
73 fldws,ma 4(%r25),%fr5
74 stws,ma %r20,4(%r26)
75 addc %r28,%r1,%r20
76 xmpyu %fr4,%fr5,%fr6
77 ldw -16(%r30),%r28
78 fstds %fr6,-16(%r30)
79 addib,<> -1,%r24,L$loop
80 ldw -12(%r30),%r1
82 L$end:
83 stws,ma %r20,4(%r26)
84 addc %r28,%r1,%r20
85 ldw -16(%r30),%r28
86 stws,ma %r20,4(%r26)
87 addc %r0,%r28,%r28
88 bv 0(%r2)
89 ldo -64(%r30),%r30
91 L$just_one_limb:
92 xmpyu %fr4,%fr5,%fr6
93 fstds %fr6,-16(%r30)
94 ldw -16(%r30),%r28
95 ldo -64(%r30),%r30
96 bv 0(%r2)
97 fstws %fr6R,0(%r26)
99 .exit
100 .procend