2006-01-10 Roland McGrath <roland@redhat.com>
[glibc-ports.git] / sysdeps / am33 / fpu / fpu_control.h
blobc0612ba53c5fa640f292cb10e70048bce10dca1b
1 /* FPU control word bits. AM33/2.0 version.
2 Copyright (C) 1996, 1997, 1998, 1999, 2000, 2004
3 Free Software Foundation, Inc.
4 This file is part of the GNU C Library.
5 Contributed by Alexandre Oliva <aoliva@redhat.com>
6 based on the corresponding file in the mips port.
8 The GNU C Library is free software; you can redistribute it and/or
9 modify it under the terms of the GNU Lesser General Public
10 License as published by the Free Software Foundation; either
11 version 2.1 of the License, or (at your option) any later version.
13 The GNU C Library is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 Lesser General Public License for more details.
18 You should have received a copy of the GNU Lesser General Public
19 License along with the GNU C Library; if not, write to the Free
20 Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
21 02111-1307 USA. */
23 #ifndef _FPU_CONTROL_H
24 #define _FPU_CONTROL_H
26 /* AM33/2.0 FPU floating point control register bits.
28 * 31-22 -> reserved
29 * 21-18 -> floating-point condition codes (L, G, E, U)
30 * 17-16 -> rounding modes (00 is to-nearest; other values are reserved
31 * 15 -> reserved (read as 0, write with 0)
32 * 14-10 -> Exception Cause (inValid, divZero, Overflow, Underflow, Inexact)
33 * 9- 5 -> Exception Enable
34 * 4- 0 -> Exception Flag, cleared when exception cause is set
37 #include <features.h>
38 #include <fenv.h>
40 /* masking of interrupts */
41 #define _FPU_MASK_V 0x0200 /* Invalid operation */
42 #define _FPU_MASK_Z 0x0100 /* Division by zero */
43 #define _FPU_MASK_O 0x0080 /* Overflow */
44 #define _FPU_MASK_U 0x0040 /* Underflow */
45 #define _FPU_MASK_I 0x0020 /* Inexact operation */
47 /* rounding control */
48 #define _FPU_RC_NEAREST 0x0 /* Only available mode */
50 #define _FPU_RESERVED 0xffc08000 /* Reserved bits in fpcr */
53 /* The fdlibm code requires strict IEEE double precision arithmetic,
54 and no interrupts for exceptions, rounding to nearest. */
56 #define _FPU_DEFAULT 0x0000001f
58 /* IEEE: same as above, but exceptions */
59 #define _FPU_IEEE 0x000003ff
61 /* Type of the control word. */
62 typedef unsigned int fpu_control_t;
64 /* Macros for accessing the hardware control word. _FPU_SETCW is
65 defined such that it won't modify the EF bits, that are cleared
66 when assigned bits that are set. Use SETFCW to get them actually
67 reset. */
68 #define _FPU_SETFCW(cw) __asm__ ("fmov %0,fpcr" : : "ri" (cw))
69 #define _FPU_SETCW(cw) _FPU_SETFCW((cw) & ~FE_ALL_EXCEPT)
70 #define _FPU_GETCW(cw) __asm__ ("fmov fpcr,%0" : "=r" (cw))
72 /* Default control word set at startup. */
73 extern fpu_control_t __fpu_control;
75 #endif /* fpu_control.h */