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xdrmem_setpos): Don't compare addresses as signed longs, check for
[glibc/history.git] / stdlib / longlong.h
blobca6285a19b1a1b84d2cd470e9a8488e4b5dc4e91
1 /* longlong.h -- definitions for mixed size 32/64 bit arithmetic.
2 Copyright (C) 1991, 1992, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 2002, 2003, 2004, 2005, 2006 Free Software Foundation, Inc.
4
5 This file is part of the GNU C Library.
6
7 The GNU C Library is free software; you can redistribute it and/or
8 modify it under the terms of the GNU Lesser General Public
9 License as published by the Free Software Foundation; either
10 version 2.1 of the License, or (at your option) any later version.
11
12 The GNU C Library is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 Lesser General Public License for more details.
16
17 You should have received a copy of the GNU Lesser General Public
18 License along with the GNU C Library; if not, write to the Free
19 Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
20 02111-1307 USA. */
21
22 /* You have to define the following before including this file:
23
24 UWtype -- An unsigned type, default type for operations (typically a "word")
25 UHWtype -- An unsigned type, at least half the size of UWtype.
26 UDWtype -- An unsigned type, at least twice as large a UWtype
27 W_TYPE_SIZE -- size in bits of UWtype
28
29 UQItype -- Unsigned 8 bit type.
30 SItype, USItype -- Signed and unsigned 32 bit types.
31 DItype, UDItype -- Signed and unsigned 64 bit types.
32
33 On a 32 bit machine UWtype should typically be USItype;
34 on a 64 bit machine, UWtype should typically be UDItype. */
35
36 #define __BITS4 (W_TYPE_SIZE / 4)
37 #define __ll_B ((UWtype) 1 << (W_TYPE_SIZE / 2))
38 #define __ll_lowpart(t) ((UWtype) (t) & (__ll_B - 1))
39 #define __ll_highpart(t) ((UWtype) (t) >> (W_TYPE_SIZE / 2))
40
41 #ifndef W_TYPE_SIZE
42 #define W_TYPE_SIZE 32
43 #define UWtype USItype
44 #define UHWtype USItype
45 #define UDWtype UDItype
46 #endif
47
48 extern const UQItype __clz_tab[256] attribute_hidden;
49
50 /* Define auxiliary asm macros.
51
52 1) umul_ppmm(high_prod, low_prod, multiplier, multiplicand) multiplies two
53 UWtype integers MULTIPLIER and MULTIPLICAND, and generates a two UWtype
54 word product in HIGH_PROD and LOW_PROD.
55
56 2) __umulsidi3(a,b) multiplies two UWtype integers A and B, and returns a
57 UDWtype product. This is just a variant of umul_ppmm.
58
59 3) udiv_qrnnd(quotient, remainder, high_numerator, low_numerator,
60 denominator) divides a UDWtype, composed by the UWtype integers
61 HIGH_NUMERATOR and LOW_NUMERATOR, by DENOMINATOR and places the quotient
62 in QUOTIENT and the remainder in REMAINDER. HIGH_NUMERATOR must be less
63 than DENOMINATOR for correct operation. If, in addition, the most
64 significant bit of DENOMINATOR must be 1, then the pre-processor symbol
65 UDIV_NEEDS_NORMALIZATION is defined to 1.
66
67 4) sdiv_qrnnd(quotient, remainder, high_numerator, low_numerator,
68 denominator). Like udiv_qrnnd but the numbers are signed. The quotient
69 is rounded towards 0.
70
71 5) count_leading_zeros(count, x) counts the number of zero-bits from the
72 msb to the first nonzero bit in the UWtype X. This is the number of
73 steps X needs to be shifted left to set the msb. Undefined for X == 0,
74 unless the symbol COUNT_LEADING_ZEROS_0 is defined to some value.
75
76 6) count_trailing_zeros(count, x) like count_leading_zeros, but counts
77 from the least significant end.
78
79 7) add_ssaaaa(high_sum, low_sum, high_addend_1, low_addend_1,
80 high_addend_2, low_addend_2) adds two UWtype integers, composed by
81 HIGH_ADDEND_1 and LOW_ADDEND_1, and HIGH_ADDEND_2 and LOW_ADDEND_2
82 respectively. The result is placed in HIGH_SUM and LOW_SUM. Overflow
83 (i.e. carry out) is not stored anywhere, and is lost.
84
85 8) sub_ddmmss(high_difference, low_difference, high_minuend, low_minuend,
86 high_subtrahend, low_subtrahend) subtracts two two-word UWtype integers,
87 composed by HIGH_MINUEND_1 and LOW_MINUEND_1, and HIGH_SUBTRAHEND_2 and
88 LOW_SUBTRAHEND_2 respectively. The result is placed in HIGH_DIFFERENCE
89 and LOW_DIFFERENCE. Overflow (i.e. carry out) is not stored anywhere,
90 and is lost.
91
92 If any of these macros are left undefined for a particular CPU,
93 C macros are used. */
94
95 /* The CPUs come in alphabetical order below.
96
97 Please add support for more CPUs here, or improve the current support
98 for the CPUs below!
99 (E.g. WE32100, IBM360.) */
100
101 #if defined (__GNUC__) && !defined (NO_ASM)
102
103 /* We sometimes need to clobber "cc" with gcc2, but that would not be
104 understood by gcc1. Use cpp to avoid major code duplication. */
105 #if __GNUC__ < 2
106 #define __CLOBBER_CC
107 #define __AND_CLOBBER_CC
108 #else /* __GNUC__ >= 2 */
109 #define __CLOBBER_CC : "cc"
110 #define __AND_CLOBBER_CC , "cc"
111 #endif /* __GNUC__ < 2 */
112
113 #if defined (__alpha) && W_TYPE_SIZE == 64
114 #define umul_ppmm(ph, pl, m0, m1) \
115 do { \
116 UDItype __m0 = (m0), __m1 = (m1); \
117 (ph) = __builtin_alpha_umulh (__m0, __m1); \
118 (pl) = __m0 * __m1; \
119 } while (0)
120 #define UMUL_TIME 46
121 #ifndef LONGLONG_STANDALONE
122 #define udiv_qrnnd(q, r, n1, n0, d) \
123 do { UDItype __r; \
124 (q) = __udiv_qrnnd (&__r, (n1), (n0), (d)); \
125 (r) = __r; \
126 } while (0)
127 extern UDItype __udiv_qrnnd (UDItype *, UDItype, UDItype, UDItype);
128 #define UDIV_TIME 220
129 #endif /* LONGLONG_STANDALONE */
130 #ifdef __alpha_cix__
131 #define count_leading_zeros(COUNT,X) ((COUNT) = __builtin_clzl (X))
132 #define count_trailing_zeros(COUNT,X) ((COUNT) = __builtin_ctzl (X))
133 #define COUNT_LEADING_ZEROS_0 64
134 #else
135 #define count_leading_zeros(COUNT,X) \
136 do { \
137 UDItype __xr = (X), __t, __a; \
138 __t = __builtin_alpha_cmpbge (0, __xr); \
139 __a = __clz_tab[__t ^ 0xff] - 1; \
140 __t = __builtin_alpha_extbl (__xr, __a); \
141 (COUNT) = 64 - (__clz_tab[__t] + __a*8); \
142 } while (0)
143 #define count_trailing_zeros(COUNT,X) \
144 do { \
145 UDItype __xr = (X), __t, __a; \
146 __t = __builtin_alpha_cmpbge (0, __xr); \
147 __t = ~__t & -~__t; \
148 __a = ((__t & 0xCC) != 0) * 2; \
149 __a += ((__t & 0xF0) != 0) * 4; \
150 __a += ((__t & 0xAA) != 0); \
151 __t = __builtin_alpha_extbl (__xr, __a); \
152 __a <<= 3; \
153 __t &= -__t; \
154 __a += ((__t & 0xCC) != 0) * 2; \
155 __a += ((__t & 0xF0) != 0) * 4; \
156 __a += ((__t & 0xAA) != 0); \
157 (COUNT) = __a; \
158 } while (0)
159 #endif /* __alpha_cix__ */
160 #endif /* __alpha */
161
162 #if defined (__arc__) && W_TYPE_SIZE == 32
163 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
164 __asm__ ("add.f %1, %4, %5\n\tadc %0, %2, %3" \
165 : "=r" ((USItype) (sh)), \
166 "=&r" ((USItype) (sl)) \
167 : "%r" ((USItype) (ah)), \
168 "rIJ" ((USItype) (bh)), \
169 "%r" ((USItype) (al)), \
170 "rIJ" ((USItype) (bl)))
171 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
172 __asm__ ("sub.f %1, %4, %5\n\tsbc %0, %2, %3" \
173 : "=r" ((USItype) (sh)), \
174 "=&r" ((USItype) (sl)) \
175 : "r" ((USItype) (ah)), \
176 "rIJ" ((USItype) (bh)), \
177 "r" ((USItype) (al)), \
178 "rIJ" ((USItype) (bl)))
179 /* Call libgcc routine. */
180 #define umul_ppmm(w1, w0, u, v) \
181 do { \
182 DWunion __w; \
183 __w.ll = __umulsidi3 (u, v); \
184 w1 = __w.s.high; \
185 w0 = __w.s.low; \
186 } while (0)
187 #define __umulsidi3 __umulsidi3
188 UDItype __umulsidi3 (USItype, USItype);
189 #endif
190
191 #if defined (__arm__) && !defined (__thumb__) && W_TYPE_SIZE == 32
192 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
193 __asm__ ("adds %1, %4, %5\n\tadc %0, %2, %3" \
194 : "=r" ((USItype) (sh)), \
195 "=&r" ((USItype) (sl)) \
196 : "%r" ((USItype) (ah)), \
197 "rI" ((USItype) (bh)), \
198 "%r" ((USItype) (al)), \
199 "rI" ((USItype) (bl)) __CLOBBER_CC)
200 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
201 __asm__ ("subs %1, %4, %5\n\tsbc %0, %2, %3" \
202 : "=r" ((USItype) (sh)), \
203 "=&r" ((USItype) (sl)) \
204 : "r" ((USItype) (ah)), \
205 "rI" ((USItype) (bh)), \
206 "r" ((USItype) (al)), \
207 "rI" ((USItype) (bl)) __CLOBBER_CC)
208 #define umul_ppmm(xh, xl, a, b) \
209 {register USItype __t0, __t1, __t2; \
210 __asm__ ("%@ Inlined umul_ppmm\n" \
211 " mov %2, %5, lsr #16\n" \
212 " mov %0, %6, lsr #16\n" \
213 " bic %3, %5, %2, lsl #16\n" \
214 " bic %4, %6, %0, lsl #16\n" \
215 " mul %1, %3, %4\n" \
216 " mul %4, %2, %4\n" \
217 " mul %3, %0, %3\n" \
218 " mul %0, %2, %0\n" \
219 " adds %3, %4, %3\n" \
220 " addcs %0, %0, #65536\n" \
221 " adds %1, %1, %3, lsl #16\n" \
222 " adc %0, %0, %3, lsr #16" \
223 : "=&r" ((USItype) (xh)), \
224 "=r" ((USItype) (xl)), \
225 "=&r" (__t0), "=&r" (__t1), "=r" (__t2) \
226 : "r" ((USItype) (a)), \
227 "r" ((USItype) (b)) __CLOBBER_CC );}
228 #define UMUL_TIME 20
229 #define UDIV_TIME 100
230 #endif /* __arm__ */
231
232 #if defined (__hppa) && W_TYPE_SIZE == 32
233 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
234 __asm__ ("add %4,%5,%1\n\taddc %2,%3,%0" \
235 : "=r" ((USItype) (sh)), \
236 "=&r" ((USItype) (sl)) \
237 : "%rM" ((USItype) (ah)), \
238 "rM" ((USItype) (bh)), \
239 "%rM" ((USItype) (al)), \
240 "rM" ((USItype) (bl)))
241 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
242 __asm__ ("sub %4,%5,%1\n\tsubb %2,%3,%0" \
243 : "=r" ((USItype) (sh)), \
244 "=&r" ((USItype) (sl)) \
245 : "rM" ((USItype) (ah)), \
246 "rM" ((USItype) (bh)), \
247 "rM" ((USItype) (al)), \
248 "rM" ((USItype) (bl)))
249 #if defined (_PA_RISC1_1)
250 #define umul_ppmm(w1, w0, u, v) \
251 do { \
252 union \
253 { \
254 UDItype __f; \
255 struct {USItype __w1, __w0;} __w1w0; \
256 } __t; \
257 __asm__ ("xmpyu %1,%2,%0" \
258 : "=x" (__t.__f) \
259 : "x" ((USItype) (u)), \
260 "x" ((USItype) (v))); \
261 (w1) = __t.__w1w0.__w1; \
262 (w0) = __t.__w1w0.__w0; \
263 } while (0)
264 #define UMUL_TIME 8
265 #else
266 #define UMUL_TIME 30
267 #endif
268 #define UDIV_TIME 40
269 #define count_leading_zeros(count, x) \
270 do { \
271 USItype __tmp; \
272 __asm__ ( \
273 "ldi 1,%0\n" \
274 " extru,= %1,15,16,%%r0 ; Bits 31..16 zero?\n" \
275 " extru,tr %1,15,16,%1 ; No. Shift down, skip add.\n"\
276 " ldo 16(%0),%0 ; Yes. Perform add.\n" \
277 " extru,= %1,23,8,%%r0 ; Bits 15..8 zero?\n" \
278 " extru,tr %1,23,8,%1 ; No. Shift down, skip add.\n"\
279 " ldo 8(%0),%0 ; Yes. Perform add.\n" \
280 " extru,= %1,27,4,%%r0 ; Bits 7..4 zero?\n" \
281 " extru,tr %1,27,4,%1 ; No. Shift down, skip add.\n"\
282 " ldo 4(%0),%0 ; Yes. Perform add.\n" \
283 " extru,= %1,29,2,%%r0 ; Bits 3..2 zero?\n" \
284 " extru,tr %1,29,2,%1 ; No. Shift down, skip add.\n"\
285 " ldo 2(%0),%0 ; Yes. Perform add.\n" \
286 " extru %1,30,1,%1 ; Extract bit 1.\n" \
287 " sub %0,%1,%0 ; Subtract it.\n" \
288 : "=r" (count), "=r" (__tmp) : "1" (x)); \
289 } while (0)
290 #endif
291
292 #if (defined (__i370__) || defined (__s390__) || defined (__mvs__)) && W_TYPE_SIZE == 32
293 #define smul_ppmm(xh, xl, m0, m1) \
294 do { \
295 union {DItype __ll; \
296 struct {USItype __h, __l;} __i; \
297 } __x; \
298 __asm__ ("lr %N0,%1\n\tmr %0,%2" \
299 : "=&r" (__x.__ll) \
300 : "r" (m0), "r" (m1)); \
301 (xh) = __x.__i.__h; (xl) = __x.__i.__l; \
302 } while (0)
303 #define sdiv_qrnnd(q, r, n1, n0, d) \
304 do { \
305 union {DItype __ll; \
306 struct {USItype __h, __l;} __i; \
307 } __x; \
308 __x.__i.__h = n1; __x.__i.__l = n0; \
309 __asm__ ("dr %0,%2" \
310 : "=r" (__x.__ll) \
311 : "0" (__x.__ll), "r" (d)); \
312 (q) = __x.__i.__l; (r) = __x.__i.__h; \
313 } while (0)
314 #endif
315
316 #if (defined (__i386__) || defined (__i486__)) && W_TYPE_SIZE == 32
317 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
318 __asm__ ("addl %5,%1\n\tadcl %3,%0" \
319 : "=r" ((USItype) (sh)), \
320 "=&r" ((USItype) (sl)) \
321 : "%0" ((USItype) (ah)), \
322 "g" ((USItype) (bh)), \
323 "%1" ((USItype) (al)), \
324 "g" ((USItype) (bl)))
325 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
326 __asm__ ("subl %5,%1\n\tsbbl %3,%0" \
327 : "=r" ((USItype) (sh)), \
328 "=&r" ((USItype) (sl)) \
329 : "0" ((USItype) (ah)), \
330 "g" ((USItype) (bh)), \
331 "1" ((USItype) (al)), \
332 "g" ((USItype) (bl)))
333 #define umul_ppmm(w1, w0, u, v) \
334 __asm__ ("mull %3" \
335 : "=a" ((USItype) (w0)), \
336 "=d" ((USItype) (w1)) \
337 : "%0" ((USItype) (u)), \
338 "rm" ((USItype) (v)))
339 #define udiv_qrnnd(q, r, n1, n0, dv) \
340 __asm__ ("divl %4" \
341 : "=a" ((USItype) (q)), \
342 "=d" ((USItype) (r)) \
343 : "0" ((USItype) (n0)), \
344 "1" ((USItype) (n1)), \
345 "rm" ((USItype) (dv)))
346 #define count_leading_zeros(count, x) \
347 do { \
348 USItype __cbtmp; \
349 __asm__ ("bsrl %1,%0" \
350 : "=r" (__cbtmp) : "rm" ((USItype) (x))); \
351 (count) = __cbtmp ^ 31; \
352 } while (0)
353 #define count_trailing_zeros(count, x) \
354 __asm__ ("bsfl %1,%0" : "=r" (count) : "rm" ((USItype)(x)))
355 #define UMUL_TIME 40
356 #define UDIV_TIME 40
357 #endif /* 80x86 */
358
359 #if defined (__i960__) && W_TYPE_SIZE == 32
360 #define umul_ppmm(w1, w0, u, v) \
361 ({union {UDItype __ll; \
362 struct {USItype __l, __h;} __i; \
363 } __xx; \
364 __asm__ ("emul %2,%1,%0" \
365 : "=d" (__xx.__ll) \
366 : "%dI" ((USItype) (u)), \
367 "dI" ((USItype) (v))); \
368 (w1) = __xx.__i.__h; (w0) = __xx.__i.__l;})
369 #define __umulsidi3(u, v) \
370 ({UDItype __w; \
371 __asm__ ("emul %2,%1,%0" \
372 : "=d" (__w) \
373 : "%dI" ((USItype) (u)), \
374 "dI" ((USItype) (v))); \
375 __w; })
376 #endif /* __i960__ */
377
378 #if defined (__M32R__) && W_TYPE_SIZE == 32
379 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
380 /* The cmp clears the condition bit. */ \
381 __asm__ ("cmp %0,%0\n\taddx %1,%5\n\taddx %0,%3" \
382 : "=r" ((USItype) (sh)), \
383 "=&r" ((USItype) (sl)) \
384 : "0" ((USItype) (ah)), \
385 "r" ((USItype) (bh)), \
386 "1" ((USItype) (al)), \
387 "r" ((USItype) (bl)) \
388 : "cbit")
389 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
390 /* The cmp clears the condition bit. */ \
391 __asm__ ("cmp %0,%0\n\tsubx %1,%5\n\tsubx %0,%3" \
392 : "=r" ((USItype) (sh)), \
393 "=&r" ((USItype) (sl)) \
394 : "0" ((USItype) (ah)), \
395 "r" ((USItype) (bh)), \
396 "1" ((USItype) (al)), \
397 "r" ((USItype) (bl)) \
398 : "cbit")
399 #endif /* __M32R__ */
400
401 #if defined (__mc68000__) && W_TYPE_SIZE == 32
402 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
403 __asm__ ("add%.l %5,%1\n\taddx%.l %3,%0" \
404 : "=d" ((USItype) (sh)), \
405 "=&d" ((USItype) (sl)) \
406 : "%0" ((USItype) (ah)), \
407 "d" ((USItype) (bh)), \
408 "%1" ((USItype) (al)), \
409 "g" ((USItype) (bl)))
410 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
411 __asm__ ("sub%.l %5,%1\n\tsubx%.l %3,%0" \
412 : "=d" ((USItype) (sh)), \
413 "=&d" ((USItype) (sl)) \
414 : "0" ((USItype) (ah)), \
415 "d" ((USItype) (bh)), \
416 "1" ((USItype) (al)), \
417 "g" ((USItype) (bl)))
418
419 /* The '020, '030, '040, '060 and CPU32 have 32x32->64 and 64/32->32q-32r. */
420 #if (defined (__mc68020__) && !defined (__mc68060__))
421 #define umul_ppmm(w1, w0, u, v) \
422 __asm__ ("mulu%.l %3,%1:%0" \
423 : "=d" ((USItype) (w0)), \
424 "=d" ((USItype) (w1)) \
425 : "%0" ((USItype) (u)), \
426 "dmi" ((USItype) (v)))
427 #define UMUL_TIME 45
428 #define udiv_qrnnd(q, r, n1, n0, d) \
429 __asm__ ("divu%.l %4,%1:%0" \
430 : "=d" ((USItype) (q)), \
431 "=d" ((USItype) (r)) \
432 : "0" ((USItype) (n0)), \
433 "1" ((USItype) (n1)), \
434 "dmi" ((USItype) (d)))
435 #define UDIV_TIME 90
436 #define sdiv_qrnnd(q, r, n1, n0, d) \
437 __asm__ ("divs%.l %4,%1:%0" \
438 : "=d" ((USItype) (q)), \
439 "=d" ((USItype) (r)) \
440 : "0" ((USItype) (n0)), \
441 "1" ((USItype) (n1)), \
442 "dmi" ((USItype) (d)))
443
444 #elif defined (__mcoldfire__) /* not mc68020 */
445
446 #define umul_ppmm(xh, xl, a, b) \
447 __asm__ ("| Inlined umul_ppmm\n" \
448 " move%.l %2,%/d0\n" \
449 " move%.l %3,%/d1\n" \
450 " move%.l %/d0,%/d2\n" \
451 " swap %/d0\n" \
452 " move%.l %/d1,%/d3\n" \
453 " swap %/d1\n" \
454 " move%.w %/d2,%/d4\n" \
455 " mulu %/d3,%/d4\n" \
456 " mulu %/d1,%/d2\n" \
457 " mulu %/d0,%/d3\n" \
458 " mulu %/d0,%/d1\n" \
459 " move%.l %/d4,%/d0\n" \
460 " clr%.w %/d0\n" \
461 " swap %/d0\n" \
462 " add%.l %/d0,%/d2\n" \
463 " add%.l %/d3,%/d2\n" \
464 " jcc 1f\n" \
465 " add%.l %#65536,%/d1\n" \
466 "1: swap %/d2\n" \
467 " moveq %#0,%/d0\n" \
468 " move%.w %/d2,%/d0\n" \
469 " move%.w %/d4,%/d2\n" \
470 " move%.l %/d2,%1\n" \
471 " add%.l %/d1,%/d0\n" \
472 " move%.l %/d0,%0" \
473 : "=g" ((USItype) (xh)), \
474 "=g" ((USItype) (xl)) \
475 : "g" ((USItype) (a)), \
476 "g" ((USItype) (b)) \
477 : "d0", "d1", "d2", "d3", "d4")
478 #define UMUL_TIME 100
479 #define UDIV_TIME 400
480 #else /* not ColdFire */
481 /* %/ inserts REGISTER_PREFIX, %# inserts IMMEDIATE_PREFIX. */
482 #define umul_ppmm(xh, xl, a, b) \
483 __asm__ ("| Inlined umul_ppmm\n" \
484 " move%.l %2,%/d0\n" \
485 " move%.l %3,%/d1\n" \
486 " move%.l %/d0,%/d2\n" \
487 " swap %/d0\n" \
488 " move%.l %/d1,%/d3\n" \
489 " swap %/d1\n" \
490 " move%.w %/d2,%/d4\n" \
491 " mulu %/d3,%/d4\n" \
492 " mulu %/d1,%/d2\n" \
493 " mulu %/d0,%/d3\n" \
494 " mulu %/d0,%/d1\n" \
495 " move%.l %/d4,%/d0\n" \
496 " eor%.w %/d0,%/d0\n" \
497 " swap %/d0\n" \
498 " add%.l %/d0,%/d2\n" \
499 " add%.l %/d3,%/d2\n" \
500 " jcc 1f\n" \
501 " add%.l %#65536,%/d1\n" \
502 "1: swap %/d2\n" \
503 " moveq %#0,%/d0\n" \
504 " move%.w %/d2,%/d0\n" \
505 " move%.w %/d4,%/d2\n" \
506 " move%.l %/d2,%1\n" \
507 " add%.l %/d1,%/d0\n" \
508 " move%.l %/d0,%0" \
509 : "=g" ((USItype) (xh)), \
510 "=g" ((USItype) (xl)) \
511 : "g" ((USItype) (a)), \
512 "g" ((USItype) (b)) \
513 : "d0", "d1", "d2", "d3", "d4")
514 #define UMUL_TIME 100
515 #define UDIV_TIME 400
516
517 #endif /* not mc68020 */
518
519 /* The '020, '030, '040 and '060 have bitfield insns.
520 cpu32 disguises as a 68020, but lacks them. */
521 #if defined (__mc68020__) && !defined (__mcpu32__)
522 #define count_leading_zeros(count, x) \
523 __asm__ ("bfffo %1{%b2:%b2},%0" \
524 : "=d" ((USItype) (count)) \
525 : "od" ((USItype) (x)), "n" (0))
526 #endif
527 #endif /* mc68000 */
528
529 #if defined (__m88000__) && W_TYPE_SIZE == 32
530 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
531 __asm__ ("addu.co %1,%r4,%r5\n\taddu.ci %0,%r2,%r3" \
532 : "=r" ((USItype) (sh)), \
533 "=&r" ((USItype) (sl)) \
534 : "%rJ" ((USItype) (ah)), \
535 "rJ" ((USItype) (bh)), \
536 "%rJ" ((USItype) (al)), \
537 "rJ" ((USItype) (bl)))
538 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
539 __asm__ ("subu.co %1,%r4,%r5\n\tsubu.ci %0,%r2,%r3" \
540 : "=r" ((USItype) (sh)), \
541 "=&r" ((USItype) (sl)) \
542 : "rJ" ((USItype) (ah)), \
543 "rJ" ((USItype) (bh)), \
544 "rJ" ((USItype) (al)), \
545 "rJ" ((USItype) (bl)))
546 #define count_leading_zeros(count, x) \
547 do { \
548 USItype __cbtmp; \
549 __asm__ ("ff1 %0,%1" \
550 : "=r" (__cbtmp) \
551 : "r" ((USItype) (x))); \
552 (count) = __cbtmp ^ 31; \
553 } while (0)
554 #define COUNT_LEADING_ZEROS_0 63 /* sic */
555 #if defined (__mc88110__)
556 #define umul_ppmm(wh, wl, u, v) \
557 do { \
558 union {UDItype __ll; \
559 struct {USItype __h, __l;} __i; \
560 } __xx; \
561 __asm__ ("mulu.d %0,%1,%2" \
562 : "=r" (__xx.__ll) \
563 : "r" ((USItype) (u)), \
564 "r" ((USItype) (v))); \
565 (wh) = __xx.__i.__h; \
566 (wl) = __xx.__i.__l; \
567 } while (0)
568 #define udiv_qrnnd(q, r, n1, n0, d) \
569 ({union {UDItype __ll; \
570 struct {USItype __h, __l;} __i; \
571 } __xx; \
572 USItype __q; \
573 __xx.__i.__h = (n1); __xx.__i.__l = (n0); \
574 __asm__ ("divu.d %0,%1,%2" \
575 : "=r" (__q) \
576 : "r" (__xx.__ll), \
577 "r" ((USItype) (d))); \
578 (r) = (n0) - __q * (d); (q) = __q; })
579 #define UMUL_TIME 5
580 #define UDIV_TIME 25
581 #else
582 #define UMUL_TIME 17
583 #define UDIV_TIME 150
584 #endif /* __mc88110__ */
585 #endif /* __m88000__ */
586
587 #if defined (__mips__) && W_TYPE_SIZE == 32
588 #define umul_ppmm(w1, w0, u, v) \
589 __asm__ ("multu %2,%3" \
590 : "=l" ((USItype) (w0)), \
591 "=h" ((USItype) (w1)) \
592 : "d" ((USItype) (u)), \
593 "d" ((USItype) (v)))
594 #define UMUL_TIME 10
595 #define UDIV_TIME 100
596 #endif /* __mips__ */
597
598 #if defined (__ns32000__) && W_TYPE_SIZE == 32
599 #define umul_ppmm(w1, w0, u, v) \
600 ({union {UDItype __ll; \
601 struct {USItype __l, __h;} __i; \
602 } __xx; \
603 __asm__ ("meid %2,%0" \
604 : "=g" (__xx.__ll) \
605 : "%0" ((USItype) (u)), \
606 "g" ((USItype) (v))); \
607 (w1) = __xx.__i.__h; (w0) = __xx.__i.__l;})
608 #define __umulsidi3(u, v) \
609 ({UDItype __w; \
610 __asm__ ("meid %2,%0" \
611 : "=g" (__w) \
612 : "%0" ((USItype) (u)), \
613 "g" ((USItype) (v))); \
614 __w; })
615 #define udiv_qrnnd(q, r, n1, n0, d) \
616 ({union {UDItype __ll; \
617 struct {USItype __l, __h;} __i; \
618 } __xx; \
619 __xx.__i.__h = (n1); __xx.__i.__l = (n0); \
620 __asm__ ("deid %2,%0" \
621 : "=g" (__xx.__ll) \
622 : "0" (__xx.__ll), \
623 "g" ((USItype) (d))); \
624 (r) = __xx.__i.__l; (q) = __xx.__i.__h; })
625 #define count_trailing_zeros(count,x) \
626 do { \
627 __asm__ ("ffsd %2,%0" \
628 : "=r" ((USItype) (count)) \
629 : "0" ((USItype) 0), \
630 "r" ((USItype) (x))); \
631 } while (0)
632 #endif /* __ns32000__ */
633
634 /* FIXME: We should test _IBMR2 here when we add assembly support for the
635 system vendor compilers.
636 FIXME: What's needed for gcc PowerPC VxWorks? __vxworks__ is not good
637 enough, since that hits ARM and m68k too. */
638 #if (defined (_ARCH_PPC) /* AIX */ \
639 || defined (_ARCH_PWR) /* AIX */ \
640 || defined (_ARCH_COM) /* AIX */ \
641 || defined (__powerpc__) /* gcc */ \
642 || defined (__POWERPC__) /* BEOS */ \
643 || defined (__ppc__) /* Darwin */ \
644 || defined (PPC) /* GNU/Linux, SysV */ \
645 ) && W_TYPE_SIZE == 32
646 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
647 do { \
648 if (__builtin_constant_p (bh) && (bh) == 0) \
649 __asm__ ("{a%I4|add%I4c} %1,%3,%4\n\t{aze|addze} %0,%2" \
650 : "=r" (sh), "=&r" (sl) : "r" (ah), "%r" (al), "rI" (bl));\
651 else if (__builtin_constant_p (bh) && (bh) == ~(USItype) 0) \
652 __asm__ ("{a%I4|add%I4c} %1,%3,%4\n\t{ame|addme} %0,%2" \
653 : "=r" (sh), "=&r" (sl) : "r" (ah), "%r" (al), "rI" (bl));\
654 else \
655 __asm__ ("{a%I5|add%I5c} %1,%4,%5\n\t{ae|adde} %0,%2,%3" \
656 : "=r" (sh), "=&r" (sl) \
657 : "%r" (ah), "r" (bh), "%r" (al), "rI" (bl)); \
658 } while (0)
659 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
660 do { \
661 if (__builtin_constant_p (ah) && (ah) == 0) \
662 __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{sfze|subfze} %0,%2" \
663 : "=r" (sh), "=&r" (sl) : "r" (bh), "rI" (al), "r" (bl));\
664 else if (__builtin_constant_p (ah) && (ah) == ~(USItype) 0) \
665 __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{sfme|subfme} %0,%2" \
666 : "=r" (sh), "=&r" (sl) : "r" (bh), "rI" (al), "r" (bl));\
667 else if (__builtin_constant_p (bh) && (bh) == 0) \
668 __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{ame|addme} %0,%2" \
669 : "=r" (sh), "=&r" (sl) : "r" (ah), "rI" (al), "r" (bl));\
670 else if (__builtin_constant_p (bh) && (bh) == ~(USItype) 0) \
671 __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{aze|addze} %0,%2" \
672 : "=r" (sh), "=&r" (sl) : "r" (ah), "rI" (al), "r" (bl));\
673 else \
674 __asm__ ("{sf%I4|subf%I4c} %1,%5,%4\n\t{sfe|subfe} %0,%3,%2" \
675 : "=r" (sh), "=&r" (sl) \
676 : "r" (ah), "r" (bh), "rI" (al), "r" (bl)); \
677 } while (0)
678 #define count_leading_zeros(count, x) \
679 __asm__ ("{cntlz|cntlzw} %0,%1" : "=r" (count) : "r" (x))
680 #define COUNT_LEADING_ZEROS_0 32
681 #if defined (_ARCH_PPC) || defined (__powerpc__) || defined (__POWERPC__) \
682 || defined (__ppc__) || defined (PPC)
683 #define umul_ppmm(ph, pl, m0, m1) \
684 do { \
685 USItype __m0 = (m0), __m1 = (m1); \
686 __asm__ ("mulhwu %0,%1,%2" : "=r" (ph) : "%r" (m0), "r" (m1)); \
687 (pl) = __m0 * __m1; \
688 } while (0)
689 #define UMUL_TIME 15
690 #define smul_ppmm(ph, pl, m0, m1) \
691 do { \
692 SItype __m0 = (m0), __m1 = (m1); \
693 __asm__ ("mulhw %0,%1,%2" : "=r" (ph) : "%r" (m0), "r" (m1)); \
694 (pl) = __m0 * __m1; \
695 } while (0)
696 #define SMUL_TIME 14
697 #define UDIV_TIME 120
698 #elif defined (_ARCH_PWR)
699 #define UMUL_TIME 8
700 #define smul_ppmm(xh, xl, m0, m1) \
701 __asm__ ("mul %0,%2,%3" : "=r" (xh), "=q" (xl) : "r" (m0), "r" (m1))
702 #define SMUL_TIME 4
703 #define sdiv_qrnnd(q, r, nh, nl, d) \
704 __asm__ ("div %0,%2,%4" : "=r" (q), "=q" (r) : "r" (nh), "1" (nl), "r" (d))
705 #define UDIV_TIME 100
706 #endif
707 #endif /* 32-bit POWER architecture variants. */
708
709 /* We should test _IBMR2 here when we add assembly support for the system
710 vendor compilers. */
711 #if (defined (_ARCH_PPC64) || defined (__powerpc64__)) && W_TYPE_SIZE == 64
712 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
713 do { \
714 if (__builtin_constant_p (bh) && (bh) == 0) \
715 __asm__ ("{a%I4|add%I4c} %1,%3,%4\n\t{aze|addze} %0,%2" \
716 : "=r" (sh), "=&r" (sl) : "r" (ah), "%r" (al), "rI" (bl));\
717 else if (__builtin_constant_p (bh) && (bh) == ~(UDItype) 0) \
718 __asm__ ("{a%I4|add%I4c} %1,%3,%4\n\t{ame|addme} %0,%2" \
719 : "=r" (sh), "=&r" (sl) : "r" (ah), "%r" (al), "rI" (bl));\
720 else \
721 __asm__ ("{a%I5|add%I5c} %1,%4,%5\n\t{ae|adde} %0,%2,%3" \
722 : "=r" (sh), "=&r" (sl) \
723 : "%r" (ah), "r" (bh), "%r" (al), "rI" (bl)); \
724 } while (0)
725 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
726 do { \
727 if (__builtin_constant_p (ah) && (ah) == 0) \
728 __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{sfze|subfze} %0,%2" \
729 : "=r" (sh), "=&r" (sl) : "r" (bh), "rI" (al), "r" (bl));\
730 else if (__builtin_constant_p (ah) && (ah) == ~(UDItype) 0) \
731 __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{sfme|subfme} %0,%2" \
732 : "=r" (sh), "=&r" (sl) : "r" (bh), "rI" (al), "r" (bl));\
733 else if (__builtin_constant_p (bh) && (bh) == 0) \
734 __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{ame|addme} %0,%2" \
735 : "=r" (sh), "=&r" (sl) : "r" (ah), "rI" (al), "r" (bl));\
736 else if (__builtin_constant_p (bh) && (bh) == ~(UDItype) 0) \
737 __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{aze|addze} %0,%2" \
738 : "=r" (sh), "=&r" (sl) : "r" (ah), "rI" (al), "r" (bl));\
739 else \
740 __asm__ ("{sf%I4|subf%I4c} %1,%5,%4\n\t{sfe|subfe} %0,%3,%2" \
741 : "=r" (sh), "=&r" (sl) \
742 : "r" (ah), "r" (bh), "rI" (al), "r" (bl)); \
743 } while (0)
744 #define count_leading_zeros(count, x) \
745 __asm__ ("cntlzd %0,%1" : "=r" (count) : "r" (x))
746 #define COUNT_LEADING_ZEROS_0 64
747 #define umul_ppmm(ph, pl, m0, m1) \
748 do { \
749 UDItype __m0 = (m0), __m1 = (m1); \
750 __asm__ ("mulhdu %0,%1,%2" : "=r" (ph) : "%r" (m0), "r" (m1)); \
751 (pl) = __m0 * __m1; \
752 } while (0)
753 #define UMUL_TIME 15
754 #define smul_ppmm(ph, pl, m0, m1) \
755 do { \
756 DItype __m0 = (m0), __m1 = (m1); \
757 __asm__ ("mulhd %0,%1,%2" : "=r" (ph) : "%r" (m0), "r" (m1)); \
758 (pl) = __m0 * __m1; \
759 } while (0)
760 #define SMUL_TIME 14 /* ??? */
761 #define UDIV_TIME 120 /* ??? */
762 #endif /* 64-bit PowerPC. */
763
764 #if defined (__ibm032__) /* RT/ROMP */ && W_TYPE_SIZE == 32
765 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
766 __asm__ ("a %1,%5\n\tae %0,%3" \
767 : "=r" ((USItype) (sh)), \
768 "=&r" ((USItype) (sl)) \
769 : "%0" ((USItype) (ah)), \
770 "r" ((USItype) (bh)), \
771 "%1" ((USItype) (al)), \
772 "r" ((USItype) (bl)))
773 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
774 __asm__ ("s %1,%5\n\tse %0,%3" \
775 : "=r" ((USItype) (sh)), \
776 "=&r" ((USItype) (sl)) \
777 : "0" ((USItype) (ah)), \
778 "r" ((USItype) (bh)), \
779 "1" ((USItype) (al)), \
780 "r" ((USItype) (bl)))
781 #define umul_ppmm(ph, pl, m0, m1) \
782 do { \
783 USItype __m0 = (m0), __m1 = (m1); \
784 __asm__ ( \
785 "s r2,r2\n" \
786 " mts r10,%2\n" \
787 " m r2,%3\n" \
788 " m r2,%3\n" \
789 " m r2,%3\n" \
790 " m r2,%3\n" \
791 " m r2,%3\n" \
792 " m r2,%3\n" \
793 " m r2,%3\n" \
794 " m r2,%3\n" \
795 " m r2,%3\n" \
796 " m r2,%3\n" \
797 " m r2,%3\n" \
798 " m r2,%3\n" \
799 " m r2,%3\n" \
800 " m r2,%3\n" \
801 " m r2,%3\n" \
802 " m r2,%3\n" \
803 " cas %0,r2,r0\n" \
804 " mfs r10,%1" \
805 : "=r" ((USItype) (ph)), \
806 "=r" ((USItype) (pl)) \
807 : "%r" (__m0), \
808 "r" (__m1) \
809 : "r2"); \
810 (ph) += ((((SItype) __m0 >> 31) & __m1) \
811 + (((SItype) __m1 >> 31) & __m0)); \
812 } while (0)
813 #define UMUL_TIME 20
814 #define UDIV_TIME 200
815 #define count_leading_zeros(count, x) \
816 do { \
817 if ((x) >= 0x10000) \
818 __asm__ ("clz %0,%1" \
819 : "=r" ((USItype) (count)) \
820 : "r" ((USItype) (x) >> 16)); \
821 else \
822 { \
823 __asm__ ("clz %0,%1" \
824 : "=r" ((USItype) (count)) \
825 : "r" ((USItype) (x))); \
826 (count) += 16; \
827 } \
828 } while (0)
829 #endif
830
831 #if defined (__sh2__) && W_TYPE_SIZE == 32
832 #define umul_ppmm(w1, w0, u, v) \
833 __asm__ ( \
834 "dmulu.l %2,%3\n\tsts macl,%1\n\tsts mach,%0" \
835 : "=r" ((USItype)(w1)), \
836 "=r" ((USItype)(w0)) \
837 : "r" ((USItype)(u)), \
838 "r" ((USItype)(v)) \
839 : "macl", "mach")
840 #define UMUL_TIME 5
841 #endif
842
843 #if defined (__SH5__) && __SHMEDIA__ && W_TYPE_SIZE == 32
844 #define __umulsidi3(u,v) ((UDItype)(USItype)u*(USItype)v)
845 #define count_leading_zeros(count, x) \
846 do \
847 { \
848 UDItype x_ = (USItype)(x); \
849 SItype c_; \
850 \
851 __asm__ ("nsb %1, %0" : "=r" (c_) : "r" (x_)); \
852 (count) = c_ - 31; \
853 } \
854 while (0)
855 #define COUNT_LEADING_ZEROS_0 32
856 #endif
857
858 #if defined (__sparc__) && !defined (__arch64__) && !defined (__sparcv9) \
859 && W_TYPE_SIZE == 32
860 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
861 __asm__ ("addcc %r4,%5,%1\n\taddx %r2,%3,%0" \
862 : "=r" ((USItype) (sh)), \
863 "=&r" ((USItype) (sl)) \
864 : "%rJ" ((USItype) (ah)), \
865 "rI" ((USItype) (bh)), \
866 "%rJ" ((USItype) (al)), \
867 "rI" ((USItype) (bl)) \
868 __CLOBBER_CC)
869 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
870 __asm__ ("subcc %r4,%5,%1\n\tsubx %r2,%3,%0" \
871 : "=r" ((USItype) (sh)), \
872 "=&r" ((USItype) (sl)) \
873 : "rJ" ((USItype) (ah)), \
874 "rI" ((USItype) (bh)), \
875 "rJ" ((USItype) (al)), \
876 "rI" ((USItype) (bl)) \
877 __CLOBBER_CC)
878 #if defined (__sparc_v8__)
879 #define umul_ppmm(w1, w0, u, v) \
880 __asm__ ("umul %2,%3,%1;rd %%y,%0" \
881 : "=r" ((USItype) (w1)), \
882 "=r" ((USItype) (w0)) \
883 : "r" ((USItype) (u)), \
884 "r" ((USItype) (v)))
885 #define udiv_qrnnd(__q, __r, __n1, __n0, __d) \
886 __asm__ ("mov %2,%%y;nop;nop;nop;udiv %3,%4,%0;umul %0,%4,%1;sub %3,%1,%1"\
887 : "=&r" ((USItype) (__q)), \
888 "=&r" ((USItype) (__r)) \
889 : "r" ((USItype) (__n1)), \
890 "r" ((USItype) (__n0)), \
891 "r" ((USItype) (__d)))
892 #else
893 #if defined (__sparclite__)
894 /* This has hardware multiply but not divide. It also has two additional
895 instructions scan (ffs from high bit) and divscc. */
896 #define umul_ppmm(w1, w0, u, v) \
897 __asm__ ("umul %2,%3,%1;rd %%y,%0" \
898 : "=r" ((USItype) (w1)), \
899 "=r" ((USItype) (w0)) \
900 : "r" ((USItype) (u)), \
901 "r" ((USItype) (v)))
902 #define udiv_qrnnd(q, r, n1, n0, d) \
903 __asm__ ("! Inlined udiv_qrnnd\n" \
904 " wr %%g0,%2,%%y ! Not a delayed write for sparclite\n" \
905 " tst %%g0\n" \
906 " divscc %3,%4,%%g1\n" \
907 " divscc %%g1,%4,%%g1\n" \
908 " divscc %%g1,%4,%%g1\n" \
909 " divscc %%g1,%4,%%g1\n" \
910 " divscc %%g1,%4,%%g1\n" \
911 " divscc %%g1,%4,%%g1\n" \
912 " divscc %%g1,%4,%%g1\n" \
913 " divscc %%g1,%4,%%g1\n" \
914 " divscc %%g1,%4,%%g1\n" \
915 " divscc %%g1,%4,%%g1\n" \
916 " divscc %%g1,%4,%%g1\n" \
917 " divscc %%g1,%4,%%g1\n" \
918 " divscc %%g1,%4,%%g1\n" \
919 " divscc %%g1,%4,%%g1\n" \
920 " divscc %%g1,%4,%%g1\n" \
921 " divscc %%g1,%4,%%g1\n" \
922 " divscc %%g1,%4,%%g1\n" \
923 " divscc %%g1,%4,%%g1\n" \
924 " divscc %%g1,%4,%%g1\n" \
925 " divscc %%g1,%4,%%g1\n" \
926 " divscc %%g1,%4,%%g1\n" \
927 " divscc %%g1,%4,%%g1\n" \
928 " divscc %%g1,%4,%%g1\n" \
929 " divscc %%g1,%4,%%g1\n" \
930 " divscc %%g1,%4,%%g1\n" \
931 " divscc %%g1,%4,%%g1\n" \
932 " divscc %%g1,%4,%%g1\n" \
933 " divscc %%g1,%4,%%g1\n" \
934 " divscc %%g1,%4,%%g1\n" \
935 " divscc %%g1,%4,%%g1\n" \
936 " divscc %%g1,%4,%%g1\n" \
937 " divscc %%g1,%4,%0\n" \
938 " rd %%y,%1\n" \
939 " bl,a 1f\n" \
940 " add %1,%4,%1\n" \
941 "1: ! End of inline udiv_qrnnd" \
942 : "=r" ((USItype) (q)), \
943 "=r" ((USItype) (r)) \
944 : "r" ((USItype) (n1)), \
945 "r" ((USItype) (n0)), \
946 "rI" ((USItype) (d)) \
947 : "g1" __AND_CLOBBER_CC)
948 #define UDIV_TIME 37
949 #define count_leading_zeros(count, x) \
950 do { \
951 __asm__ ("scan %1,1,%0" \
952 : "=r" ((USItype) (count)) \
953 : "r" ((USItype) (x))); \
954 } while (0)
955 /* Early sparclites return 63 for an argument of 0, but they warn that future
956 implementations might change this. Therefore, leave COUNT_LEADING_ZEROS_0
957 undefined. */
958 #else
959 /* SPARC without integer multiplication and divide instructions.
960 (i.e. at least Sun4/20,40,60,65,75,110,260,280,330,360,380,470,490) */
961 #define umul_ppmm(w1, w0, u, v) \
962 __asm__ ("! Inlined umul_ppmm\n" \
963 " wr %%g0,%2,%%y ! SPARC has 0-3 delay insn after a wr\n"\
964 " sra %3,31,%%o5 ! Don't move this insn\n" \
965 " and %2,%%o5,%%o5 ! Don't move this insn\n" \
966 " andcc %%g0,0,%%g1 ! Don't move this insn\n" \
967 " mulscc %%g1,%3,%%g1\n" \
968 " mulscc %%g1,%3,%%g1\n" \
969 " mulscc %%g1,%3,%%g1\n" \
970 " mulscc %%g1,%3,%%g1\n" \
971 " mulscc %%g1,%3,%%g1\n" \
972 " mulscc %%g1,%3,%%g1\n" \
973 " mulscc %%g1,%3,%%g1\n" \
974 " mulscc %%g1,%3,%%g1\n" \
975 " mulscc %%g1,%3,%%g1\n" \
976 " mulscc %%g1,%3,%%g1\n" \
977 " mulscc %%g1,%3,%%g1\n" \
978 " mulscc %%g1,%3,%%g1\n" \
979 " mulscc %%g1,%3,%%g1\n" \
980 " mulscc %%g1,%3,%%g1\n" \
981 " mulscc %%g1,%3,%%g1\n" \
982 " mulscc %%g1,%3,%%g1\n" \
983 " mulscc %%g1,%3,%%g1\n" \
984 " mulscc %%g1,%3,%%g1\n" \
985 " mulscc %%g1,%3,%%g1\n" \
986 " mulscc %%g1,%3,%%g1\n" \
987 " mulscc %%g1,%3,%%g1\n" \
988 " mulscc %%g1,%3,%%g1\n" \
989 " mulscc %%g1,%3,%%g1\n" \
990 " mulscc %%g1,%3,%%g1\n" \
991 " mulscc %%g1,%3,%%g1\n" \
992 " mulscc %%g1,%3,%%g1\n" \
993 " mulscc %%g1,%3,%%g1\n" \
994 " mulscc %%g1,%3,%%g1\n" \
995 " mulscc %%g1,%3,%%g1\n" \
996 " mulscc %%g1,%3,%%g1\n" \
997 " mulscc %%g1,%3,%%g1\n" \
998 " mulscc %%g1,%3,%%g1\n" \
999 " mulscc %%g1,0,%%g1\n" \
1000 " add %%g1,%%o5,%0\n" \
1001 " rd %%y,%1" \
1002 : "=r" ((USItype) (w1)), \
1003 "=r" ((USItype) (w0)) \
1004 : "%rI" ((USItype) (u)), \
1005 "r" ((USItype) (v)) \
1006 : "g1", "o5" __AND_CLOBBER_CC)
1007 #define UMUL_TIME 39 /* 39 instructions */
1008 /* It's quite necessary to add this much assembler for the sparc.
1009 The default udiv_qrnnd (in C) is more than 10 times slower! */
1010 #define udiv_qrnnd(__q, __r, __n1, __n0, __d) \
1011 __asm__ ("! Inlined udiv_qrnnd\n" \
1012 " mov 32,%%g1\n" \
1013 " subcc %1,%2,%%g0\n" \
1014 "1: bcs 5f\n" \
1015 " addxcc %0,%0,%0 ! shift n1n0 and a q-bit in lsb\n" \
1016 " sub %1,%2,%1 ! this kills msb of n\n" \
1017 " addx %1,%1,%1 ! so this can't give carry\n" \
1018 " subcc %%g1,1,%%g1\n" \
1019 "2: bne 1b\n" \
1020 " subcc %1,%2,%%g0\n" \
1021 " bcs 3f\n" \
1022 " addxcc %0,%0,%0 ! shift n1n0 and a q-bit in lsb\n" \
1023 " b 3f\n" \
1024 " sub %1,%2,%1 ! this kills msb of n\n" \
1025 "4: sub %1,%2,%1\n" \
1026 "5: addxcc %1,%1,%1\n" \
1027 " bcc 2b\n" \
1028 " subcc %%g1,1,%%g1\n" \
1029 "! Got carry from n. Subtract next step to cancel this carry.\n" \
1030 " bne 4b\n" \
1031 " addcc %0,%0,%0 ! shift n1n0 and a 0-bit in lsb\n" \
1032 " sub %1,%2,%1\n" \
1033 "3: xnor %0,0,%0\n" \
1034 " ! End of inline udiv_qrnnd" \
1035 : "=&r" ((USItype) (__q)), \
1036 "=&r" ((USItype) (__r)) \
1037 : "r" ((USItype) (__d)), \
1038 "1" ((USItype) (__n1)), \
1039 "0" ((USItype) (__n0)) : "g1" __AND_CLOBBER_CC)
1040 #define UDIV_TIME (3+7*32) /* 7 instructions/iteration. 32 iterations. */
1041 #endif /* __sparclite__ */
1042 #endif /* __sparc_v8__ */
1043 #endif /* sparc32 */
1044
1045 #if ((defined (__sparc__) && defined (__arch64__)) || defined (__sparcv9)) \
1046 && W_TYPE_SIZE == 64
1047 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
1048 __asm__ ("addcc %r4,%5,%1\n\t" \
1049 "add %r2,%3,%0\n\t" \
1050 "bcs,a,pn %%xcc, 1f\n\t" \
1051 "add %0, 1, %0\n" \
1052 "1:" \
1053 : "=r" ((UDItype)(sh)), \
1054 "=&r" ((UDItype)(sl)) \
1055 : "%rJ" ((UDItype)(ah)), \
1056 "rI" ((UDItype)(bh)), \
1057 "%rJ" ((UDItype)(al)), \
1058 "rI" ((UDItype)(bl)) \
1059 __CLOBBER_CC)
1060
1061 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
1062 __asm__ ("subcc %r4,%5,%1\n\t" \
1063 "sub %r2,%3,%0\n\t" \
1064 "bcs,a,pn %%xcc, 1f\n\t" \
1065 "sub %0, 1, %0\n\t" \
1066 "1:" \
1067 : "=r" ((UDItype)(sh)), \
1068 "=&r" ((UDItype)(sl)) \
1069 : "rJ" ((UDItype)(ah)), \
1070 "rI" ((UDItype)(bh)), \
1071 "rJ" ((UDItype)(al)), \
1072 "rI" ((UDItype)(bl)) \
1073 __CLOBBER_CC)
1074
1075 #define umul_ppmm(wh, wl, u, v) \
1076 do { \
1077 UDItype tmp1, tmp2, tmp3, tmp4; \
1078 __asm__ __volatile__ ( \
1079 "srl %7,0,%3\n\t" \
1080 "mulx %3,%6,%1\n\t" \
1081 "srlx %6,32,%2\n\t" \
1082 "mulx %2,%3,%4\n\t" \
1083 "sllx %4,32,%5\n\t" \
1084 "srl %6,0,%3\n\t" \
1085 "sub %1,%5,%5\n\t" \
1086 "srlx %5,32,%5\n\t" \
1087 "addcc %4,%5,%4\n\t" \
1088 "srlx %7,32,%5\n\t" \
1089 "mulx %3,%5,%3\n\t" \
1090 "mulx %2,%5,%5\n\t" \
1091 "sethi %%hi(0x80000000),%2\n\t" \
1092 "addcc %4,%3,%4\n\t" \
1093 "srlx %4,32,%4\n\t" \
1094 "add %2,%2,%2\n\t" \
1095 "movcc %%xcc,%%g0,%2\n\t" \
1096 "addcc %5,%4,%5\n\t" \
1097 "sllx %3,32,%3\n\t" \
1098 "add %1,%3,%1\n\t" \
1099 "add %5,%2,%0" \
1100 : "=r" ((UDItype)(wh)), \
1101 "=&r" ((UDItype)(wl)), \
1102 "=&r" (tmp1), "=&r" (tmp2), "=&r" (tmp3), "=&r" (tmp4) \
1103 : "r" ((UDItype)(u)), \
1104 "r" ((UDItype)(v)) \
1105 __CLOBBER_CC); \
1106 } while (0)
1107 #define UMUL_TIME 96
1108 #define UDIV_TIME 230
1109 #endif /* sparc64 */
1110
1111 #if defined (__vax__) && W_TYPE_SIZE == 32
1112 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
1113 __asm__ ("addl2 %5,%1\n\tadwc %3,%0" \
1114 : "=g" ((USItype) (sh)), \
1115 "=&g" ((USItype) (sl)) \
1116 : "%0" ((USItype) (ah)), \
1117 "g" ((USItype) (bh)), \
1118 "%1" ((USItype) (al)), \
1119 "g" ((USItype) (bl)))
1120 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
1121 __asm__ ("subl2 %5,%1\n\tsbwc %3,%0" \
1122 : "=g" ((USItype) (sh)), \
1123 "=&g" ((USItype) (sl)) \
1124 : "0" ((USItype) (ah)), \
1125 "g" ((USItype) (bh)), \
1126 "1" ((USItype) (al)), \
1127 "g" ((USItype) (bl)))
1128 #define umul_ppmm(xh, xl, m0, m1) \
1129 do { \
1130 union { \
1131 UDItype __ll; \
1132 struct {USItype __l, __h;} __i; \
1133 } __xx; \
1134 USItype __m0 = (m0), __m1 = (m1); \
1135 __asm__ ("emul %1,%2,$0,%0" \
1136 : "=r" (__xx.__ll) \
1137 : "g" (__m0), \
1138 "g" (__m1)); \
1139 (xh) = __xx.__i.__h; \
1140 (xl) = __xx.__i.__l; \
1141 (xh) += ((((SItype) __m0 >> 31) & __m1) \
1142 + (((SItype) __m1 >> 31) & __m0)); \
1143 } while (0)
1144 #define sdiv_qrnnd(q, r, n1, n0, d) \
1145 do { \
1146 union {DItype __ll; \
1147 struct {SItype __l, __h;} __i; \
1148 } __xx; \
1149 __xx.__i.__h = n1; __xx.__i.__l = n0; \
1150 __asm__ ("ediv %3,%2,%0,%1" \
1151 : "=g" (q), "=g" (r) \
1152 : "g" (__xx.__ll), "g" (d)); \
1153 } while (0)
1154 #endif /* __vax__ */
1155
1156 #if defined (__z8000__) && W_TYPE_SIZE == 16
1157 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
1158 __asm__ ("add %H1,%H5\n\tadc %H0,%H3" \
1159 : "=r" ((unsigned int)(sh)), \
1160 "=&r" ((unsigned int)(sl)) \
1161 : "%0" ((unsigned int)(ah)), \
1162 "r" ((unsigned int)(bh)), \
1163 "%1" ((unsigned int)(al)), \
1164 "rQR" ((unsigned int)(bl)))
1165 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
1166 __asm__ ("sub %H1,%H5\n\tsbc %H0,%H3" \
1167 : "=r" ((unsigned int)(sh)), \
1168 "=&r" ((unsigned int)(sl)) \
1169 : "0" ((unsigned int)(ah)), \
1170 "r" ((unsigned int)(bh)), \
1171 "1" ((unsigned int)(al)), \
1172 "rQR" ((unsigned int)(bl)))
1173 #define umul_ppmm(xh, xl, m0, m1) \
1174 do { \
1175 union {long int __ll; \
1176 struct {unsigned int __h, __l;} __i; \
1177 } __xx; \
1178 unsigned int __m0 = (m0), __m1 = (m1); \
1179 __asm__ ("mult %S0,%H3" \
1180 : "=r" (__xx.__i.__h), \
1181 "=r" (__xx.__i.__l) \
1182 : "%1" (__m0), \
1183 "rQR" (__m1)); \
1184 (xh) = __xx.__i.__h; (xl) = __xx.__i.__l; \
1185 (xh) += ((((signed int) __m0 >> 15) & __m1) \
1186 + (((signed int) __m1 >> 15) & __m0)); \
1187 } while (0)
1188 #endif /* __z8000__ */
1189
1190 #endif /* __GNUC__ */
1191
1192 /* If this machine has no inline assembler, use C macros. */
1193
1194 #if !defined (add_ssaaaa)
1195 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
1196 do { \
1197 UWtype __x; \
1198 __x = (al) + (bl); \
1199 (sh) = (ah) + (bh) + (__x < (al)); \
1200 (sl) = __x; \
1201 } while (0)
1202 #endif
1203
1204 #if !defined (sub_ddmmss)
1205 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
1206 do { \
1207 UWtype __x; \
1208 __x = (al) - (bl); \
1209 (sh) = (ah) - (bh) - (__x > (al)); \
1210 (sl) = __x; \
1211 } while (0)
1212 #endif
1213
1214 /* If we lack umul_ppmm but have smul_ppmm, define umul_ppmm in terms of
1215 smul_ppmm. */
1216 #if !defined (umul_ppmm) && defined (smul_ppmm)
1217 #define umul_ppmm(w1, w0, u, v) \
1218 do { \
1219 UWtype __w1; \
1220 UWtype __xm0 = (u), __xm1 = (v); \
1221 smul_ppmm (__w1, w0, __xm0, __xm1); \
1222 (w1) = __w1 + (-(__xm0 >> (W_TYPE_SIZE - 1)) & __xm1) \
1223 + (-(__xm1 >> (W_TYPE_SIZE - 1)) & __xm0); \
1224 } while (0)
1225 #endif
1226
1227 /* If we still don't have umul_ppmm, define it using plain C. */
1228 #if !defined (umul_ppmm)
1229 #define umul_ppmm(w1, w0, u, v) \
1230 do { \
1231 UWtype __x0, __x1, __x2, __x3; \
1232 UHWtype __ul, __vl, __uh, __vh; \
1233 \
1234 __ul = __ll_lowpart (u); \
1235 __uh = __ll_highpart (u); \
1236 __vl = __ll_lowpart (v); \
1237 __vh = __ll_highpart (v); \
1238 \
1239 __x0 = (UWtype) __ul * __vl; \
1240 __x1 = (UWtype) __ul * __vh; \
1241 __x2 = (UWtype) __uh * __vl; \
1242 __x3 = (UWtype) __uh * __vh; \
1243 \
1244 __x1 += __ll_highpart (__x0);/* this can't give carry */ \
1245 __x1 += __x2; /* but this indeed can */ \
1246 if (__x1 < __x2) /* did we get it? */ \
1247 __x3 += __ll_B; /* yes, add it in the proper pos. */ \
1248 \
1249 (w1) = __x3 + __ll_highpart (__x1); \
1250 (w0) = __ll_lowpart (__x1) * __ll_B + __ll_lowpart (__x0); \
1251 } while (0)
1252 #endif
1253
1254 #if !defined (__umulsidi3)
1255 #define __umulsidi3(u, v) \
1256 ({DWunion __w; \
1257 umul_ppmm (__w.s.high, __w.s.low, u, v); \
1258 __w.ll; })
1259 #endif
1260
1261 /* Define this unconditionally, so it can be used for debugging. */
1262 #define __udiv_qrnnd_c(q, r, n1, n0, d) \
1263 do { \
1264 UWtype __d1, __d0, __q1, __q0; \
1265 UWtype __r1, __r0, __m; \
1266 __d1 = __ll_highpart (d); \
1267 __d0 = __ll_lowpart (d); \
1268 \
1269 __r1 = (n1) % __d1; \
1270 __q1 = (n1) / __d1; \
1271 __m = (UWtype) __q1 * __d0; \
1272 __r1 = __r1 * __ll_B | __ll_highpart (n0); \
1273 if (__r1 < __m) \
1274 { \
1275 __q1--, __r1 += (d); \
1276 if (__r1 >= (d)) /* i.e. we didn't get carry when adding to __r1 */\
1277 if (__r1 < __m) \
1278 __q1--, __r1 += (d); \
1279 } \
1280 __r1 -= __m; \
1281 \
1282 __r0 = __r1 % __d1; \
1283 __q0 = __r1 / __d1; \
1284 __m = (UWtype) __q0 * __d0; \
1285 __r0 = __r0 * __ll_B | __ll_lowpart (n0); \
1286 if (__r0 < __m) \
1287 { \
1288 __q0--, __r0 += (d); \
1289 if (__r0 >= (d)) \
1290 if (__r0 < __m) \
1291 __q0--, __r0 += (d); \
1292 } \
1293 __r0 -= __m; \
1294 \
1295 (q) = (UWtype) __q1 * __ll_B | __q0; \
1296 (r) = __r0; \
1297 } while (0)
1298
1299 /* If the processor has no udiv_qrnnd but sdiv_qrnnd, go through
1300 __udiv_w_sdiv (defined in libgcc or elsewhere). */
1301 #if !defined (udiv_qrnnd) && defined (sdiv_qrnnd)
1302 #define udiv_qrnnd(q, r, nh, nl, d) \
1303 do { \
1304 USItype __r; \
1305 (q) = __udiv_w_sdiv (&__r, nh, nl, d); \
1306 (r) = __r; \
1307 } while (0)
1308 #endif
1309
1310 /* If udiv_qrnnd was not defined for this processor, use __udiv_qrnnd_c. */
1311 #if !defined (udiv_qrnnd)
1312 #define UDIV_NEEDS_NORMALIZATION 1
1313 #define udiv_qrnnd __udiv_qrnnd_c
1314 #endif
1315
1316 #if !defined (count_leading_zeros)
1317 #define count_leading_zeros(count, x) \
1318 do { \
1319 UWtype __xr = (x); \
1320 UWtype __a; \
1321 \
1322 if (W_TYPE_SIZE <= 32) \
1323 { \
1324 __a = __xr < ((UWtype)1<<2*__BITS4) \
1325 ? (__xr < ((UWtype)1<<__BITS4) ? 0 : __BITS4) \
1326 : (__xr < ((UWtype)1<<3*__BITS4) ? 2*__BITS4 : 3*__BITS4); \
1327 } \
1328 else \
1329 { \
1330 for (__a = W_TYPE_SIZE - 8; __a > 0; __a -= 8) \
1331 if (((__xr >> __a) & 0xff) != 0) \
1332 break; \
1333 } \
1334 \
1335 (count) = W_TYPE_SIZE - (__clz_tab[__xr >> __a] + __a); \
1336 } while (0)
1337 #define COUNT_LEADING_ZEROS_0 W_TYPE_SIZE
1338 #endif
1339
1340 #if !defined (count_trailing_zeros)
1341 /* Define count_trailing_zeros using count_leading_zeros. The latter might be
1342 defined in asm, but if it is not, the C version above is good enough. */
1343 #define count_trailing_zeros(count, x) \
1344 do { \
1345 UWtype __ctz_x = (x); \
1346 UWtype __ctz_c; \
1347 count_leading_zeros (__ctz_c, __ctz_x & -__ctz_x); \
1348 (count) = W_TYPE_SIZE - 1 - __ctz_c; \
1349 } while (0)
1350 #endif
1351
1352 #ifndef UDIV_NEEDS_NORMALIZATION
1353 #define UDIV_NEEDS_NORMALIZATION 0
1354 #endif
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