sysdeps/unix/sysv/linux/i386/sysconf.c

   1 /* Get file-specific information about a file.  Linux version.
   2    Copyright (C) 2003, 2004, 2006, 2007 Free Software Foundation, Inc.
   3    This file is part of the GNU C Library.
   4
   5    The GNU C Library is free software; you can redistribute it and/or
   6    modify it under the terms of the GNU Lesser General Public
   7    License as published by the Free Software Foundation; either
   8    version 2.1 of the License, or (at your option) any later version.
   9
  10    The GNU C Library is distributed in the hope that it will be useful,
  11    but WITHOUT ANY WARRANTY; without even the implied warranty of
  12    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  13    Lesser General Public License for more details.
  14
  15    You should have received a copy of the GNU Lesser General Public
  16    License along with the GNU C Library; if not, write to the Free
  17    Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
  18    02111-1307 USA.  */
  19
  20 #include <assert.h>
  21 #include <stdbool.h>
  22 #include <stdlib.h>
  23 #include <unistd.h>
  24 #include <hp-timing.h>
  25
  26 static long int linux_sysconf (int name);
  27
  28
  29 static long int __attribute__ ((noinline))
  30 handle_i486 (int name)
  31 {
  32   /* The processor only has a unified level 1 cache of 8k.  */
  33   switch (name)
  34     {
  35     case _SC_LEVEL1_ICACHE_SIZE:
  36     case _SC_LEVEL1_DCACHE_SIZE:
  37       return 8 * 1024;
  38
  39     case _SC_LEVEL1_ICACHE_ASSOC:
  40     case _SC_LEVEL1_DCACHE_ASSOC:
  41       // XXX Anybody know this?
  42       return 0;
  43
  44     case _SC_LEVEL1_ICACHE_LINESIZE:
  45     case _SC_LEVEL1_DCACHE_LINESIZE:
  46       // XXX Anybody know for sure?
  47       return 16;
  48
  49     case _SC_LEVEL2_CACHE_SIZE:
  50     case _SC_LEVEL2_CACHE_ASSOC:
  51     case _SC_LEVEL2_CACHE_LINESIZE:
  52     case _SC_LEVEL3_CACHE_SIZE:
  53     case _SC_LEVEL3_CACHE_ASSOC:
  54     case _SC_LEVEL3_CACHE_LINESIZE:
  55     case _SC_LEVEL4_CACHE_SIZE:
  56     case _SC_LEVEL4_CACHE_ASSOC:
  57       /* Not available.  */
  58       break;
  59
  60     default:
  61       assert (! "cannot happen");
  62     }
  63
  64   return -1;
  65 }
  66
  67
  68 static const struct intel_02_cache_info
  69 {
  70   unsigned int idx;
  71   int name;
  72   long int size;
  73   long int assoc;
  74   long int linesize;
  75 } intel_02_known[] =
  76   {
  77     { 0x06, _SC_LEVEL1_ICACHE_SIZE, 8192, 4, 32 },
  78     { 0x08, _SC_LEVEL1_ICACHE_SIZE, 16384, 4, 32 },
  79     { 0x09, _SC_LEVEL1_ICACHE_SIZE, 32768, 4, 32 },
  80     { 0x0a, _SC_LEVEL1_DCACHE_SIZE, 8192, 2, 32 },
  81     { 0x0c, _SC_LEVEL1_DCACHE_SIZE, 16384, 4, 32 },
  82     { 0x0d, _SC_LEVEL1_DCACHE_SIZE, 16384, 4, 64 },
  83     { 0x21, _SC_LEVEL2_CACHE_SIZE, 262144, 8, 64 },
  84     { 0x22, _SC_LEVEL3_CACHE_SIZE, 524288, 4, 64 },
  85     { 0x23, _SC_LEVEL3_CACHE_SIZE, 1048576, 8, 64 },
  86     { 0x25, _SC_LEVEL3_CACHE_SIZE, 2097152, 8, 64 },
  87     { 0x29, _SC_LEVEL3_CACHE_SIZE, 4194304, 8, 64 },
  88     { 0x2c, _SC_LEVEL1_DCACHE_SIZE, 32768, 8, 64 },
  89     { 0x30, _SC_LEVEL1_ICACHE_SIZE, 32768, 8, 64 },
  90     { 0x39, _SC_LEVEL2_CACHE_SIZE, 131072, 4, 64 },
  91     { 0x3a, _SC_LEVEL2_CACHE_SIZE, 196608, 6, 64 },
  92     { 0x3b, _SC_LEVEL2_CACHE_SIZE, 131072, 2, 64 },
  93     { 0x3c, _SC_LEVEL2_CACHE_SIZE, 262144, 4, 64 },
  94     { 0x3d, _SC_LEVEL2_CACHE_SIZE, 393216, 6, 64 },
  95     { 0x3e, _SC_LEVEL2_CACHE_SIZE, 524288, 4, 64 },
  96     { 0x3f, _SC_LEVEL2_CACHE_SIZE, 262144, 2, 64 },
  97     { 0x41, _SC_LEVEL2_CACHE_SIZE, 131072, 4, 32 },
  98     { 0x42, _SC_LEVEL2_CACHE_SIZE, 262144, 4, 32 },
  99     { 0x43, _SC_LEVEL2_CACHE_SIZE, 524288, 4, 32 },
 100     { 0x44, _SC_LEVEL2_CACHE_SIZE, 1048576, 4, 32 },
 101     { 0x45, _SC_LEVEL2_CACHE_SIZE, 2097152, 4, 32 },
 102     { 0x46, _SC_LEVEL3_CACHE_SIZE, 4194304, 4, 64 },
 103     { 0x47, _SC_LEVEL3_CACHE_SIZE, 8388608, 8, 64 },
 104     { 0x48, _SC_LEVEL2_CACHE_SIZE, 3145728, 12, 64 },
 105     { 0x49, _SC_LEVEL2_CACHE_SIZE, 4194304, 16, 64 },
 106     { 0x4a, _SC_LEVEL3_CACHE_SIZE, 6291456, 12, 64 },
 107     { 0x4b, _SC_LEVEL3_CACHE_SIZE, 8388608, 16, 64 },
 108     { 0x4c, _SC_LEVEL3_CACHE_SIZE, 12582912, 12, 64 },
 109     { 0x4d, _SC_LEVEL3_CACHE_SIZE, 16777216, 16, 64 },
 110     { 0x4e, _SC_LEVEL2_CACHE_SIZE, 6291456, 24, 64 },
 111     { 0x60, _SC_LEVEL1_DCACHE_SIZE, 16384, 8, 64 },
 112     { 0x66, _SC_LEVEL1_DCACHE_SIZE, 8192, 4, 64 },
 113     { 0x67, _SC_LEVEL1_DCACHE_SIZE, 16384, 4, 64 },
 114     { 0x68, _SC_LEVEL1_DCACHE_SIZE, 32768, 4, 64 },
 115     { 0x78, _SC_LEVEL2_CACHE_SIZE, 1048576, 8, 64 },
 116     { 0x79, _SC_LEVEL2_CACHE_SIZE, 131072, 8, 64 },
 117     { 0x7a, _SC_LEVEL2_CACHE_SIZE, 262144, 8, 64 },
 118     { 0x7b, _SC_LEVEL2_CACHE_SIZE, 524288, 8, 64 },
 119     { 0x7c, _SC_LEVEL2_CACHE_SIZE, 1048576, 8, 64 },
 120     { 0x7d, _SC_LEVEL2_CACHE_SIZE, 2097152, 8, 64 },
 121     { 0x7f, _SC_LEVEL2_CACHE_SIZE, 524288, 2, 64 },
 122     { 0x82, _SC_LEVEL2_CACHE_SIZE, 262144, 8, 32 },
 123     { 0x83, _SC_LEVEL2_CACHE_SIZE, 524288, 8, 32 },
 124     { 0x84, _SC_LEVEL2_CACHE_SIZE, 1048576, 8, 32 },
 125     { 0x85, _SC_LEVEL2_CACHE_SIZE, 2097152, 8, 32 },
 126     { 0x86, _SC_LEVEL2_CACHE_SIZE, 524288, 4, 64 },
 127     { 0x87, _SC_LEVEL2_CACHE_SIZE, 1048576, 8, 64 },
 128     { 0xd0, _SC_LEVEL3_CACHE_SIZE, 524288, 4, 64 },
 129     { 0xd1, _SC_LEVEL3_CACHE_SIZE, 1048576, 4, 64 },
 130     { 0xd2, _SC_LEVEL3_CACHE_SIZE, 2097152, 4, 64 },
 131     { 0xd6, _SC_LEVEL3_CACHE_SIZE, 1048576, 8, 64 },
 132     { 0xd7, _SC_LEVEL3_CACHE_SIZE, 2097152, 8, 64 },
 133     { 0xd8, _SC_LEVEL3_CACHE_SIZE, 4194304, 8, 64 },
 134     { 0xdc, _SC_LEVEL3_CACHE_SIZE, 2097152, 12, 64 },
 135     { 0xdd, _SC_LEVEL3_CACHE_SIZE, 4194304, 12, 64 },
 136     { 0xde, _SC_LEVEL3_CACHE_SIZE, 8388608, 12, 64 },
 137     { 0xe3, _SC_LEVEL3_CACHE_SIZE, 2097152, 16, 64 },
 138     { 0xe3, _SC_LEVEL3_CACHE_SIZE, 4194304, 16, 64 },
 139     { 0xe4, _SC_LEVEL3_CACHE_SIZE, 8388608, 16, 64 },
 140   };
 141 #define nintel_02_known (sizeof (intel_02_known) / sizeof (intel_02_known[0]))
 142
 143
 144 static int
 145 intel_02_known_compare (const void *p1, const void *p2)
 146 {
 147   const struct intel_02_cache_info *i1;
 148   const struct intel_02_cache_info *i2;
 149
 150   i1 = (const struct intel_02_cache_info *) p1;
 151   i2 = (const struct intel_02_cache_info *) p2;
 152
 153   if (i1->idx == i2->idx)
 154     return 0;
 155
 156   return i1->idx < i2->idx ? -1 : 1;
 157 }
 158
 159
 160 static long int
 161 __attribute__ ((noinline))
 162 intel_check_word (int name, unsigned int value, bool *has_level_2,
 163                   bool *no_level_2_or_3)
 164 {
 165   if ((value & 0x80000000) != 0)
 166     /* The register value is reserved.  */
 167     return 0;
 168
 169   /* Fold the name.  The _SC_ constants are always in the order SIZE,
 170      ASSOC, LINESIZE.  */
 171   int folded_name = (_SC_LEVEL1_ICACHE_SIZE
 172                      + ((name - _SC_LEVEL1_ICACHE_SIZE) / 3) * 3);
 173
 174   while (value != 0)
 175     {
 176       unsigned int byte = value & 0xff;
 177
 178       if (byte == 0x40)
 179         {
 180           *no_level_2_or_3 = true;
 181
 182           if (folded_name == _SC_LEVEL3_CACHE_SIZE)
 183             /* No need to look further.  */
 184             break;
 185         }
 186       else
 187         {
 188           if (byte == 0x49 && folded_name == _SC_LEVEL3_CACHE_SIZE)
 189             {
 190               /* Intel reused this value.  For family 15, model 6 it
 191                  specifies the 3rd level cache.  Otherwise the 2nd
 192                  level cache.  */
 193               unsigned int eax;
 194               unsigned int ebx;
 195               unsigned int ecx;
 196               unsigned int edx;
 197               asm volatile ("xchgl %%ebx, %1; cpuid; xchgl %%ebx, %1"
 198                             : "=a" (eax), "=r" (ebx), "=c" (ecx), "=d" (edx)
 199                             : "0" (1));
 200
 201               unsigned int family = ((eax >> 20) & 0xff) + ((eax >> 8) & 0xf);
 202               unsigned int model = ((((eax >>16) & 0xf) << 4)
 203                                     + ((eax >> 4) & 0xf));
 204               if (family == 15 && model == 6)
 205                 {
 206                   /* The level 3 cache is encoded for this model like
 207                      the level 2 cache is for other models.  Pretend
 208                      the caller asked for the level 2 cache.  */
 209                   name = (_SC_LEVEL2_CACHE_SIZE
 210                           + (name - _SC_LEVEL3_CACHE_SIZE));
 211                   folded_name = _SC_LEVEL3_CACHE_SIZE;
 212                 }
 213             }
 214
 215           struct intel_02_cache_info *found;
 216           struct intel_02_cache_info search;
 217
 218           search.idx = byte;
 219           found = bsearch (&search, intel_02_known, nintel_02_known,
 220                            sizeof (intel_02_known[0]), intel_02_known_compare);
 221           if (found != NULL)
 222             {
 223               if (found->name == folded_name)
 224                 {
 225                   unsigned int offset = name - folded_name;
 226
 227                   if (offset == 0)
 228                     /* Cache size.  */
 229                     return found->size;
 230                   if (offset == 1)
 231                     return found->assoc;
 232
 233                   assert (offset == 2);
 234                   return found->linesize;
 235                 }
 236
 237               if (found->name == _SC_LEVEL2_CACHE_SIZE)
 238                 *has_level_2 = true;
 239             }
 240         }
 241
 242       /* Next byte for the next round.  */
 243       value >>= 8;
 244     }
 245
 246   /* Nothing found.  */
 247   return 0;
 248 }
 249
 250
 251 static long int  __attribute__ ((noinline))
 252 handle_intel (int name, unsigned int maxidx)
 253 {
 254   if (maxidx < 2)
 255     {
 256       // XXX Do such processors exist?  When we know we can fill in some
 257       // values.
 258       return 0;
 259     }
 260
 261   /* OK, we can use the CPUID instruction to get all info about the
 262      caches.  */
 263   unsigned int cnt = 0;
 264   unsigned int max = 1;
 265   long int result = 0;
 266   bool no_level_2_or_3 = false;
 267   bool has_level_2 = false;
 268   while (cnt++ < max)
 269     {
 270       unsigned int eax;
 271       unsigned int ebx;
 272       unsigned int ecx;
 273       unsigned int edx;
 274       asm volatile ("xchgl %%ebx, %1; cpuid; xchgl %%ebx, %1"
 275                     : "=a" (eax), "=r" (ebx), "=c" (ecx), "=d" (edx)
 276                     : "0" (2));
 277
 278       /* The low byte of EAX in the first round contain the number of
 279          rounds we have to make.  At least one, the one we are already
 280          doing.  */
 281       if (cnt == 1)
 282         {
 283           max = eax & 0xff;
 284           eax &= 0xffffff00;
 285         }
 286
 287       /* Process the individual registers' value.  */
 288       result = intel_check_word (name, eax, &has_level_2, &no_level_2_or_3);
 289       if (result != 0)
 290         return result;
 291
 292       result = intel_check_word (name, ebx, &has_level_2, &no_level_2_or_3);
 293       if (result != 0)
 294         return result;
 295
 296       result = intel_check_word (name, ecx, &has_level_2, &no_level_2_or_3);
 297       if (result != 0)
 298         return result;
 299
 300       result = intel_check_word (name, edx, &has_level_2, &no_level_2_or_3);
 301       if (result != 0)
 302         return result;
 303     }
 304
 305   if (name >= _SC_LEVEL2_CACHE_SIZE && name <= _SC_LEVEL3_CACHE_LINESIZE
 306       && no_level_2_or_3)
 307     return -1;
 308
 309   return 0;
 310 }
 311
 312
 313 static long int __attribute__ ((noinline))
 314 handle_amd (int name)
 315 {
 316   unsigned int eax;
 317   unsigned int ebx;
 318   unsigned int ecx;
 319   unsigned int edx;
 320   asm volatile ("xchgl %%ebx, %1; cpuid; xchgl %%ebx, %1"
 321                 : "=a" (eax), "=r" (ebx), "=c" (ecx), "=d" (edx)
 322                 : "0" (0x80000000));
 323
 324   if (name >= _SC_LEVEL3_CACHE_SIZE)
 325     return 0;
 326
 327   unsigned int fn = 0x80000005 + (name >= _SC_LEVEL2_CACHE_SIZE);
 328   if (eax < fn)
 329     return 0;
 330
 331   asm volatile ("xchgl %%ebx, %1; cpuid; xchgl %%ebx, %1"
 332                 : "=a" (eax), "=r" (ebx), "=c" (ecx), "=d" (edx)
 333                 : "0" (fn));
 334
 335   if (name < _SC_LEVEL1_DCACHE_SIZE)
 336     {
 337       name += _SC_LEVEL1_DCACHE_SIZE - _SC_LEVEL1_ICACHE_SIZE;
 338       ecx = edx;
 339     }
 340
 341   switch (name)
 342     {
 343     case _SC_LEVEL1_DCACHE_SIZE:
 344       return (ecx >> 14) & 0x3fc00;
 345     case _SC_LEVEL1_DCACHE_ASSOC:
 346       ecx >>= 16;
 347       if ((ecx & 0xff) == 0xff)
 348         /* Fully associative.  */
 349         return (ecx << 2) & 0x3fc00;
 350       return ecx & 0xff;
 351     case _SC_LEVEL1_DCACHE_LINESIZE:
 352       return ecx & 0xff;
 353     case _SC_LEVEL2_CACHE_SIZE:
 354       return (ecx & 0xf000) == 0 ? 0 : (ecx >> 6) & 0x3fffc00;
 355     case _SC_LEVEL2_CACHE_ASSOC:
 356       ecx >>= 12;
 357       switch (ecx & 0xf)
 358         {
 359         case 0:
 360         case 1:
 361         case 2:
 362         case 4:
 363           return ecx & 0xf;
 364         case 6:
 365           return 8;
 366         case 8:
 367           return 16;
 368         case 0xf:
 369           return (ecx << 6) & 0x3fffc00;
 370         default:
 371           return 0;
 372         }
 373     case _SC_LEVEL2_CACHE_LINESIZE:
 374       return (ecx & 0xf000) == 0 ? 0 : ecx & 0xff;
 375     default:
 376       assert (! "cannot happen");
 377     }
 378   return -1;
 379 }
 380
 381
 382 static int
 383 i386_i486_test (void)
 384 {
 385   int eflags;
 386   int ac;
 387   asm volatile ("pushfl;\n\t"
 388                 "popl %0;\n\t"
 389                 "movl $0x240000, %1;\n\t"
 390                 "xorl %0, %1;\n\t"
 391                 "pushl %1;\n\t"
 392                 "popfl;\n\t"
 393                 "pushfl;\n\t"
 394                 "popl %1;\n\t"
 395                 "xorl %0, %1;\n\t"
 396                 "pushl %0;\n\t"
 397                 "popfl"
 398                 : "=r" (eflags), "=r" (ac));
 399
 400   return ac;
 401 }
 402
 403
 404 /* Get the value of the system variable NAME.  */
 405 long int
 406 __sysconf (int name)
 407 {
 408   /* All the remainder, except the cache information, is handled in
 409      the generic code.  */
 410   if (name < _SC_LEVEL1_ICACHE_SIZE || name > _SC_LEVEL4_CACHE_LINESIZE)
 411     return linux_sysconf (name);
 412
 413   /* Recognize i386 and compatible.  These don't have any cache on
 414      board.  */
 415   int ac = i386_i486_test ();
 416
 417   if (ac == 0)
 418     /* This is an i386.  */
 419     // XXX Is this true for all brands?
 420     return -1;
 421
 422   /* Detect i486, the last Intel processor without CPUID.  */
 423   if ((ac & (1 << 21)) == 0)
 424     {
 425       /* No CPUID.  */
 426       // XXX Fill in info about other brands.  For now only Intel.
 427       return handle_i486 (name);
 428     }
 429
 430   /* Find out what brand of processor.  */
 431   unsigned int eax;
 432   unsigned int ebx;
 433   unsigned int ecx;
 434   unsigned int edx;
 435   asm volatile ("xchgl %%ebx, %1; cpuid; xchgl %%ebx, %1"
 436                 : "=a" (eax), "=r" (ebx), "=c" (ecx), "=d" (edx)
 437                 : "0" (0));
 438
 439   /* This spells out "GenuineIntel".  */
 440   if (ebx == 0x756e6547 && ecx == 0x6c65746e && edx == 0x49656e69)
 441     return handle_intel (name, eax);
 442
 443   /* This spells out "AuthenticAMD".  */
 444   if (ebx == 0x68747541 && ecx == 0x444d4163 && edx == 0x69746e65)
 445     return handle_amd (name);
 446
 447   // XXX Fill in more vendors.
 448
 449   /* CPU not known, we have no information.  */
 450   return 0;
 451 }
 452
 453 /* Now the generic Linux version.  */
 454 #undef __sysconf
 455 #define __sysconf static linux_sysconf
 456 #include "../sysconf.c"