sysdeps/unix/sysv/linux/x86_64/sysconf.c

   1 /* Get file-specific information about a file.  Linux version.
   2    Copyright (C) 2003, 2004, 2006 Free Software Foundation, Inc.
   3    This file is part of the GNU C Library.
   4
   5    The GNU C Library is free software; you can redistribute it and/or
   6    modify it under the terms of the GNU Lesser General Public
   7    License as published by the Free Software Foundation; either
   8    version 2.1 of the License, or (at your option) any later version.
   9
  10    The GNU C Library is distributed in the hope that it will be useful,
  11    but WITHOUT ANY WARRANTY; without even the implied warranty of
  12    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  13    Lesser General Public License for more details.
  14
  15    You should have received a copy of the GNU Lesser General Public
  16    License along with the GNU C Library; if not, write to the Free
  17    Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
  18    02111-1307 USA.  */
  19
  20 #include <assert.h>
  21 #include <stdbool.h>
  22 #include <stdlib.h>
  23 #include <unistd.h>
  24
  25
  26 static long int linux_sysconf (int name);
  27
  28
  29 static const struct intel_02_cache_info
  30 {
  31   unsigned int idx;
  32   int name;
  33   long int size;
  34   long int assoc;
  35   long int linesize;
  36 } intel_02_known[] =
  37   {
  38     { 0x06, _SC_LEVEL1_ICACHE_SIZE, 8192, 4, 32 },
  39     { 0x08, _SC_LEVEL1_ICACHE_SIZE, 16384, 4, 32 },
  40     { 0x0a, _SC_LEVEL1_DCACHE_SIZE, 8192, 2, 32 },
  41     { 0x0c, _SC_LEVEL1_DCACHE_SIZE, 16384, 4, 32 },
  42     { 0x22, _SC_LEVEL3_CACHE_SIZE, 524288, 4, 64 },
  43     { 0x23, _SC_LEVEL3_CACHE_SIZE, 1048576, 8, 64 },
  44     { 0x25, _SC_LEVEL3_CACHE_SIZE, 2097152, 8, 64 },
  45     { 0x29, _SC_LEVEL3_CACHE_SIZE, 4194304, 8, 64 },
  46     { 0x2c, _SC_LEVEL1_DCACHE_SIZE, 32768, 8, 64 },
  47     { 0x30, _SC_LEVEL1_ICACHE_SIZE, 32768, 8, 64 },
  48     { 0x39, _SC_LEVEL2_CACHE_SIZE, 131072, 4, 64 },
  49     { 0x3a, _SC_LEVEL2_CACHE_SIZE, 196608, 6, 64 },
  50     { 0x3b, _SC_LEVEL2_CACHE_SIZE, 131072, 2, 64 },
  51     { 0x3c, _SC_LEVEL2_CACHE_SIZE, 262144, 4, 64 },
  52     { 0x3d, _SC_LEVEL2_CACHE_SIZE, 393216, 6, 64 },
  53     { 0x3e, _SC_LEVEL2_CACHE_SIZE, 524288, 4, 64 },
  54     { 0x41, _SC_LEVEL2_CACHE_SIZE, 131072, 4, 32 },
  55     { 0x42, _SC_LEVEL2_CACHE_SIZE, 262144, 4, 32 },
  56     { 0x43, _SC_LEVEL2_CACHE_SIZE, 524288, 4, 32 },
  57     { 0x44, _SC_LEVEL2_CACHE_SIZE, 1048576, 4, 32 },
  58     { 0x45, _SC_LEVEL2_CACHE_SIZE, 2097152, 4, 32 },
  59     { 0x46, _SC_LEVEL3_CACHE_SIZE, 4194304, 4, 64 },
  60     { 0x47, _SC_LEVEL3_CACHE_SIZE, 8388608, 8, 64 },
  61     { 0x49, _SC_LEVEL2_CACHE_SIZE, 4194304, 16, 64 },
  62     { 0x4a, _SC_LEVEL3_CACHE_SIZE, 6291456, 12, 64 },
  63     { 0x4b, _SC_LEVEL3_CACHE_SIZE, 8388608, 16, 64 },
  64     { 0x4c, _SC_LEVEL3_CACHE_SIZE, 12582912, 12, 64 },
  65     { 0x4d, _SC_LEVEL3_CACHE_SIZE, 16777216, 16, 64 },
  66     { 0x60, _SC_LEVEL1_DCACHE_SIZE, 16384, 8, 64 },
  67     { 0x66, _SC_LEVEL1_DCACHE_SIZE, 8192, 4, 64 },
  68     { 0x67, _SC_LEVEL1_DCACHE_SIZE, 16384, 4, 64 },
  69     { 0x68, _SC_LEVEL1_DCACHE_SIZE, 32768, 4, 64 },
  70     { 0x78, _SC_LEVEL2_CACHE_SIZE, 1048576, 8, 64 },
  71     { 0x79, _SC_LEVEL2_CACHE_SIZE, 131072, 8, 64 },
  72     { 0x7a, _SC_LEVEL2_CACHE_SIZE, 262144, 8, 64 },
  73     { 0x7b, _SC_LEVEL2_CACHE_SIZE, 524288, 8, 64 },
  74     { 0x7c, _SC_LEVEL2_CACHE_SIZE, 1048576, 8, 64 },
  75     { 0x7d, _SC_LEVEL2_CACHE_SIZE, 2097152, 8, 64 },
  76     { 0x7f, _SC_LEVEL2_CACHE_SIZE, 524288, 2, 64 },
  77     { 0x82, _SC_LEVEL2_CACHE_SIZE, 262144, 8, 32 },
  78     { 0x83, _SC_LEVEL2_CACHE_SIZE, 524288, 8, 32 },
  79     { 0x84, _SC_LEVEL2_CACHE_SIZE, 1048576, 8, 32 },
  80     { 0x85, _SC_LEVEL2_CACHE_SIZE, 2097152, 8, 32 },
  81     { 0x86, _SC_LEVEL2_CACHE_SIZE, 524288, 4, 64 },
  82     { 0x87, _SC_LEVEL2_CACHE_SIZE, 1048576, 8, 64 },
  83   };
  84 #define nintel_02_known (sizeof (intel_02_known) / sizeof (intel_02_known[0]))
  85
  86
  87 static int
  88 intel_02_known_compare (const void *p1, const void *p2)
  89 {
  90   const struct intel_02_cache_info *i1;
  91   const struct intel_02_cache_info *i2;
  92
  93   i1 = (const struct intel_02_cache_info *) p1;
  94   i2 = (const struct intel_02_cache_info *) p2;
  95
  96   if (i1->idx == i2->idx)
  97     return 0;
  98
  99   return i1->idx < i2->idx ? -1 : 1;
 100 }
 101
 102
 103 static long int
 104 intel_check_word (int name, unsigned int value, bool *has_level_2,
 105                   bool *no_level_2_or_3)
 106 {
 107   if ((value & 0x80000000) != 0)
 108     /* The register value is reserved.  */
 109     return 0;
 110
 111   /* Fold the name.  The _SC_ constants are always in the order SIZE,
 112      ASSOC, LINESIZE.  */
 113   int folded_name = (_SC_LEVEL1_ICACHE_SIZE
 114                      + ((name - _SC_LEVEL1_ICACHE_SIZE) / 3) * 3);
 115
 116   while (value != 0)
 117     {
 118       unsigned int byte = value & 0xff;
 119
 120       if (byte == 0x40)
 121         {
 122           *no_level_2_or_3 = true;
 123
 124           if (folded_name == _SC_LEVEL3_CACHE_SIZE)
 125             /* No need to look further.  */
 126             break;
 127         }
 128       else
 129         {
 130           if (byte == 0x49 && folded_name == _SC_LEVEL3_CACHE_SIZE)
 131             {
 132               /* Intel reused this value.  For family 15, model 6 it
 133                  specifies the 3rd level cache.  Otherwise the 2nd
 134                  level cache.  */
 135               unsigned int eax;
 136               unsigned int ebx;
 137               unsigned int ecx;
 138               unsigned int edx;
 139               asm volatile ("xchgl %%ebx, %1; cpuid; xchgl %%ebx, %1"
 140                             : "=a" (eax), "=r" (ebx), "=c" (ecx), "=d" (edx)
 141                             : "0" (1));
 142
 143               unsigned int family = ((eax >> 20) & 0xff) + ((eax >> 8) & 0xf);
 144               unsigned int model = ((((eax >>16) & 0xf) << 4)
 145                                     + ((eax >> 4) & 0xf));
 146               if (family == 15 && model == 6)
 147                 {
 148                   /* The level 3 cache is encoded for this model like
 149                      the level 2 cache is for other models.  Pretend
 150                      the caller asked for the level 2 cache.  */
 151                   name = (_SC_LEVEL2_CACHE_SIZE
 152                           + (name - _SC_LEVEL3_CACHE_SIZE));
 153                   folded_name = _SC_LEVEL3_CACHE_SIZE;
 154                 }
 155             }
 156
 157           struct intel_02_cache_info *found;
 158           struct intel_02_cache_info search;
 159
 160           search.idx = byte;
 161           found = bsearch (&search, intel_02_known, nintel_02_known,
 162                            sizeof (intel_02_known[0]), intel_02_known_compare);
 163           if (found != NULL)
 164             {
 165               if (found->name == folded_name)
 166                 {
 167                   unsigned int offset = name - folded_name;
 168
 169                   if (offset == 0)
 170                     /* Cache size.  */
 171                     return found->size;
 172                   if (offset == 1)
 173                     return found->assoc;
 174
 175                   assert (offset == 2);
 176                   return found->linesize;
 177                 }
 178
 179               if (found->name == _SC_LEVEL2_CACHE_SIZE)
 180                 *has_level_2 = true;
 181             }
 182         }
 183
 184       /* Next byte for the next round.  */
 185       value >>= 8;
 186     }
 187
 188   /* Nothing found.  */
 189   return 0;
 190 }
 191
 192
 193 static long int __attribute__ ((noinline))
 194 handle_intel (int name, unsigned int maxidx)
 195 {
 196   assert (maxidx >= 2);
 197
 198   /* OK, we can use the CPUID instruction to get all info about the
 199      caches.  */
 200   unsigned int cnt = 0;
 201   unsigned int max = 1;
 202   long int result = 0;
 203   bool no_level_2_or_3 = false;
 204   bool has_level_2 = false;
 205   while (cnt++ < max)
 206     {
 207       unsigned int eax;
 208       unsigned int ebx;
 209       unsigned int ecx;
 210       unsigned int edx;
 211       asm volatile ("xchgl %%ebx, %1; cpuid; xchgl %%ebx, %1"
 212                     : "=a" (eax), "=r" (ebx), "=c" (ecx), "=d" (edx)
 213                     : "0" (2));
 214
 215       /* The low byte of EAX in the first round contain the number of
 216          rounds we have to make.  At least one, the one we are already
 217          doing.  */
 218       if (cnt == 1)
 219         {
 220           max = eax & 0xff;
 221           eax &= 0xffffff00;
 222         }
 223
 224       /* Process the individual registers' value.  */
 225       result = intel_check_word (name, eax, &has_level_2, &no_level_2_or_3);
 226       if (result != 0)
 227         return result;
 228
 229       result = intel_check_word (name, ebx, &has_level_2, &no_level_2_or_3);
 230       if (result != 0)
 231         return result;
 232
 233       result = intel_check_word (name, ecx, &has_level_2, &no_level_2_or_3);
 234       if (result != 0)
 235         return result;
 236
 237       result = intel_check_word (name, edx, &has_level_2, &no_level_2_or_3);
 238       if (result != 0)
 239         return result;
 240     }
 241
 242   if (name >= _SC_LEVEL2_CACHE_SIZE && name <= _SC_LEVEL3_CACHE_LINESIZE
 243       && no_level_2_or_3)
 244     return -1;
 245
 246   return 0;
 247 }
 248
 249
 250 static long int __attribute__ ((noinline))
 251 handle_amd (int name)
 252 {
 253   unsigned int eax;
 254   unsigned int ebx;
 255   unsigned int ecx;
 256   unsigned int edx;
 257   asm volatile ("xchgl %%ebx, %1; cpuid; xchgl %%ebx, %1"
 258                 : "=a" (eax), "=r" (ebx), "=c" (ecx), "=d" (edx)
 259                 : "0" (0x80000000));
 260
 261   if (name >= _SC_LEVEL3_CACHE_SIZE)
 262     return 0;
 263
 264   unsigned int fn = 0x80000005 + (name >= _SC_LEVEL2_CACHE_SIZE);
 265   if (eax < fn)
 266     return 0;
 267
 268   asm volatile ("xchgl %%ebx, %1; cpuid; xchgl %%ebx, %1"
 269                 : "=a" (eax), "=r" (ebx), "=c" (ecx), "=d" (edx)
 270                 : "0" (fn));
 271
 272   if (name < _SC_LEVEL1_DCACHE_SIZE)
 273     {
 274       name += _SC_LEVEL1_DCACHE_SIZE - _SC_LEVEL1_ICACHE_SIZE;
 275       ecx = edx;
 276     }
 277
 278   switch (name)
 279     {
 280     case _SC_LEVEL1_DCACHE_SIZE:
 281       return (ecx >> 14) & 0x3fc00;
 282     case _SC_LEVEL1_DCACHE_ASSOC:
 283       ecx >>= 16;
 284       if ((ecx & 0xff) == 0xff)
 285         /* Fully associative.  */
 286         return (ecx << 2) & 0x3fc00;
 287       return ecx & 0xff;
 288     case _SC_LEVEL1_DCACHE_LINESIZE:
 289       return ecx & 0xff;
 290     case _SC_LEVEL2_CACHE_SIZE:
 291       return (ecx & 0xf000) == 0 ? 0 : (ecx >> 6) & 0x3fffc00;
 292     case _SC_LEVEL2_CACHE_ASSOC:
 293       ecx >>= 12;
 294       switch (ecx & 0xf)
 295         {
 296         case 0:
 297         case 1:
 298         case 2:
 299         case 4:
 300           return ecx & 0xf;
 301         case 6:
 302           return 8;
 303         case 8:
 304           return 16;
 305         case 0xf:
 306           return (ecx << 6) & 0x3fffc00;
 307         default:
 308           return 0;
 309         }
 310     case _SC_LEVEL2_CACHE_LINESIZE:
 311       return (ecx & 0xf000) == 0 ? 0 : ecx & 0xff;
 312     default:
 313       assert (! "cannot happen");
 314     }
 315   return -1;
 316 }
 317
 318
 319 /* Get the value of the system variable NAME.  */
 320 long int
 321 __sysconf (int name)
 322 {
 323   /* We only handle the cache information here (for now).  */
 324   if (name < _SC_LEVEL1_ICACHE_SIZE || name > _SC_LEVEL4_CACHE_LINESIZE)
 325     return linux_sysconf (name);
 326
 327   /* Find out what brand of processor.  */
 328   unsigned int eax;
 329   unsigned int ebx;
 330   unsigned int ecx;
 331   unsigned int edx;
 332   asm volatile ("xchgl %%ebx, %1; cpuid; xchgl %%ebx, %1"
 333                 : "=a" (eax), "=r" (ebx), "=c" (ecx), "=d" (edx)
 334                 : "0" (0));
 335
 336   /* This spells out "GenuineIntel".  */
 337   if (ebx == 0x756e6547 && ecx == 0x6c65746e && edx == 0x49656e69)
 338     return handle_intel (name, eax);
 339
 340   /* This spells out "AuthenticAMD".  */
 341   if (ebx == 0x68747541 && ecx == 0x444d4163 && edx == 0x69746e65)
 342     return handle_amd (name);
 343
 344   // XXX Fill in more vendors.
 345
 346   /* CPU not known, we have no information.  */
 347   return 0;
 348 }
 349
 350 /* Now the generic Linux version.  */
 351 #undef __sysconf
 352 #define __sysconf static linux_sysconf
 353 #include "../sysconf.c"