src/d_digital.h

   1 /*$Id: d_logic.h,v 1.4 2009-12-13 17:55:01 felix Exp $ -*- C++ -*-
   2  * vim:ts=8:sw=2:et:
   3  * Copyright (C) 2001 Albert Davis
   4  * Author: Albert Davis <aldavis@gnu.org>
   5  *
   6  * This file is part of "Gnucap", the Gnu Circuit Analysis Package
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 3, or (at your option)
  11  * any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
  21  * 02110-1301, USA.
  22  *------------------------------------------------------------------
  23  * data structures and defaults for logic model.
  24  */
  25 //testing=script,sparse 2006.07.17
  26 #ifndef D_DIGITAL_H
  27 #define D_DIGITAL_H
  28 #include "e_model.h"
  29 #include "e_elemnt.h"
  30 /*--------------------------------------------------------------------------*/
  31 enum {PORTS_PER_GATE = 10};
  32 /*--------------------------------------------------------------------------*/
  33 class DEV_DIGITAL : public ELEMENT {
  34 public:
  35   enum {OUTNODE=0,GND_NODE=1,PWR_NODE=2,ENABLE=3,BEGIN_IN=4}; //node labels
  36 private:
  37   int           _lastchangenode;
  38   int           _quality;
  39   std::string   _failuremode;
  40   smode_t       _oldgatemode;
  41   smode_t       _gatemode;
  42   static int    _count;
  43   node_t        nodes[PORTS_PER_GATE];  /* PORTS_PER_GATE <= PORTSPERSUBCKT */
  44 public:
  45   explicit      DEV_DIGITAL();
  46   explicit      DEV_DIGITAL(const DEV_DIGITAL& p);
  47                 ~DEV_DIGITAL()          {--_count;}
  48 private: // override virtuals
  49   char     id_letter()const     {return 'U';}
  50   std::string value_name()const {return "#";}
  51   bool        print_type_in_spice()const {return true;}
  52   std::string dev_type()const {assert(has_common());
  53     return (common()->modelname() + " " + common()->name()).c_str();}
  54   int      tail_size()const     {return 2;}
  55   int      max_nodes()const     {return PORTS_PER_GATE;}
  56   int      min_nodes()const     {return BEGIN_IN+1;}
  57   virtual int matrix_nodes()const       {return 2;}
  58   int      net_nodes()const     {return _net_nodes;}
  59   CARD*    clone()const         {return new DEV_DIGITAL(*this);}
  60   void     precalc_first() {ELEMENT::precalc_first(); if (subckt()) {subckt()->precalc_first();}}
  61   void     expand();
  62   void     precalc_last() {ELEMENT::precalc_last(); if (subckt()) {subckt()->precalc_last();}}
  63   //void   map_nodes();
  64
  65   void     tr_iwant_matrix();
  66   void     tr_begin();
  67   void     tr_restore();
  68   void     dc_advance();
  69   void     tr_advance();
  70   void     tr_regress();
  71   bool     tr_needs_eval()const;
  72   void     tr_queue_eval();
  73   bool     do_tr();
  74   void     tr_load();
  75   TIME_PAIR tr_review();
  76   void     tr_accept();
  77   void     tr_unload();
  78   hp_float_t   tr_involts()const                {unreachable(); return 0;}
  79   //double tr_input()const              //ELEMENT
  80   hp_float_t   tr_involts_limited()const        {unreachable(); return 0;}
  81   //double tr_input_limited()const      //ELEMENT
  82   //double tr_amps()const               //ELEMENT
  83   double   tr_probe_num(const std::string&)const;
  84
  85   void     ac_iwant_matrix();
  86   void     ac_begin();
  87   void     do_ac()      {untested();  assert(subckt());  subckt()->do_ac();}
  88   void     tt_next();
  89   void     ac_load()    {untested();  assert(subckt());  subckt()->ac_load();}
  90   COMPLEX  ac_involts()const            {unreachable(); return 0.;}
  91   COMPLEX  ac_amps()const               {unreachable(); return 0.;}
  92   XPROBE   ac_probe_ext(const std::string&)const;
  93
  94   std::string port_name(int)const {untested();
  95     incomplete();
  96     return "";
  97   }
  98 public:
  99   static int count()                    {return _count;}
 100 private:
 101   bool     tr_eval_digital();
 102   bool     want_analog()const;
 103   bool     want_digital()const;
 104 };
 105 /*--------------------------------------------------------------------------*/
 106 class MODEL_DIGITAL : public MODEL_CARD {
 107 private:
 108   explicit      MODEL_DIGITAL(const MODEL_DIGITAL& p);
 109 public:
 110   explicit MODEL_DIGITAL(const DEV_DIGITAL*);
 111            ~MODEL_DIGITAL()             {--_count;}
 112 private: // override virtuals
 113   std::string   dev_type()const         {return "logic";}
 114   CARD*         clone()const            {return new MODEL_DIGITAL(*this);}
 115   void          precalc_first();
 116   void          set_param_by_index(int, std::string&, int);
 117   bool          param_is_printable(int)const;
 118   std::string   param_name(int)const;
 119   std::string   param_name(int,int)const;
 120   std::string   param_value(int)const;
 121   int           param_count()const      {return (13 + MODEL_CARD::param_count());}
 122 public:
 123   static int    count()                 {return _count;}
 124 public:
 125                         /* ----- digital mode ----- */
 126   PARAMETER<double> delay;      /* propagation delay */
 127                         /* -- conversion parameters both ways -- */
 128   PARAMETER<double> vmax;       /* nominal volts for logic 1 */
 129   PARAMETER<double> vmin;       /* nominal volts for logic 0 */
 130   PARAMETER<double> unknown;    /* nominal volts for unknown (bogus) */
 131                         /* ---- D to A conversion ---- */
 132   PARAMETER<double> rise;       /* rise time (time in slope) */
 133   PARAMETER<double> fall;       /* fall time (time in slope) */
 134   PARAMETER<double> rs;         /* series resistance -- strong */
 135   PARAMETER<double> rw;         /* series resistance -- weak */
 136                         /* ---- A to D conversion ---- */
 137   PARAMETER<double> th1;        /* threshold for 1 as fraction of range */
 138   PARAMETER<double> th0;        /* threshold for 0 as fraction of range */
 139                         /* ---- quality judgement parameters ---- */
 140   PARAMETER<double> mr;         /* margin rise - how much worse rise can be */
 141   PARAMETER<double> mf;         /* margin fall - how much worse fall can be */
 142   PARAMETER<double> over;       /* overshoot limit - as fraction of range */
 143 public: // calculated parameters
 144   double range;                 /* vmax - vmin */
 145 private:
 146   static int _count;
 147 };
 148 /*--------------------------------------------------------------------------*/
 149 class INTERFACE COMMON_DIGITAL : public COMMON_COMPONENT {
 150 protected:
 151   explicit      COMMON_DIGITAL(int c=0)
 152     :COMMON_COMPONENT(c), incount(0) {++_count;}
 153   explicit      COMMON_DIGITAL(const COMMON_DIGITAL& p)
 154     :COMMON_COMPONENT(p), incount(p.incount) {++_count;}
 155 public:
 156                 ~COMMON_DIGITAL()                       {--_count;}
 157   bool operator==(const COMMON_COMPONENT&)const;
 158   static  int   count()                         {return _count;}
 159   virtual LOGICVAL logic_eval(const node_t*)const       = 0;
 160 public:
 161   int           incount;
 162 protected:
 163   static int    _count;
 164 };
 165 /*--------------------------------------------------------------------------*/
 166 /*--------------------------------------------------------------------------
 167 class LOGIC_INV : public COMMON_LOGIC {
 168 private:
 169   explicit LOGIC_INV(const LOGIC_INV& p) :COMMON_LOGIC(p){++_count;}
 170   COMMON_COMPONENT* clone()const        {return new LOGIC_INV(*this);}
 171 public:
 172   explicit LOGIC_INV(int c=0)             :COMMON_LOGIC(c) {}
 173   LOGICVAL logic_eval(const node_t* n)const {
 174     return ~n[0]->lv();
 175   }
 176   virtual std::string name()const         {return "inv";}
 177 };
 178 --------------------------------------------------------------------------*/
 179 #endif