src/d_invert.v

   1 `timescale 10ps/1ps
   2
   3 module invert (out,in);
   4    input in;
   5    output reg out;
   6
   7         parameter inv_delay = 260; // inverter delay in ps
   8         // parameters for AD and DA conversion come from LOGIC_MODEL
   9
  10    always @(in) begin
  11       out <= #inv_delay !in;
  12                 // not implemented.
  13                 //$display($realtime, " inverter sees ", in);
  14    end
  15 endmodule