interactive testing
[gnucap-felix.git] / src / extlib.h
blob4257b9dc5d4fce7b73e460ddcfe2524e7ba58362
1 /*$Id$
2 * vim:sw=2:et:ts=8:
3 * Copyright (C) 2009 Kevin Cameron
4 * Authors: Kevin Cameron
6 * This file is a part of plugin "Gnucap-Icarus" to "Gnucap",
7 * the Gnu Circuit Analysis Package
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 3, or (at your option)
12 * any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
22 * 02110-1301, USA.
23 *------------------------------------------------------------------
24 * Dynamic binding of PWL signal sources to external simulators
26 * mostly obsolete for DEV_VVP
27 * TODO: merge needed stuff into COMMON_VVP
32 #ifndef EXT_H_LIB
33 #define EXT_H_LIB
34 #include "vvp/vpi_priv.h"
35 //#include "extpwl.h"
36 #include "e_compon.h"
37 #include "e_elemnt.h"
38 #include <dlfcn.h>
40 # include "vvp/compile.h"
41 # include "vvp/schedule.h"
42 # include "vvp/vpi_priv.h"
43 # include "vvp/statistics.h"
44 # include "vvp/vvp_cleanup.h"
45 # include <cstdio>
46 # include <csignal>
47 # include <cstdlib>
48 # include <cstring>
49 # include <unistd.h>
51 // trace facility from gnucap
52 # include "io_trace.h"
54 #if defined(HAVE_SYS_RESOURCE_H)
55 # include <sys/time.h>
56 # include <sys/resource.h>
57 #endif // defined(HAVE_SYS_RESOURCE_H)
59 # define EXT_BAS 0
60 # define EXT_REF 1
61 # define EXT_SIG 2
63 // extern void schedule_simulate(void);
64 //extern void vpip_mcd_init(FILE *log);
67 class ExtBase {
68 public:
69 virtual int id() {return 0;}
70 static void null_call() { unreachable(); }
71 virtual ~ExtBase(){}
74 struct SpcDllData {
75 char active;
76 double next_time;
78 void* El;
81 // schnittstelle zu digisim
82 class ExtAPI : public SpcDllData {
83 public:
85 //void *(*bindnet)(const char *,char,int *,void *,void (*)(void *,void *,double));
86 double (*startsim)(const char *);
87 void (*endsim)();
88 double (*contsim)(const char *,double);
89 int (*so_main)(const char*);
90 void (*activate)(void *,void *,double);
93 ExtAPI() {
94 startsim = (typeof(startsim))ExtBase::null_call;
95 endsim = (typeof(endsim))ExtBase::null_call;
96 //bindnet = (typeof(bindnet))ExtBase::null_call;
97 contsim = (typeof(contsim))ExtBase::null_call;
98 activate = (typeof(activate))ExtBase::null_call;
99 so_main = (typeof(so_main))ExtBase::null_call;
103 class ExtLib : public ExtAPI , public COMPONENT {
104 public:
105 std::list<class ExtRef*> refs;
106 std::string name;
107 void *handle;
108 double now;
109 ExtLib(const char *_nm,void *_hndl) : name(_nm), handle(_hndl), now(-1) {
110 El=this;
112 int init(const char *);
113 static void SetActive(void *dl,void *handle,double time);
114 void set_active(void *handle,double time);
115 virtual std::string value_name() const {return name;}
116 virtual bool print_type_in_spice() const {return false;}
117 static ExtLib *Sdd2El(SpcDllData *spd) {
118 return (ExtLib*) spd->El;
119 //intptr_t p = (intptr_t)spd;
120 //p -= offsetof(ExtLib,active);
121 //return (ExtLib *)p;
123 private:
124 ExtLib();
126 public:
127 virtual std::string port_name(uint_t)const {return "";}
130 class ExtSig : public ExtBase {
131 public:
132 virtual int id() {return EXT_SIG;}
134 COMMON_COMPONENT *cmpnt;
136 ExtLib *lib;
137 void *cb_data;
138 int slots;
139 char iv;
140 ELEMENT *d;
142 void set_active(double time);
143 static void SetActive(void *,void *,double);
145 ExtSig(COMMON_COMPONENT *_c,ExtLib *_l,char _iv,void *)
146 : cmpnt(_c), lib(_l), iv(_iv){}
148 private:
149 ExtSig();
151 public:
152 LOGICVAL get_logic(){
154 // SpcIvlCB *cbd = cb_data;
155 //double time0 = CKT_BASE::_sim->_time0,*dp,nxt;
156 // assert(lib->d == d);
157 // dp = (*cbd->eval)(cbd,time0,CB_LOAD,getVoltage,xsig,0);
158 return lvUNKNOWN;
163 class ExtRef : public ExtBase {
164 public:
165 virtual int id() {return EXT_REF;}
167 std::list<ExtSig*> sigs;
169 ExtLib *lib;
170 std::string spec;
171 char iv;
173 ExtRef(ExtLib *_l,const char *sig_spec,char _iv)
174 : lib(_l), spec(sig_spec), iv(_iv) {
175 trace1(("ExtRef() baue "+spec ).c_str(), iv );
176 lib->refs.push_back(this);
181 class ExtControl{
182 ExtRef *bindExtSigInit(const string &,const char *);
183 ExtSig *bindExtSigConnect(intptr_t,const string &,
184 const CARD_LIST* Scope,COMMON_COMPONENT *);
185 void ExtSigTrEval(intptr_t,std::vector<DPAIR>*,ELEMENT*);
186 double ExtSigTrCheck(intptr_t,double,std::vector<DPAIR>*,COMPONENT*);
188 void ExtStartSim(const char *);
189 void ExtContSim(const char *,double);
190 void ExtEndSim(double);
193 void PrintInst(FILE *fp,struct __vpiScope *scope);
195 /*------------------------------------------------------------*/
197 #endif