src/d_clock.v

   1 `timescale 10ps/1ps  // <- not implemented yet.
   2
   3 /*
   4 nature Voltage;
   5 units      = "V";
   6 access     = V;
   7 idt_nature = Flux;
   8 `ifdef VOLTAGE_ABSTOL
   9         abstol     = `VOLTAGE_ABSTOL;
  10 `else
  11         abstol     = 1e-6;
  12 `endif
  13 endnature
  14
  15 nature Current;
  16 units      = "A";
  17 access     = I;
  18 idt_nature = Charge;
  19 `ifdef CURRENT_ABSTOL
  20         abstol     = `CURRENT_ABSTOL
  21 `else
  22         abstol     = 1e-12;
  23 `endif
  24 endnature
  25
  26
  27 discipline electrical;
  28         potential Voltage;
  29         flow Current;
  30 enddiscipline
  31 */
  32
  33 module clock (out);
  34         output out;
  35         reg out;
  36    // wire out; ?
  37         //      electrical out;
  38
  39         parameter width = 500;
  40         parameter period = 1000;
  41         parameter iv = 0;
  42         parameter delay = 0;
  43
  44
  45         initial begin
  46                 out = iv;
  47                 out <= #(delay+width) !iv;
  48                 #(delay+width);
  49                 forever begin
  50                         out <= #width   iv;
  51                         #width;
  52                         out <= #(period-width)  !iv;
  53                         #(period-width);
  54                 end
  55         end
  56         /*
  57         always @( posedge out ) begin
  58                 #(width-notify);
  59                 out <= #notify  !out;
  60    end
  61         always @( negedge out ) begin
  62         end
  63         */
  64
  65 //      analog begin
  66 //              V(out) <+ transition( vout_val, tdelay, trise, tfall);
  67 //      end
  68
  69 endmodule