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Add errfile definition for new e1000.c
[gpxe.git] / src / drivers / net / e1000 / e1000_main.c
blobef801aff9a7132f46fae7eb03a28cbdce5956529
1 /*******************************************************************************
2
3 Intel PRO/1000 Linux driver
4 Copyright(c) 1999 - 2006 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27 *******************************************************************************/
28
29 #include "e1000.h"
30
31 static struct pci_device_id e1000_nics[] = {
32 PCI_ROM(0x8086, 0x1000, "e1000-0x1000", "E1000-0x1000"),
33 PCI_ROM(0x8086, 0x1001, "e1000-0x1001", "E1000-0x1001"),
34 PCI_ROM(0x8086, 0x1004, "e1000-0x1004", "E1000-0x1004"),
35 PCI_ROM(0x8086, 0x1008, "e1000-0x1008", "E1000-0x1008"),
36 PCI_ROM(0x8086, 0x1009, "e1000-0x1009", "E1000-0x1009"),
37 PCI_ROM(0x8086, 0x100C, "e1000-0x100C", "E1000-0x100C"),
38 PCI_ROM(0x8086, 0x100D, "e1000-0x100D", "E1000-0x100D"),
39 PCI_ROM(0x8086, 0x100E, "e1000-0x100E", "E1000-0x100E"),
40 PCI_ROM(0x8086, 0x100F, "e1000-0x100F", "E1000-0x100F"),
41 PCI_ROM(0x8086, 0x1010, "e1000-0x1010", "E1000-0x1010"),
42 PCI_ROM(0x8086, 0x1011, "e1000-0x1011", "E1000-0x1011"),
43 PCI_ROM(0x8086, 0x1012, "e1000-0x1012", "E1000-0x1012"),
44 PCI_ROM(0x8086, 0x1013, "e1000-0x1013", "E1000-0x1013"),
45 PCI_ROM(0x8086, 0x1014, "e1000-0x1014", "E1000-0x1014"),
46 PCI_ROM(0x8086, 0x1015, "e1000-0x1015", "E1000-0x1015"),
47 PCI_ROM(0x8086, 0x1016, "e1000-0x1016", "E1000-0x1016"),
48 PCI_ROM(0x8086, 0x1017, "e1000-0x1017", "E1000-0x1017"),
49 PCI_ROM(0x8086, 0x1018, "e1000-0x1018", "E1000-0x1018"),
50 PCI_ROM(0x8086, 0x1019, "e1000-0x1019", "E1000-0x1019"),
51 PCI_ROM(0x8086, 0x101A, "e1000-0x101A", "E1000-0x101A"),
52 PCI_ROM(0x8086, 0x101D, "e1000-0x101D", "E1000-0x101D"),
53 PCI_ROM(0x8086, 0x101E, "e1000-0x101E", "E1000-0x101E"),
54 PCI_ROM(0x8086, 0x1026, "e1000-0x1026", "E1000-0x1026"),
55 PCI_ROM(0x8086, 0x1027, "e1000-0x1027", "E1000-0x1027"),
56 PCI_ROM(0x8086, 0x1028, "e1000-0x1028", "E1000-0x1028"),
57 PCI_ROM(0x8086, 0x1049, "e1000-0x1049", "E1000-0x1049"),
58 PCI_ROM(0x8086, 0x104A, "e1000-0x104A", "E1000-0x104A"),
59 PCI_ROM(0x8086, 0x104B, "e1000-0x104B", "E1000-0x104B"),
60 PCI_ROM(0x8086, 0x104C, "e1000-0x104C", "E1000-0x104C"),
61 PCI_ROM(0x8086, 0x104D, "e1000-0x104D", "E1000-0x104D"),
62 PCI_ROM(0x8086, 0x105E, "e1000-0x105E", "E1000-0x105E"),
63 PCI_ROM(0x8086, 0x105F, "e1000-0x105F", "E1000-0x105F"),
64 PCI_ROM(0x8086, 0x1060, "e1000-0x1060", "E1000-0x1060"),
65 PCI_ROM(0x8086, 0x1075, "e1000-0x1075", "E1000-0x1075"),
66 PCI_ROM(0x8086, 0x1076, "e1000-0x1076", "E1000-0x1076"),
67 PCI_ROM(0x8086, 0x1077, "e1000-0x1077", "E1000-0x1077"),
68 PCI_ROM(0x8086, 0x1078, "e1000-0x1078", "E1000-0x1078"),
69 PCI_ROM(0x8086, 0x1079, "e1000-0x1079", "E1000-0x1079"),
70 PCI_ROM(0x8086, 0x107A, "e1000-0x107A", "E1000-0x107A"),
71 PCI_ROM(0x8086, 0x107B, "e1000-0x107B", "E1000-0x107B"),
72 PCI_ROM(0x8086, 0x107C, "e1000-0x107C", "E1000-0x107C"),
73 PCI_ROM(0x8086, 0x107D, "e1000-0x107D", "E1000-0x107D"),
74 PCI_ROM(0x8086, 0x107E, "e1000-0x107E", "E1000-0x107E"),
75 PCI_ROM(0x8086, 0x107F, "e1000-0x107F", "E1000-0x107F"),
76 PCI_ROM(0x8086, 0x108A, "e1000-0x108A", "E1000-0x108A"),
77 PCI_ROM(0x8086, 0x108B, "e1000-0x108B", "E1000-0x108B"),
78 PCI_ROM(0x8086, 0x108C, "e1000-0x108C", "E1000-0x108C"),
79 PCI_ROM(0x8086, 0x1096, "e1000-0x1096", "E1000-0x1096"),
80 PCI_ROM(0x8086, 0x1098, "e1000-0x1098", "E1000-0x1098"),
81 PCI_ROM(0x8086, 0x1099, "e1000-0x1099", "E1000-0x1099"),
82 PCI_ROM(0x8086, 0x109A, "e1000-0x109A", "E1000-0x109A"),
83 PCI_ROM(0x8086, 0x10A4, "e1000-0x10A4", "E1000-0x10A4"),
84 PCI_ROM(0x8086, 0x10A5, "e1000-0x10A5", "E1000-0x10A5"),
85 PCI_ROM(0x8086, 0x10B5, "e1000-0x10B5", "E1000-0x10B5"),
86 PCI_ROM(0x8086, 0x10B9, "e1000-0x10B9", "E1000-0x10B9"),
87 PCI_ROM(0x8086, 0x10BA, "e1000-0x10BA", "E1000-0x10BA"),
88 PCI_ROM(0x8086, 0x10BB, "e1000-0x10BB", "E1000-0x10BB"),
89 PCI_ROM(0x8086, 0x10BC, "e1000-0x10BC", "E1000-0x10BC"),
90 PCI_ROM(0x8086, 0x10C4, "e1000-0x10C4", "E1000-0x10C4"),
91 PCI_ROM(0x8086, 0x10C5, "e1000-0x10C5", "E1000-0x10C5"),
92 PCI_ROM(0x8086, 0x10D9, "e1000-0x10D9", "E1000-0x10D9"),
93 PCI_ROM(0x8086, 0x10DA, "e1000-0x10DA", "E1000-0x10DA"),
94 };
95
96 static void
97 e1000_init_manageability ( struct e1000_adapter *adapter )
98 {
99 DBG ( "e1000_init_manageability\n" );
100
101 if (adapter->en_mng_pt) {
102 uint32_t manc = E1000_READ_REG(&adapter->hw, MANC);
103
104 /* disable hardware interception of ARP */
105 manc &= ~(E1000_MANC_ARP_EN);
106
107 /* enable receiving management packets to the host */
108 /* this will probably generate destination unreachable messages
109 * from the host OS, but the packets will be handled on SMBUS */
110 if (adapter->hw.has_manc2h) {
111 uint32_t manc2h = E1000_READ_REG(&adapter->hw, MANC2H);
112
113 manc |= E1000_MANC_EN_MNG2HOST;
114 manc2h |= E1000_MNG2HOST_PORT_623;
115 manc2h |= E1000_MNG2HOST_PORT_664;
116 E1000_WRITE_REG(&adapter->hw, MANC2H, manc2h);
117 }
118
119 E1000_WRITE_REG(&adapter->hw, MANC, manc);
120 }
121 }
122
123 /**
124 * e1000_power_up_phy - restore link in case the phy was powered down
125 * @adapter: address of board private structure
126 *
127 * The phy may be powered down to save power and turn off link when the
128 * driver is unloaded and wake on lan is not enabled (among others)
129 * *** this routine MUST be followed by a call to e1000_reset ***
130 *
131 **/
132 static void
133 e1000_power_up_phy ( struct e1000_adapter *adapter )
134 {
135 DBG ( "e1000_power_up_phy\n" );
136
137 uint16_t mii_reg = 0;
138
139 /* Just clear the power down bit to wake the phy back up */
140 if (adapter->hw.media_type == e1000_media_type_copper) {
141 /* according to the manual, the phy will retain its
142 * settings across a power-down/up cycle */
143 e1000_read_phy_reg(&adapter->hw, PHY_CTRL, &mii_reg);
144 mii_reg &= ~MII_CR_POWER_DOWN;
145 e1000_write_phy_reg(&adapter->hw, PHY_CTRL, mii_reg);
146 }
147 }
148
149 static void
150 e1000_power_down_phy ( struct e1000_adapter *adapter )
151 {
152 DBG ( "e1000_power_down_phy\n" );
153
154 /* Power down the PHY so no link is implied when interface is down *
155 * The PHY cannot be powered down if any of the following is TRUE *
156 * (a) WoL is enabled
157 * (b) AMT is active
158 * (c) SoL/IDER session is active */
159 if (!adapter->wol && adapter->hw.mac_type >= e1000_82540 &&
160 adapter->hw.media_type == e1000_media_type_copper) {
161 uint16_t mii_reg = 0;
162
163 switch (adapter->hw.mac_type) {
164 case e1000_82540:
165 case e1000_82545:
166 case e1000_82545_rev_3:
167 case e1000_82546:
168 case e1000_82546_rev_3:
169 case e1000_82541:
170 case e1000_82541_rev_2:
171 case e1000_82547:
172 case e1000_82547_rev_2:
173 if (E1000_READ_REG(&adapter->hw, MANC) &
174 E1000_MANC_SMBUS_EN)
175 goto out;
176 break;
177 case e1000_82571:
178 case e1000_82572:
179 case e1000_82573:
180 case e1000_80003es2lan:
181 case e1000_ich8lan:
182 if (e1000_check_mng_mode(&adapter->hw) ||
183 e1000_check_phy_reset_block(&adapter->hw))
184 goto out;
185 break;
186 default:
187 goto out;
188 }
189 e1000_read_phy_reg(&adapter->hw, PHY_CTRL, &mii_reg);
190 mii_reg |= MII_CR_POWER_DOWN;
191 e1000_write_phy_reg(&adapter->hw, PHY_CTRL, mii_reg);
192 mdelay(1);
193 }
194 out:
195 return;
196 }
197
198 /**
199 * e1000_sw_init - Initialize general software structures (struct e1000_adapter)
200 * @adapter: board private structure to initialize
201 *
202 * e1000_sw_init initializes the Adapter private data structure.
203 * Fields are initialized based on PCI device information and
204 * OS network device settings (MTU size).
205 **/
206 static int
207 e1000_sw_init ( struct e1000_adapter *adapter )
208 {
209 struct e1000_hw *hw = &adapter->hw;
210 struct pci_device *pdev = adapter->pdev;
211
212 DBG ( "e1000_sw_init\n" );
213
214 /* PCI config space info */
215 hw->vendor_id = pdev->vendor;
216 hw->device_id = pdev->device;
217
218 pci_read_config_word(pdev, PCI_COMMAND, &hw->pci_cmd_word);
219
220 adapter->rx_buffer_len = 2048;
221
222 /* identify the MAC */
223
224 if ( e1000_set_mac_type ( hw ) ) {
225 DBG ( "Unknown MAC Type\n" );
226 return -EINVAL;
227 }
228
229 switch (hw->mac_type) {
230 default:
231 break;
232 case e1000_82541:
233 case e1000_82547:
234 case e1000_82541_rev_2:
235 case e1000_82547_rev_2:
236 hw->phy_init_script = 1;
237 break;
238 }
239
240 e1000_set_media_type(hw);
241
242 hw->wait_autoneg_complete = TRUE;
243 hw->tbi_compatibility_en = TRUE;
244 hw->adaptive_ifs = TRUE;
245
246 /* Copper options */
247
248 if (hw->media_type == e1000_media_type_copper) {
249 hw->mdix = AUTO_ALL_MODES;
250 hw->disable_polarity_correction = FALSE;
251 hw->master_slave = E1000_MASTER_SLAVE;
252 }
253
254 adapter->num_tx_queues = 1;
255 adapter->num_rx_queues = 1;
256
257 return E1000_SUCCESS;
258 }
259
260 /**
261 * e1000_setup_tx_resources - allocate Tx resources (Descriptors)
262 * @adapter: board private structure
263 * @txdr: tx descriptor ring (for a specific queue) to setup
264 *
265 * Return 0 on success, negative on failure
266 **/
267 static int
268 e1000_setup_tx_resources ( struct e1000_adapter *adapter )
269 {
270 int i;
271
272 DBG ( "e1000_setup_tx_resources\n" );
273
274 /* Allocate transmit descriptor ring memory.
275 It must not cross a 64K boundary because of hardware errata #23
276 so we use malloc_dma() requesting a 128 byte block that is
277 128 byte aligned. This should guarantee that the memory
278 allocated will not cross a 64K boundary, because 128 is an
279 even multiple of 65536 ( 65536 / 128 == 512 ), so all possible
280 allocations of 128 bytes on a 128 byte boundary will not
281 cross 64K bytes.
282 */
283
284 adapter->tx_desc_ring =
285 malloc_dma ( sizeof ( struct e1000_tx_desc ) * NUM_TX_DESC,
286 sizeof ( struct e1000_tx_desc ) * NUM_TX_DESC );
287
288 if ( ! adapter->tx_desc_ring ) {
289 return -ENOMEM;
290 }
291
292 memset ( adapter->tx_desc_ring, 0, sizeof ( struct e1000_tx_desc ) *
293 NUM_TX_DESC );
294
295 for ( i = 0; i < NUM_TX_DESC; i++ ) {
296 adapter->tx_desc[i] = (void *) adapter->tx_desc_ring +
297 ( i * sizeof ( struct e1000_tx_desc ) );
298 }
299
300 return 0;
301 }
302
303 static void
304 e1000_free_tx_resources ( struct e1000_adapter *adapter )
305 {
306 DBG ( "e1000_free_tx_resources\n" );
307
308 free_dma ( adapter->tx_desc_ring,
309 sizeof ( struct e1000_tx_desc ) * NUM_TX_DESC );
310 }
311
312 /**
313 * e1000_setup_rx_resources - allocate Rx resources (Descriptors)
314 * @adapter: board private structure
315 * @rxdr: rx descriptor ring (for a specific queue) to setup
316 *
317 * Returns 0 on success, negative on failure
318 **/
319 static int
320 e1000_setup_rx_resources ( struct e1000_adapter *adapter )
321 {
322 int i, j;
323
324 DBG ( "e1000_setup_rx_resources\n" );
325
326 /* Allocate receive descriptor ring memory.
327 It must not cross a 64K boundary because of hardware errata
328 */
329
330 adapter->rx_desc_ring =
331 malloc_dma ( sizeof ( struct e1000_rx_desc ) * NUM_RX_DESC,
332 sizeof ( struct e1000_rx_desc ) * NUM_RX_DESC );
333
334 if ( ! adapter->rx_desc_ring ) {
335 return -ENOMEM;
336 }
337
338 memset ( adapter->rx_desc_ring, 0, sizeof (struct e1000_rx_desc) * NUM_RX_DESC );
339
340 for ( i = 0; i < NUM_RX_DESC; i++ ) {
341
342 adapter->rx_iobuf[i] = alloc_iob ( E1000_RXBUFFER_2048 );
343
344 /* If unable to allocate all iobufs, free any that
345 * were successfully allocated, and return an error
346 */
347 if ( ! adapter->rx_iobuf[i] ) {
348 for ( j = 0; j < i; j++ ) {
349 free_iob ( adapter->rx_iobuf[j] );
350 }
351 return -ENOMEM;
352 }
353
354 adapter->rx_desc[i] = (void *) adapter->rx_desc_ring +
355 ( i * sizeof ( struct e1000_rx_desc ) );
356
357 adapter->rx_desc[i]->buffer_addr = virt_to_bus ( adapter->rx_iobuf[i]->data );
358 }
359 return 0;
360 }
361
362 static void
363 e1000_free_rx_resources ( struct e1000_adapter *adapter )
364 {
365 int i;
366
367 DBG ( "e1000_free_rx_resources\n" );
368
369 free_dma ( adapter->rx_desc_ring,
370 sizeof ( struct e1000_rx_desc ) * NUM_RX_DESC );
371
372 for ( i = 0; i < NUM_RX_DESC; i++ ) {
373 free_iob ( adapter->rx_iobuf[i] );
374 }
375 }
376
377 /**
378 * e1000_configure_tx - Configure 8254x Transmit Unit after Reset
379 * @adapter: board private structure
380 *
381 * Configure the Tx unit of the MAC after a reset.
382 **/
383 static void
384 e1000_configure_tx ( struct e1000_adapter *adapter )
385 {
386 struct e1000_hw *hw = &adapter->hw;
387 uint32_t tctl, tipg, tarc;
388 uint32_t ipgr1, ipgr2;
389
390 DBG ( "e1000_configure_tx\n" );
391
392 E1000_WRITE_REG ( hw, TDBAH, 0 );
393 E1000_WRITE_REG ( hw, TDBAL, virt_to_bus ( adapter->tx_base ) );
394 E1000_WRITE_REG ( hw, TDLEN, sizeof ( struct e1000_tx_desc ) *
395 NUM_TX_DESC );
396
397 /* Setup the HW Tx Head and Tail descriptor pointers */
398 E1000_WRITE_REG ( hw, TDH, 0 );
399 E1000_WRITE_REG ( hw, TDT, 0 );
400
401 adapter->tx_head = 0;
402 adapter->tx_tail = 0;
403 adapter->tx_fill_ctr = 0;
404
405 /* Set the default values for the Tx Inter Packet Gap timer */
406 if (adapter->hw.mac_type <= e1000_82547_rev_2 &&
407 (hw->media_type == e1000_media_type_fiber ||
408 hw->media_type == e1000_media_type_internal_serdes))
409 tipg = DEFAULT_82543_TIPG_IPGT_FIBER;
410 else
411 tipg = DEFAULT_82543_TIPG_IPGT_COPPER;
412
413 switch (hw->mac_type) {
414 case e1000_82542_rev2_0:
415 case e1000_82542_rev2_1:
416 tipg = DEFAULT_82542_TIPG_IPGT;
417 ipgr1 = DEFAULT_82542_TIPG_IPGR1;
418 ipgr2 = DEFAULT_82542_TIPG_IPGR2;
419 break;
420 case e1000_80003es2lan:
421 ipgr1 = DEFAULT_82543_TIPG_IPGR1;
422 ipgr2 = DEFAULT_80003ES2LAN_TIPG_IPGR2;
423 break;
424 default:
425 ipgr1 = DEFAULT_82543_TIPG_IPGR1;
426 ipgr2 = DEFAULT_82543_TIPG_IPGR2;
427 break;
428 }
429 tipg |= ipgr1 << E1000_TIPG_IPGR1_SHIFT;
430 tipg |= ipgr2 << E1000_TIPG_IPGR2_SHIFT;
431 E1000_WRITE_REG ( hw, TIPG, tipg );
432
433 /* Set the Tx Interrupt Delay register */
434
435 E1000_WRITE_REG (hw, TIDV, adapter->tx_int_delay);
436 if (hw->mac_type >= e1000_82540)
437 E1000_WRITE_REG(hw, TADV, adapter->tx_abs_int_delay);
438
439 /* Program the Transmit Control Register */
440
441 tctl = E1000_READ_REG(hw, TCTL);
442 tctl &= ~E1000_TCTL_CT;
443 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
444 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
445
446 if (hw->mac_type == e1000_82571 || hw->mac_type == e1000_82572) {
447 tarc = E1000_READ_REG(hw, TARC0);
448 /* set the speed mode bit, we'll clear it if we're not at
449 * gigabit link later */
450 tarc |= (1 << 21);
451 E1000_WRITE_REG(hw, TARC0, tarc);
452 } else if (hw->mac_type == e1000_80003es2lan) {
453 tarc = E1000_READ_REG(hw, TARC0);
454 tarc |= 1;
455 E1000_WRITE_REG(hw, TARC0, tarc);
456 tarc = E1000_READ_REG(hw, TARC1);
457 tarc |= 1;
458 E1000_WRITE_REG(hw, TARC1, tarc);
459 }
460
461 e1000_config_collision_dist(hw);
462
463 /* Setup Transmit Descriptor Settings for eop descriptor */
464 adapter->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_IFCS;
465
466 /* only set IDE if we are delaying interrupts using the timers */
467 if (adapter->tx_int_delay)
468 adapter->txd_cmd |= E1000_TXD_CMD_IDE;
469
470 if (hw->mac_type < e1000_82543)
471 adapter->txd_cmd |= E1000_TXD_CMD_RPS;
472 else
473 adapter->txd_cmd |= E1000_TXD_CMD_RS;
474
475 /* Cache if we're 82544 running in PCI-X because we'll
476 * need this to apply a workaround later in the send path. */
477 if (hw->mac_type == e1000_82544 &&
478 hw->bus_type == e1000_bus_type_pcix)
479 adapter->pcix_82544 = 1;
480
481 E1000_WRITE_REG ( hw, TCTL, tctl );
482 }
483
484 /**
485 * e1000_setup_rctl - configure the receive control registers
486 * @adapter: Board private structure
487 **/
488 static void
489 e1000_setup_rctl ( struct e1000_adapter *adapter )
490 {
491 uint32_t rctl;
492
493 DBG ( "e1000_setup_rctl\n" );
494
495 rctl = E1000_READ_REG ( &adapter->hw, RCTL );
496
497 rctl &= ~( 3 << E1000_RCTL_MO_SHIFT );
498
499 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM |
500 E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF |
501 ( adapter->hw.mc_filter_type << E1000_RCTL_MO_SHIFT );
502
503 if ( adapter->hw.tbi_compatibility_on == 1 )
504 rctl |= E1000_RCTL_SBP;
505 else
506 rctl &= ~E1000_RCTL_SBP;
507
508 rctl &= ~E1000_RCTL_LPE;
509
510 /* Setup buffer sizes */
511 rctl |= E1000_RCTL_SZ_2048;
512 rctl &= ~E1000_RCTL_BSEX;
513
514 E1000_WRITE_REG ( &adapter->hw, RCTL, rctl );
515 }
516
517 /**
518 * e1000_configure_rx - Configure 8254x Receive Unit after Reset
519 * @adapter: board private structure
520 *
521 * Configure the Rx unit of the MAC after a reset.
522 **/
523 static void
524 e1000_configure_rx ( struct e1000_adapter *adapter )
525 {
526 struct e1000_hw *hw = &adapter->hw;
527 uint32_t rctl, ctrl_ext;
528
529 DBG ( "e1000_configure_rx\n" );
530
531 /* disable receives while setting up the descriptors */
532 rctl = E1000_READ_REG(hw, RCTL);
533 E1000_WRITE_REG ( hw, RCTL, rctl & ~E1000_RCTL_EN );
534
535 /* set the Receive Delay Timer Register */
536 E1000_WRITE_REG( hw, RDTR, adapter->rx_int_delay );
537
538 if (hw->mac_type >= e1000_82540) {
539 E1000_WRITE_REG(hw, RADV, adapter->rx_abs_int_delay);
540 if (adapter->itr_setting != 0)
541 E1000_WRITE_REG(hw, ITR,
542 1000000000 / (adapter->itr * 256));
543 }
544
545 if (hw->mac_type >= e1000_82571) {
546 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
547 /* Reset delay timers after every interrupt */
548 ctrl_ext |= E1000_CTRL_EXT_INT_TIMER_CLR;
549 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
550 E1000_WRITE_FLUSH(hw);
551 }
552
553 /* Setup the HW Rx Head and Tail Descriptor Pointers and
554 * the Base and Length of the Rx Descriptor Ring */
555
556 adapter->rx_tail = 0;
557
558 E1000_WRITE_REG ( hw, RDBAH, 0 );
559 E1000_WRITE_REG ( hw, RDBAL, virt_to_bus ( adapter->rx_base ) );
560 E1000_WRITE_REG ( hw, RDLEN, sizeof ( struct e1000_tx_desc ) *
561 NUM_TX_DESC );
562
563 E1000_WRITE_REG ( hw, RDH, 0);
564 E1000_WRITE_REG ( hw, RDT, 0);
565
566 /* Enable Receives */
567
568 E1000_WRITE_REG ( hw, RCTL, rctl );
569 }
570
571 /**
572 * e1000_configure - configure the hardware for RX and TX
573 * @adapter = private board structure
574 **/
575 static void e1000_configure ( struct e1000_adapter *adapter )
576 {
577 DBG ( "e1000_configure\n" );
578
579 e1000_configure_tx ( adapter );
580
581 e1000_setup_rctl ( adapter );
582
583 e1000_configure_rx ( adapter );
584 }
585
586 /**
587 * e1000_reset - Put e1000 NIC in known initial state
588 *
589 * @v adapter e1000 private structure
590 **/
591 static void
592 e1000_reset ( struct e1000_adapter *adapter )
593 {
594 uint32_t pba = 0;
595 uint16_t fc_high_water_mark = E1000_FC_HIGH_DIFF;
596
597 DBG ( "e1000_reset\n" );
598
599 switch (adapter->hw.mac_type) {
600 case e1000_82542_rev2_0:
601 case e1000_82542_rev2_1:
602 case e1000_82543:
603 case e1000_82544:
604 case e1000_82540:
605 case e1000_82541:
606 case e1000_82541_rev_2:
607 pba = E1000_PBA_48K;
608 break;
609 case e1000_82545:
610 case e1000_82545_rev_3:
611 case e1000_82546:
612 case e1000_82546_rev_3:
613 pba = E1000_PBA_48K;
614 break;
615 case e1000_82547:
616 case e1000_82547_rev_2:
617 pba = E1000_PBA_30K;
618 break;
619 case e1000_82571:
620 case e1000_82572:
621 case e1000_80003es2lan:
622 pba = E1000_PBA_38K;
623 break;
624 case e1000_82573:
625 pba = E1000_PBA_20K;
626 break;
627 case e1000_ich8lan:
628 pba = E1000_PBA_8K;
629 case e1000_undefined:
630 case e1000_num_macs:
631 break;
632 }
633
634 E1000_WRITE_REG(&adapter->hw, PBA, pba);
635
636 /* flow control settings */
637 /* Set the FC high water mark to 90% of the FIFO size.
638 * Required to clear last 3 LSB */
639 fc_high_water_mark = ((pba * 9216)/10) & 0xFFF8;
640 /* We can't use 90% on small FIFOs because the remainder
641 * would be less than 1 full frame. In this case, we size
642 * it to allow at least a full frame above the high water
643 * mark. */
644 if (pba < E1000_PBA_16K)
645 fc_high_water_mark = (pba * 1024) - 1600;
646
647 adapter->hw.fc_high_water = fc_high_water_mark;
648 adapter->hw.fc_low_water = fc_high_water_mark - 8;
649 if (adapter->hw.mac_type == e1000_80003es2lan)
650 adapter->hw.fc_pause_time = 0xFFFF;
651 else
652 adapter->hw.fc_pause_time = E1000_FC_PAUSE_TIME;
653 adapter->hw.fc_send_xon = 1;
654 adapter->hw.fc = adapter->hw.original_fc;
655
656 /* Allow time for pending master requests to run */
657 e1000_reset_hw(&adapter->hw);
658 if (adapter->hw.mac_type >= e1000_82544)
659 E1000_WRITE_REG(&adapter->hw, WUC, 0);
660
661 if (e1000_init_hw(&adapter->hw))
662 DBG ( "Hardware Error\n" );
663
664 /* if (adapter->hwflags & HWFLAGS_PHY_PWR_BIT) { */
665 if (adapter->hw.mac_type >= e1000_82544 &&
666 adapter->hw.mac_type <= e1000_82547_rev_2 &&
667 adapter->hw.autoneg == 1 &&
668 adapter->hw.autoneg_advertised == ADVERTISE_1000_FULL) {
669 uint32_t ctrl = E1000_READ_REG(&adapter->hw, CTRL);
670 /* clear phy power management bit if we are in gig only mode,
671 * which if enabled will attempt negotiation to 100Mb, which
672 * can cause a loss of link at power off or driver unload */
673 ctrl &= ~E1000_CTRL_SWDPIN3;
674 E1000_WRITE_REG(&adapter->hw, CTRL, ctrl);
675 }
676
677 e1000_phy_get_info(&adapter->hw, &adapter->phy_info);
678
679 if (!adapter->smart_power_down &&
680 (adapter->hw.mac_type == e1000_82571 ||
681 adapter->hw.mac_type == e1000_82572)) {
682 uint16_t phy_data = 0;
683 /* speed up time to link by disabling smart power down, ignore
684 * the return value of this function because there is nothing
685 * different we would do if it failed */
686 e1000_read_phy_reg(&adapter->hw, IGP02E1000_PHY_POWER_MGMT,
687 &phy_data);
688 phy_data &= ~IGP02E1000_PM_SPD;
689 e1000_write_phy_reg(&adapter->hw, IGP02E1000_PHY_POWER_MGMT,
690 phy_data);
691 }
692
693 }
694
695 /** Functions that implement the gPXE driver API **/
696
697 /**
698 * e1000_close - Disables a network interface
699 *
700 * @v netdev network interface device structure
701 *
702 **/
703 static void
704 e1000_close ( struct net_device *netdev )
705 {
706 struct e1000_adapter *adapter = netdev_priv( netdev );
707
708 DBG ( "e1000_close\n" );
709
710 e1000_reset ( adapter );
711 e1000_power_down_phy ( adapter );
712
713 e1000_free_tx_resources ( adapter );
714 e1000_free_rx_resources ( adapter );
715 }
716
717 /**
718 * e1000_transmit - Transmit a packet
719 *
720 * @v netdev Network device
721 * @v iobuf I/O buffer
722 *
723 * @ret rc Return status code
724 */
725 static int
726 e1000_transmit ( struct net_device *netdev, struct io_buffer *iobuf )
727 {
728 struct e1000_adapter *adapter = netdev_priv( netdev );
729 struct e1000_hw *hw = &adapter->hw;
730
731 DBG ("e1000_transmit\n");
732
733 if ( adapter->tx_fill_ctr == NUM_TX_DESC ) {
734 DBG ("TX overflow\n");
735 return -ENOBUFS;
736 }
737
738 /* Save pointer to iobuf we have been given to transmit,
739 netdev_tx_complete() will need it later
740 */
741 adapter->tx_iobuf[adapter->tx_tail] = iobuf;
742
743 /* Add the packet to TX ring
744 */
745 adapter->tx_desc[adapter->tx_tail]->buffer_addr =
746 virt_to_bus ( iobuf->data );
747 adapter->tx_desc[adapter->tx_tail]->lower.data =
748 E1000_TXD_CMD_RPS | E1000_TXD_CMD_RS | E1000_TXD_CMD_EOP |
749 E1000_TXD_CMD_IFCS | iob_len ( iobuf );
750 adapter->tx_desc[adapter->tx_tail]->upper.data = 0;
751
752 DBG ( "TX fill: %ld tail: %ld addr: %#08lx len: %d\n", adapter->tx_fill_ctr,
753 adapter->tx_tail, virt_to_bus ( iobuf->data ), iob_len ( iobuf ) );
754
755 /* Point to next free descriptor */
756 adapter->tx_tail = ( adapter->tx_tail + 1 ) % NUM_TX_DESC;
757
758 adapter->tx_fill_ctr++;
759
760 /* Write new tail to NIC, making packet available for transmit
761 */
762 E1000_WRITE_REG ( hw, TDT, adapter->tx_tail ) ;
763
764 return 0;
765 }
766
767 /**
768 * e1000_poll - Poll for received packets
769 *
770 * @v netdev Network device
771 */
772 static void
773 e1000_poll ( struct net_device *netdev )
774 {
775 struct e1000_adapter *adapter = netdev_priv( netdev );
776 struct e1000_hw *hw = &adapter->hw;
777
778 uint32_t icr;
779 uint32_t tx_status;
780 uint32_t rx_status;
781 uint32_t rx_len;
782 uint32_t rx_err;
783 struct io_buffer *rx_iob;
784
785 uint32_t i;
786
787 #if 0
788 DBG ( "e1000_poll\n" );
789 #endif
790
791 /* Acknowledge interrupt. */
792 icr = E1000_READ_REG ( hw, ICR );
793
794 #if 0
795 DBG ( "e1000_poll: intr_status = %#08lx\n", icr );
796 #endif
797
798 /* Check status of transmitted packets
799 */
800 while ( ( i = adapter->tx_head ) != adapter->tx_tail ) {
801
802 //tx_status = adapter->tx_desc[i]->upper.fields.status;
803 tx_status = adapter->tx_desc[i]->upper.data;
804
805 DBG ( "e1000_poll: tx_status = %#08lx\n", tx_status );
806
807 /* if the packet at tx_head is not owned by hardware */
808 if ( ! ( tx_status & E1000_TXD_STAT_DD ) )
809 break;
810
811 DBG ( "got packet. tx_head: %ld tx_tail: %ld tx_status: %#08lx\n",
812 adapter->tx_head, adapter->tx_tail, tx_status );
813
814 if ( tx_status & ( E1000_TXD_STAT_EC | E1000_TXD_STAT_LC |
815 E1000_TXD_STAT_TU ) ) {
816 netdev_tx_complete_err ( netdev, adapter->tx_iobuf[i], -EINVAL );
817 DBG ( "Error transmitting packet, tx_status: %#08lx\n",
818 tx_status );
819 } else {
820 netdev_tx_complete ( netdev, adapter->tx_iobuf[i] );
821 DBG ( "Success transmitting packet, tx_status: %#08lx\n",
822 tx_status );
823 }
824
825 /* Decrement count of used descriptors, clear this descriptor
826 */
827 adapter->tx_fill_ctr--;
828 memset ( &adapter->tx_desc[i], 0, sizeof ( struct e1000_tx_desc ) );
829
830 adapter->tx_head = ( adapter->tx_head + 1 ) % NUM_TX_DESC;
831 }
832
833 /* Process received packets
834 */
835 while ( ( rx_status = adapter->rx_desc[adapter->rx_tail]->status ) & E1000_RXD_STAT_DD ) {
836
837 i = adapter->rx_tail;
838
839 rx_len = adapter->rx_desc[i]->length;
840
841 DBG ( "Received packet, rx_tail: %ld rx_status: %#08lx rx_len: %ld\n",
842 i, rx_status, rx_len );
843
844 rx_err = adapter->rx_desc[adapter->rx_tail]->errors;
845
846 if ( rx_err & E1000_RXD_ERR_FRAME_ERR_MASK ) {
847
848 netdev_rx_err ( netdev, NULL, -EINVAL );
849 DBG ( "e1000_poll: Corrupted packet received!"
850 " rx_err: %#08lx\n", rx_err );
851
852 } else {
853
854 /* If unable allocate space for this packet,
855 * try again next poll
856 */
857 rx_iob = alloc_iob ( rx_len );
858 if ( ! rx_iob )
859 break;
860
861 memcpy ( iob_put ( rx_iob, rx_len ),
862 adapter->rx_iobuf[i]->data, rx_len );
863
864 /* Add this packet to the receive queue.
865 */
866 netdev_rx ( netdev, rx_iob );
867 }
868
869 adapter->rx_tail = ( adapter->rx_tail + 1 ) % NUM_RX_DESC;
870 }
871 }
872
873 /**
874 * e1000_irq - Enable, Disable, or Force interrupts
875 *
876 * @v adapter e1000 adapter
877 * @v action requested interrupt action
878 **/
879 static void
880 e1000_irq ( struct net_device *netdev, int enable )
881 {
882 struct e1000_adapter *adapter = netdev_priv(netdev);
883
884 DBG ( "e1000_irq\n" );
885
886 switch ( enable ) {
887 case 0 :
888 E1000_WRITE_REG ( &adapter->hw, IMC, ~0 );
889 E1000_WRITE_FLUSH ( &adapter->hw );
890 break;
891 case 1 :
892 E1000_WRITE_REG ( &adapter->hw, IMS,
893 E1000_IMS_RXT0 | E1000_IMS_RXSEQ );
894 E1000_WRITE_FLUSH ( &adapter->hw );
895 break;
896 /* FIXME: Etherboot has a "FORCE" action, does gPXE? */
897 case 2 :
898 E1000_WRITE_REG ( &adapter->hw, ICS, E1000_ICS_RXT0 );
899 break;
900 }
901 }
902
903 static struct net_device_operations e1000_operations;
904
905 /**
906 * e1000_probe - Initial configuration of e1000 NIC
907 *
908 * @v pci PCI device
909 * @v id PCI IDs
910 *
911 * @ret rc Return status code
912 **/
913 static int
914 e1000_probe ( struct pci_device *pdev,
915 const struct pci_device_id *id __unused )
916 {
917 int i, err;
918 struct net_device *netdev;
919 struct e1000_adapter *adapter;
920 unsigned long mmio_start, mmio_len;
921 unsigned long flash_start, flash_len;
922
923 DBG ( "e1000_probe\n" );
924
925 err = -ENOMEM;
926
927 /* Allocate net device (also allocates memory for netdev->priv
928 and makes netdev-priv point to it
929 */
930 netdev = alloc_etherdev ( sizeof ( struct e1000_adapter ) );
931 if ( ! netdev )
932 goto err_alloc_etherdev;
933
934 pci_set_drvdata ( pdev, netdev );
935
936 adapter = netdev_priv ( netdev );
937 memset ( adapter, 0, ( sizeof ( struct e1000_adapter ) ) );
938
939 /* Enable PCI device associated with this NIC device */
940 adjust_pci_device ( pdev );
941
942 adapter->ioaddr = pdev->ioaddr;
943 adapter->irqno = pdev->irq;
944 adapter->netdev = netdev;
945 adapter->pdev = pdev;
946 adapter->hw.back = adapter;
947
948 mmio_start = pci_bar_start ( pdev, PCI_BASE_ADDRESS_0 );
949 mmio_len = pci_bar_size ( pdev, PCI_BASE_ADDRESS_0 );
950
951 err = -EIO;
952
953 adapter->hw.hw_addr = ioremap ( mmio_start, mmio_len );
954 if ( ! adapter->hw.hw_addr )
955 goto err_ioremap;
956
957 for ( i = BAR_1; i <= BAR_5; i++ ) {
958 if ( pci_bar_size ( pdev, i ) == 0 )
959 continue;
960 if ( pci_find_capability ( pdev, i ) & IORESOURCE_IO ) {
961 adapter->hw.io_base = pci_bar_start ( pdev, i );
962 break;
963 }
964 }
965
966 /* Associate e1000-specific network operations operations with
967 * generic network device layer
968 */
969 netdev_init ( netdev, &e1000_operations );
970
971 /* setup the private structure */
972 if ( ( err = e1000_sw_init ( adapter ) ) )
973 goto err_sw_init;
974
975 DBG ( "adapter->hw.mac_type: %#08x\n", adapter->hw.mac_type );
976
977 /* Flash BAR mapping must happen after e1000_sw_init
978 * because it depends on mac_type
979 */
980 if ( ( adapter->hw.mac_type == e1000_ich8lan ) && ( pdev->ioaddr ) ) {
981 flash_start = pci_bar_start ( pdev, 1 );
982 flash_len = pci_bar_size ( pdev, 1 );
983 adapter->hw.flash_address = ioremap ( flash_start, flash_len );
984 if ( ! adapter->hw.flash_address )
985 goto err_flashmap;
986 }
987
988 /* initialize eeprom parameters */
989 if ( e1000_init_eeprom_params ( &adapter->hw ) ) {
990 DBG ( "EEPROM initialization failed\n" );
991 goto err_eeprom;
992 }
993
994 /* before reading the EEPROM, reset the controller to
995 * put the device in a known good starting state
996 */
997 e1000_reset_hw ( &adapter->hw );
998
999 /* make sure the EEPROM is good */
1000 if ( e1000_validate_eeprom_checksum( &adapter->hw ) < 0 ) {
1001 DBG ( "The EEPROM Checksum Is Not Valid\n" );
1002 goto err_eeprom;
1003 }
1004
1005 /* copy the MAC address out of the EEPROM */
1006 if ( e1000_read_mac_addr ( &adapter->hw ) )
1007 DBG ( "EEPROM Read Error\n" );
1008
1009 memcpy ( netdev->ll_addr, adapter->hw.mac_addr, ETH_ALEN );
1010
1011 /* reset the hardware with the new settings */
1012 e1000_reset ( adapter );
1013
1014 if ( ( err = register_netdev ( netdev ) ) != 0)
1015 goto err_register;
1016
1017 /* No errors, return success */
1018 return 0;
1019
1020 /* Error return paths */
1021 err_register:
1022 err_eeprom:
1023 if ( ! e1000_check_phy_reset_block ( &adapter->hw ) )
1024 e1000_phy_hw_reset ( &adapter->hw );
1025 if ( adapter->hw.flash_address )
1026 iounmap ( adapter->hw.flash_address );
1027 err_flashmap:
1028 err_sw_init:
1029 iounmap ( adapter->hw.hw_addr );
1030 err_ioremap:
1031 netdev_put ( netdev );
1032 err_alloc_etherdev:
1033 return err;
1034 }
1035
1036 /**
1037 * e1000_remove - Device Removal Routine
1038 *
1039 * @v pdev PCI device information struct
1040 *
1041 **/
1042 static void
1043 e1000_remove ( struct pci_device *pdev )
1044 {
1045 struct net_device *netdev = pci_get_drvdata ( pdev );
1046 struct e1000_adapter *adapter = netdev_priv ( netdev );
1047
1048 DBG ( "e1000_remove\n" );
1049
1050 e1000_reset_hw ( &adapter->hw );
1051 unregister_netdev ( netdev );
1052 netdev_put ( netdev );
1053 }
1054
1055 /**
1056 * e1000_open - Called when a network interface is made active
1057 *
1058 * @v netdev network interface device structure
1059 * @ret rc Return status code, 0 on success, negative value on failure
1060 *
1061 **/
1062 static int
1063 e1000_open ( struct net_device *netdev )
1064 {
1065 struct e1000_adapter *adapter = netdev_priv(netdev);
1066 int err;
1067
1068 DBG ( "e1000_open\n" );
1069
1070 /* allocate transmit descriptors */
1071 err = e1000_setup_tx_resources ( adapter );
1072 if (err)
1073 goto err_setup_tx;
1074
1075 /* allocate receive descriptors */
1076 err = e1000_setup_rx_resources ( adapter );
1077 if (err)
1078 goto err_setup_rx;
1079
1080 e1000_power_up_phy ( adapter );
1081
1082 /* disable firmware control */
1083 e1000_init_manageability ( adapter );
1084
1085 e1000_configure ( adapter );
1086
1087 return E1000_SUCCESS;
1088
1089 err_setup_rx:
1090 e1000_free_tx_resources ( adapter );
1091 err_setup_tx:
1092 e1000_reset ( adapter );
1093
1094 return err;
1095 }
1096
1097 struct pci_driver e1000_driver __pci_driver = {
1098 .ids = e1000_nics,
1099 .id_count = (sizeof (e1000_nics) / sizeof (e1000_nics[0])),
1100 .probe = e1000_probe,
1101 .remove = e1000_remove,
1102 };
1103
1104 /** e1000 net device operations */
1105 static struct net_device_operations e1000_operations = {
1106 .open = e1000_open,
1107 .close = e1000_close,
1108 .transmit = e1000_transmit,
1109 .poll = e1000_poll,
1110 .irq = e1000_irq,
1111 };
1112
1113 int32_t
1114 e1000_read_pcie_cap_reg(struct e1000_hw *hw, uint32_t reg, uint16_t *value)
1115 {
1116 struct e1000_adapter *adapter = hw->back;
1117 uint16_t cap_offset;
1118
1119 #define PCI_CAP_ID_EXP 0x10 /* PCI Express */
1120 cap_offset = pci_find_capability(adapter->pdev, PCI_CAP_ID_EXP);
1121 if (!cap_offset)
1122 return -E1000_ERR_CONFIG;
1123
1124 pci_read_config_word(adapter->pdev, cap_offset + reg, value);
1125
1126 return E1000_SUCCESS;
1127 }
1128
1129 void
1130 e1000_pci_clear_mwi ( struct e1000_hw *hw __unused )
1131 {
1132 }
1133
1134 void
1135 e1000_pci_set_mwi ( struct e1000_hw *hw __unused )
1136 {
1137 }
1138
1139 void
1140 e1000_read_pci_cfg(struct e1000_hw *hw, uint32_t reg, uint16_t *value)
1141 {
1142 struct e1000_adapter *adapter = hw->back;
1143
1144 pci_read_config_word(adapter->pdev, reg, value);
1145 }
1146
1147 void
1148 e1000_write_pci_cfg(struct e1000_hw *hw, uint32_t reg, uint16_t *value)
1149 {
1150 struct e1000_adapter *adapter = hw->back;
1151
1152 pci_write_config_word(adapter->pdev, reg, *value);
1153 }
1154
1155 void
1156 e1000_io_write ( struct e1000_hw *hw __unused, unsigned long port, uint32_t value )
1157 {
1158 outl ( value, port );
1159 }
1160
1161 /*
1162 * Local variables:
1163 * c-basic-offset: 8
1164 * c-indent-level: 8
1165 * tab-width: 8
1166 * End:
1167 */
gPXE - free pxe roms