src/drivers/net/eepro.c

   1 #ifdef ALLMULTI
   2 #error multicast support is not yet implemented
   3 #endif
   4 /**************************************************************************
   5 Etherboot -  BOOTP/TFTP Bootstrap Program
   6 Intel EEPRO/10 NIC driver for Etherboot
   7 Adapted from Linux eepro.c from kernel 2.2.17
   8
   9 This board accepts a 32 pin EEPROM (29C256), however a test with a
  10 27C010 shows that this EPROM also works in the socket, but it's not clear
  11 how repeatably. The two top address pins appear to be held low, thus
  12 the bottom 32kB of the 27C010 is visible in the CPU's address space.
  13 To be sure you could put 4 copies of the code in the 27C010, then
  14 it doesn't matter whether the extra lines are held low or high, just
  15 hopefully not floating as CMOS chips don't like floating inputs.
  16
  17 Be careful with seating the EPROM as the socket on my board actually
  18 has 34 pins, the top row of 2 are not used.
  19 ***************************************************************************/
  20
  21 /*
  22
  23  timlegge       2005-05-18      remove the relocation changes cards that
  24                                 write directly to the hardware don't need it
  25 */
  26
  27 /*
  28  * This program is free software; you can redistribute it and/or
  29  * modify it under the terms of the GNU General Public License as
  30  * published by the Free Software Foundation; either version 2, or (at
  31  * your option) any later version.
  32  */
  33
  34 #include "etherboot.h"
  35 #include <errno.h>
  36 #include "nic.h"
  37 #include <gpxe/isa.h>
  38 #include "timer.h"
  39 #include <gpxe/ethernet.h>
  40
  41 /* Different 82595 chips */
  42 #define LAN595          0
  43 #define LAN595TX        1
  44 #define LAN595FX        2
  45 #define LAN595FX_10ISA  3
  46
  47 #define SLOW_DOWN       inb(0x80);
  48
  49 /* The station (ethernet) address prefix, used for IDing the board. */
  50 #define SA_ADDR0 0x00   /* Etherexpress Pro/10 */
  51 #define SA_ADDR1 0xaa
  52 #define SA_ADDR2 0x00
  53
  54 #define GetBit(x,y) ((x & (1<<y))>>y)
  55
  56 /* EEPROM Word 0: */
  57 #define ee_PnP       0  /* Plug 'n Play enable bit */
  58 #define ee_Word1     1  /* Word 1? */
  59 #define ee_BusWidth  2  /* 8/16 bit */
  60 #define ee_FlashAddr 3  /* Flash Address */
  61 #define ee_FlashMask 0x7   /* Mask */
  62 #define ee_AutoIO    6  /* */
  63 #define ee_reserved0 7  /* =0! */
  64 #define ee_Flash     8  /* Flash there? */
  65 #define ee_AutoNeg   9  /* Auto Negotiation enabled? */
  66 #define ee_IO0       10 /* IO Address LSB */
  67 #define ee_IO0Mask   0x /*...*/
  68 #define ee_IO1       15 /* IO MSB */
  69
  70 /* EEPROM Word 1: */
  71 #define ee_IntSel    0   /* Interrupt */
  72 #define ee_IntMask   0x7
  73 #define ee_LI        3   /* Link Integrity 0= enabled */
  74 #define ee_PC        4   /* Polarity Correction 0= enabled */
  75 #define ee_TPE_AUI   5   /* PortSelection 1=TPE */
  76 #define ee_Jabber    6   /* Jabber prevention 0= enabled */
  77 #define ee_AutoPort  7   /* Auto Port Selection 1= Disabled */
  78 #define ee_SMOUT     8   /* SMout Pin Control 0= Input */
  79 #define ee_PROM      9   /* Flash EPROM / PROM 0=Flash */
  80 #define ee_reserved1 10  /* .. 12 =0! */
  81 #define ee_AltReady  13  /* Alternate Ready, 0=normal */
  82 #define ee_reserved2 14  /* =0! */
  83 #define ee_Duplex    15
  84
  85 /* Word2,3,4: */
  86 #define ee_IA5       0 /*bit start for individual Addr Byte 5 */
  87 #define ee_IA4       8 /*bit start for individual Addr Byte 5 */
  88 #define ee_IA3       0 /*bit start for individual Addr Byte 5 */
  89 #define ee_IA2       8 /*bit start for individual Addr Byte 5 */
  90 #define ee_IA1       0 /*bit start for individual Addr Byte 5 */
  91 #define ee_IA0       8 /*bit start for individual Addr Byte 5 */
  92
  93 /* Word 5: */
  94 #define ee_BNC_TPE   0 /* 0=TPE */
  95 #define ee_BootType  1 /* 00=None, 01=IPX, 10=ODI, 11=NDIS */
  96 #define ee_BootTypeMask 0x3
  97 #define ee_NumConn   3  /* Number of Connections 0= One or Two */
  98 #define ee_FlashSock 4  /* Presence of Flash Socket 0= Present */
  99 #define ee_PortTPE   5
 100 #define ee_PortBNC   6
 101 #define ee_PortAUI   7
 102 #define ee_PowerMgt  10 /* 0= disabled */
 103 #define ee_CP        13 /* Concurrent Processing */
 104 #define ee_CPMask    0x7
 105
 106 /* Word 6: */
 107 #define ee_Stepping  0 /* Stepping info */
 108 #define ee_StepMask  0x0F
 109 #define ee_BoardID   4 /* Manucaturer Board ID, reserved */
 110 #define ee_BoardMask 0x0FFF
 111
 112 /* Word 7: */
 113 #define ee_INT_TO_IRQ 0 /* int to IRQ Mapping  = 0x1EB8 for Pro/10+ */
 114 #define ee_FX_INT2IRQ 0x1EB8 /* the _only_ mapping allowed for FX chips */
 115
 116 /*..*/
 117 #define ee_SIZE 0x40 /* total EEprom Size */
 118 #define ee_Checksum 0xBABA /* initial and final value for adding checksum */
 119
 120
 121 /* Card identification via EEprom:   */
 122 #define ee_addr_vendor 0x10  /* Word offset for EISA Vendor ID */
 123 #define ee_addr_id 0x11      /* Word offset for Card ID */
 124 #define ee_addr_SN 0x12      /* Serial Number */
 125 #define ee_addr_CRC_8 0x14   /* CRC over last thee Bytes */
 126
 127
 128 #define ee_vendor_intel0 0x25  /* Vendor ID Intel */
 129 #define ee_vendor_intel1 0xD4
 130 #define ee_id_eepro10p0 0x10   /* ID for eepro/10+ */
 131 #define ee_id_eepro10p1 0x31
 132
 133 /* now this section could be used by both boards: the oldies and the ee10:
 134  * ee10 uses tx buffer before of rx buffer and the oldies the inverse.
 135  * (aris)
 136  */
 137 #define RAM_SIZE        0x8000
 138
 139 #define RCV_HEADER      8
 140 #define RCV_DEFAULT_RAM 0x6000
 141 #define RCV_RAM         rcv_ram
 142
 143 static unsigned rcv_ram = RCV_DEFAULT_RAM;
 144
 145 #define XMT_HEADER      8
 146 #define XMT_RAM         (RAM_SIZE - RCV_RAM)
 147
 148 #define XMT_START       ((rcv_start + RCV_RAM) % RAM_SIZE)
 149
 150 #define RCV_LOWER_LIMIT (rcv_start >> 8)
 151 #define RCV_UPPER_LIMIT (((rcv_start + RCV_RAM) - 2) >> 8)
 152 #define XMT_LOWER_LIMIT (XMT_START >> 8)
 153 #define XMT_UPPER_LIMIT (((XMT_START + XMT_RAM) - 2) >> 8)
 154
 155 #define RCV_START_PRO   0x00
 156 #define RCV_START_10    XMT_RAM
 157                                         /* by default the old driver */
 158 static unsigned rcv_start = RCV_START_PRO;
 159
 160 #define RCV_DONE        0x0008
 161 #define RX_OK           0x2000
 162 #define RX_ERROR        0x0d81
 163
 164 #define TX_DONE_BIT     0x0080
 165 #define CHAIN_BIT       0x8000
 166 #define XMT_STATUS      0x02
 167 #define XMT_CHAIN       0x04
 168 #define XMT_COUNT       0x06
 169
 170 #define BANK0_SELECT    0x00
 171 #define BANK1_SELECT    0x40
 172 #define BANK2_SELECT    0x80
 173
 174 /* Bank 0 registers */
 175 #define COMMAND_REG     0x00    /* Register 0 */
 176 #define MC_SETUP        0x03
 177 #define XMT_CMD         0x04
 178 #define DIAGNOSE_CMD    0x07
 179 #define RCV_ENABLE_CMD  0x08
 180 #define RCV_DISABLE_CMD 0x0a
 181 #define STOP_RCV_CMD    0x0b
 182 #define RESET_CMD       0x0e
 183 #define POWER_DOWN_CMD  0x18
 184 #define RESUME_XMT_CMD  0x1c
 185 #define SEL_RESET_CMD   0x1e
 186 #define STATUS_REG      0x01    /* Register 1 */
 187 #define RX_INT          0x02
 188 #define TX_INT          0x04
 189 #define EXEC_STATUS     0x30
 190 #define ID_REG          0x02    /* Register 2   */
 191 #define R_ROBIN_BITS    0xc0    /* round robin counter */
 192 #define ID_REG_MASK     0x2c
 193 #define ID_REG_SIG      0x24
 194 #define AUTO_ENABLE     0x10
 195 #define INT_MASK_REG    0x03    /* Register 3   */
 196 #define RX_STOP_MASK    0x01
 197 #define RX_MASK         0x02
 198 #define TX_MASK         0x04
 199 #define EXEC_MASK       0x08
 200 #define ALL_MASK        0x0f
 201 #define IO_32_BIT       0x10
 202 #define RCV_BAR         0x04    /* The following are word (16-bit) registers */
 203 #define RCV_STOP        0x06
 204
 205 #define XMT_BAR_PRO     0x0a
 206 #define XMT_BAR_10      0x0b
 207 static unsigned xmt_bar = XMT_BAR_PRO;
 208
 209 #define HOST_ADDRESS_REG        0x0c
 210 #define IO_PORT         0x0e
 211 #define IO_PORT_32_BIT  0x0c
 212
 213 /* Bank 1 registers */
 214 #define REG1    0x01
 215 #define WORD_WIDTH      0x02
 216 #define INT_ENABLE      0x80
 217 #define INT_NO_REG      0x02
 218 #define RCV_LOWER_LIMIT_REG     0x08
 219 #define RCV_UPPER_LIMIT_REG     0x09
 220
 221 #define XMT_LOWER_LIMIT_REG_PRO 0x0a
 222 #define XMT_UPPER_LIMIT_REG_PRO 0x0b
 223 #define XMT_LOWER_LIMIT_REG_10  0x0b
 224 #define XMT_UPPER_LIMIT_REG_10  0x0a
 225 static unsigned xmt_lower_limit_reg = XMT_LOWER_LIMIT_REG_PRO;
 226 static unsigned xmt_upper_limit_reg = XMT_UPPER_LIMIT_REG_PRO;
 227
 228 /* Bank 2 registers */
 229 #define XMT_Chain_Int   0x20    /* Interrupt at the end of the transmit chain */
 230 #define XMT_Chain_ErrStop       0x40 /* Interrupt at the end of the chain even if there are errors */
 231 #define RCV_Discard_BadFrame    0x80 /* Throw bad frames away, and continue to receive others */
 232 #define REG2            0x02
 233 #define PRMSC_Mode      0x01
 234 #define Multi_IA        0x20
 235 #define REG3            0x03
 236 #define TPE_BIT         0x04
 237 #define BNC_BIT         0x20
 238 #define REG13           0x0d
 239 #define FDX             0x00
 240 #define A_N_ENABLE      0x02
 241
 242 #define I_ADD_REG0      0x04
 243 #define I_ADD_REG1      0x05
 244 #define I_ADD_REG2      0x06
 245 #define I_ADD_REG3      0x07
 246 #define I_ADD_REG4      0x08
 247 #define I_ADD_REG5      0x09
 248
 249 #define EEPROM_REG_PRO  0x0a
 250 #define EEPROM_REG_10   0x0b
 251 static unsigned eeprom_reg = EEPROM_REG_PRO;
 252
 253 #define EESK 0x01
 254 #define EECS 0x02
 255 #define EEDI 0x04
 256 #define EEDO 0x08
 257
 258 /* The horrible routine to read a word from the serial EEPROM. */
 259 /* IMPORTANT - the 82595 will be set to Bank 0 after the eeprom is read */
 260
 261 /* The delay between EEPROM clock transitions. */
 262 #define eeprom_delay() { udelay(40); }
 263 #define EE_READ_CMD (6 << 6)
 264
 265 /* do a full reset; data sheet asks for 250us delay */
 266 #define eepro_full_reset(ioaddr)        outb(RESET_CMD, ioaddr); udelay(255);
 267
 268 /* do a nice reset */
 269 #define eepro_sel_reset(ioaddr) \
 270   do {  \
 271     outb ( SEL_RESET_CMD, ioaddr ); \
 272     (void) SLOW_DOWN; \
 273     (void) SLOW_DOWN; \
 274   } while (0)
 275
 276 /* clear all interrupts */
 277 #define eepro_clear_int(ioaddr) outb(ALL_MASK, ioaddr + STATUS_REG)
 278
 279 /* enable rx */
 280 #define eepro_en_rx(ioaddr)     outb(RCV_ENABLE_CMD, ioaddr)
 281
 282 /* disable rx */
 283 #define eepro_dis_rx(ioaddr)    outb(RCV_DISABLE_CMD, ioaddr)
 284
 285 /* switch bank */
 286 #define eepro_sw2bank0(ioaddr) outb(BANK0_SELECT, ioaddr)
 287 #define eepro_sw2bank1(ioaddr) outb(BANK1_SELECT, ioaddr)
 288 #define eepro_sw2bank2(ioaddr) outb(BANK2_SELECT, ioaddr)
 289
 290 static unsigned int     rx_start, tx_start;
 291 static int              tx_last;
 292 static unsigned int     tx_end;
 293 static int              eepro = 0;
 294 static unsigned int     mem_start, mem_end = RCV_DEFAULT_RAM / 1024;
 295
 296 /**************************************************************************
 297 RESET - Reset adapter
 298 ***************************************************************************/
 299 static void eepro_reset(struct nic *nic)
 300 {
 301         int             temp_reg, i;
 302
 303         /* put the card in its initial state */
 304         eepro_sw2bank2(nic->ioaddr);    /* be careful, bank2 now */
 305         temp_reg = inb(nic->ioaddr + eeprom_reg);
 306         DBG("Stepping %d\n", temp_reg >> 5);
 307         if (temp_reg & 0x10)    /* check the TurnOff Enable bit */
 308                 outb(temp_reg & 0xEF, nic->ioaddr + eeprom_reg);
 309         for (i = 0; i < ETH_ALEN; i++)  /* fill the MAC address */
 310                 outb(nic->node_addr[i], nic->ioaddr + I_ADD_REG0 + i);
 311         temp_reg = inb(nic->ioaddr + REG1);
 312         /* setup Transmit Chaining and discard bad RCV frames */
 313         outb(temp_reg | XMT_Chain_Int | XMT_Chain_ErrStop
 314                 | RCV_Discard_BadFrame, nic->ioaddr + REG1);
 315         temp_reg = inb(nic->ioaddr + REG2);             /* match broadcast */
 316         outb(temp_reg | 0x14, nic->ioaddr + REG2);
 317         temp_reg = inb(nic->ioaddr + REG3);
 318         outb(temp_reg & 0x3F, nic->ioaddr + REG3);      /* clear test mode */
 319         /* set the receiving mode */
 320         eepro_sw2bank1(nic->ioaddr);    /* be careful, bank1 now */
 321         /* initialise the RCV and XMT upper and lower limits */
 322         outb(RCV_LOWER_LIMIT, nic->ioaddr + RCV_LOWER_LIMIT_REG);
 323         outb(RCV_UPPER_LIMIT, nic->ioaddr + RCV_UPPER_LIMIT_REG);
 324         outb(XMT_LOWER_LIMIT, nic->ioaddr + xmt_lower_limit_reg);
 325         outb(XMT_UPPER_LIMIT, nic->ioaddr + xmt_upper_limit_reg);
 326         eepro_sw2bank0(nic->ioaddr);    /* Switch back to bank 0 */
 327         eepro_clear_int(nic->ioaddr);
 328         /* Initialise RCV */
 329         outw(rx_start = (RCV_LOWER_LIMIT << 8), nic->ioaddr + RCV_BAR);
 330         outw(((RCV_UPPER_LIMIT << 8) | 0xFE), nic->ioaddr + RCV_STOP);
 331         /* Make sure 1st poll won't find a valid packet header */
 332         outw((RCV_LOWER_LIMIT << 8), nic->ioaddr + HOST_ADDRESS_REG);
 333         outw(0,                      nic->ioaddr + IO_PORT);
 334         /* Intialise XMT */
 335         outw((XMT_LOWER_LIMIT << 8), nic->ioaddr + xmt_bar);
 336         eepro_sel_reset(nic->ioaddr);
 337         tx_start = tx_end = (unsigned int) (XMT_LOWER_LIMIT << 8);
 338         tx_last = 0;
 339         eepro_en_rx(nic->ioaddr);
 340 }
 341
 342 /**************************************************************************
 343 POLL - Wait for a frame
 344 ***************************************************************************/
 345 static int eepro_poll(struct nic *nic, int retrieve)
 346 {
 347         unsigned int    rcv_car = rx_start;
 348         unsigned int    rcv_event, rcv_status, rcv_next_frame, rcv_size;
 349
 350         /* return true if there's an ethernet packet ready to read */
 351         /* nic->packet should contain data on return */
 352         /* nic->packetlen should contain length of data */
 353 #if     0
 354         if ((inb(nic->ioaddr + STATUS_REG) & 0x40) == 0)
 355                 return (0);
 356         outb(0x40, nic->ioaddr + STATUS_REG);
 357 #endif
 358         outw(rcv_car, nic->ioaddr + HOST_ADDRESS_REG);
 359         rcv_event = inw(nic->ioaddr + IO_PORT);
 360         if (rcv_event != RCV_DONE)
 361                 return (0);
 362
 363         /* FIXME: I'm guessing this might not work with this card, since
 364            it looks like once a rcv_event is started it must be completed.
 365            maybe there's another way. */
 366         if ( ! retrieve ) return 1;
 367
 368         rcv_status = inw(nic->ioaddr + IO_PORT);
 369         rcv_next_frame = inw(nic->ioaddr + IO_PORT);
 370         rcv_size = inw(nic->ioaddr + IO_PORT);
 371 #if     0
 372         printf("%hX %hX %d %hhX\n", rcv_status, rcv_next_frame, rcv_size,
 373                 inb(nic->ioaddr + STATUS_REG));
 374 #endif
 375         if ((rcv_status & (RX_OK|RX_ERROR)) != RX_OK) {
 376                 printf("Receive error %hX\n", rcv_status);
 377                 return (0);
 378         }
 379         rcv_size &= 0x3FFF;
 380         insw(nic->ioaddr + IO_PORT, nic->packet, ((rcv_size + 3) >> 1));
 381 #if     0
 382 {
 383         int i;
 384         for (i = 0; i < 48; i++) {
 385                 printf("%hhX", nic->packet[i]);
 386                 putchar(i % 16 == 15 ? '\n' : ' ');
 387         }
 388 }
 389 #endif
 390         nic->packetlen = rcv_size;
 391         rcv_car  = (rx_start + RCV_HEADER + rcv_size);
 392         rx_start = rcv_next_frame;
 393 /*
 394         hex_dump(rcv_car, nic->packetlen);
 395 */
 396
 397         if (rcv_car == 0)
 398                 rcv_car = ((RCV_UPPER_LIMIT << 8) | 0xff);
 399         outw(rcv_car - 1, nic->ioaddr + RCV_STOP);
 400         return (1);
 401 }
 402
 403 /**************************************************************************
 404 TRANSMIT - Transmit a frame
 405 ***************************************************************************/
 406 static void eepro_transmit(
 407         struct nic *nic,
 408         const char *d,                  /* Destination */
 409         unsigned int t,                 /* Type */
 410         unsigned int s,                 /* size */
 411         const char *p)                  /* Packet */
 412 {
 413         unsigned int    status, tx_available, last, end, length;
 414         unsigned short  type;
 415         int             boguscount = 20;
 416
 417         length = s + ETH_HLEN;
 418         if (tx_end > tx_start)
 419                 tx_available = XMT_RAM - (tx_end - tx_start);
 420         else if (tx_end < tx_start)
 421                 tx_available = tx_start - tx_end;
 422         else
 423                 tx_available = XMT_RAM;
 424         last = tx_end;
 425         end = last + (((length + 3) >> 1) << 1) + XMT_HEADER;
 426         if (end >= (XMT_UPPER_LIMIT << 8)) {
 427                 last = (XMT_LOWER_LIMIT << 8);
 428                 end = last + (((length + 3) >> 1) << 1) + XMT_HEADER;
 429         }
 430         outw(last, nic->ioaddr + HOST_ADDRESS_REG);
 431         outw(XMT_CMD, nic->ioaddr + IO_PORT);
 432         outw(0, nic->ioaddr + IO_PORT);
 433         outw(end, nic->ioaddr + IO_PORT);
 434         outw(length, nic->ioaddr + IO_PORT);
 435         outsw(nic->ioaddr + IO_PORT, d, ETH_ALEN / 2);
 436         outsw(nic->ioaddr + IO_PORT, nic->node_addr, ETH_ALEN / 2);
 437         type = htons(t);
 438         outsw(nic->ioaddr + IO_PORT, &type, sizeof(type) / 2);
 439         outsw(nic->ioaddr + IO_PORT, p, (s + 3) >> 1);
 440         /* A dummy read to flush the DRAM write pipeline */
 441         status = inw(nic->ioaddr + IO_PORT);
 442         outw(last, nic->ioaddr + xmt_bar);
 443         outb(XMT_CMD, nic->ioaddr);
 444         tx_start = last;
 445         tx_last = last;
 446         tx_end = end;
 447 #if     0
 448         printf("%d %d\n", tx_start, tx_end);
 449 #endif
 450         while (boguscount > 0) {
 451                 if (((status = inw(nic->ioaddr + IO_PORT)) & TX_DONE_BIT) == 0) {
 452                         udelay(40);
 453                         boguscount--;
 454                         continue;
 455                 }
 456                 if ((status & 0x2000) == 0) {
 457                         DBG("Transmit status %hX\n", status);
 458                 }
 459         }
 460 }
 461
 462 /**************************************************************************
 463 DISABLE - Turn off ethernet interface
 464 ***************************************************************************/
 465 static void eepro_disable ( struct nic *nic, struct isa_device *isa __unused ) {
 466         eepro_sw2bank0(nic->ioaddr);    /* Switch to bank 0 */
 467         /* Flush the Tx and disable Rx */
 468         outb(STOP_RCV_CMD, nic->ioaddr);
 469         tx_start = tx_end = (XMT_LOWER_LIMIT << 8);
 470         tx_last = 0;
 471         /* Reset the 82595 */
 472         eepro_full_reset(nic->ioaddr);
 473 }
 474
 475 /**************************************************************************
 476 DISABLE - Enable, Disable, or Force interrupts
 477 ***************************************************************************/
 478 static void eepro_irq(struct nic *nic __unused, irq_action_t action __unused)
 479 {
 480   switch ( action ) {
 481   case DISABLE :
 482     break;
 483   case ENABLE :
 484     break;
 485   case FORCE :
 486     break;
 487   }
 488 }
 489
 490 static int read_eeprom(uint16_t ioaddr, int location)
 491 {
 492         int             i;
 493         unsigned short  retval = 0;
 494         int             ee_addr = ioaddr + eeprom_reg;
 495         int             read_cmd = location | EE_READ_CMD;
 496         int             ctrl_val = EECS;
 497
 498         if (eepro == LAN595FX_10ISA) {
 499                 eepro_sw2bank1(ioaddr);
 500                 outb(0x00, ioaddr + STATUS_REG);
 501         }
 502         eepro_sw2bank2(ioaddr);
 503         outb(ctrl_val, ee_addr);
 504         /* shift the read command bits out */
 505         for (i = 8; i >= 0; i--) {
 506                 short outval = (read_cmd & (1 << i)) ? ctrl_val | EEDI : ctrl_val;
 507                 outb(outval, ee_addr);
 508                 outb(outval | EESK, ee_addr);   /* EEPROM clock tick */
 509                 eeprom_delay();
 510                 outb(outval, ee_addr);          /* finish EEPROM clock tick */
 511                 eeprom_delay();
 512         }
 513         outb(ctrl_val, ee_addr);
 514         for (i = 16; i > 0; i--) {
 515                 outb(ctrl_val | EESK, ee_addr);
 516                 eeprom_delay();
 517                 retval = (retval << 1) | ((inb(ee_addr) & EEDO) ? 1 : 0);
 518                 outb(ctrl_val, ee_addr);
 519                 eeprom_delay();
 520         }
 521         /* terminate the EEPROM access */
 522         ctrl_val &= ~EECS;
 523         outb(ctrl_val | EESK, ee_addr);
 524         eeprom_delay();
 525         outb(ctrl_val, ee_addr);
 526         eeprom_delay();
 527         eepro_sw2bank0(ioaddr);
 528         return (retval);
 529 }
 530
 531 static int eepro_probe1 ( isa_probe_addr_t ioaddr ) {
 532         int             id, counter;
 533
 534         id = inb(ioaddr + ID_REG);
 535         if ((id & ID_REG_MASK) != ID_REG_SIG)
 536                 return (0);
 537         counter = id & R_ROBIN_BITS;
 538         if (((id = inb(ioaddr + ID_REG)) & R_ROBIN_BITS) != (counter + 0x40))
 539                 return (0);
 540         /* yes the 82595 has been found */
 541         return (1);
 542 }
 543
 544 static struct nic_operations eepro_operations = {
 545         .connect        = dummy_connect,
 546         .poll           = eepro_poll,
 547         .transmit       = eepro_transmit,
 548         .irq            = eepro_irq,
 549
 550 };
 551
 552 /**************************************************************************
 553 PROBE - Look for an adapter, this routine's visible to the outside
 554 ***************************************************************************/
 555 static int eepro_probe ( struct nic *nic, struct isa_device *isa ) {
 556
 557         int             i, l_eepro = 0;
 558         union {
 559                 unsigned char   caddr[ETH_ALEN];
 560                 unsigned short  saddr[ETH_ALEN/2];
 561         } station_addr;
 562         const char *name;
 563
 564         nic->irqno  = 0;
 565         isa_fill_nic ( nic, isa );
 566         nic->ioaddr = isa->ioaddr;
 567
 568         station_addr.saddr[2] = read_eeprom(nic->ioaddr,2);
 569         if ( ( station_addr.saddr[2] == 0x0000 ) ||
 570              ( station_addr.saddr[2] == 0xFFFF ) ) {
 571                 l_eepro = 3;
 572                 eepro = LAN595FX_10ISA;
 573                 eeprom_reg= EEPROM_REG_10;
 574                 rcv_start = RCV_START_10;
 575                 xmt_lower_limit_reg = XMT_LOWER_LIMIT_REG_10;
 576                 xmt_upper_limit_reg = XMT_UPPER_LIMIT_REG_10;
 577                 station_addr.saddr[2] = read_eeprom(nic->ioaddr,2);
 578         }
 579         station_addr.saddr[1] = read_eeprom(nic->ioaddr,3);
 580         station_addr.saddr[0] = read_eeprom(nic->ioaddr,4);
 581         if (l_eepro)
 582                 name = "Intel EtherExpress 10 ISA";
 583         else if (read_eeprom(nic->ioaddr,7) == ee_FX_INT2IRQ) {
 584                 name = "Intel EtherExpress Pro/10+ ISA";
 585                 l_eepro = 2;
 586         } else if (station_addr.saddr[0] == SA_ADDR1) {
 587                 name = "Intel EtherExpress Pro/10 ISA";
 588                 l_eepro = 1;
 589         } else {
 590                 l_eepro = 0;
 591                 name = "Intel 82595-based LAN card";
 592         }
 593         station_addr.saddr[0] = swap16(station_addr.saddr[0]);
 594         station_addr.saddr[1] = swap16(station_addr.saddr[1]);
 595         station_addr.saddr[2] = swap16(station_addr.saddr[2]);
 596         for (i = 0; i < ETH_ALEN; i++) {
 597                 nic->node_addr[i] = station_addr.caddr[i];
 598         }
 599
 600         DBG ( "%s ioaddr %#hX, addr %s", name, nic->ioaddr, eth_ntoa ( nic->node_addr ) );
 601
 602         mem_start = RCV_LOWER_LIMIT << 8;
 603         if ((mem_end & 0x3F) < 3 || (mem_end & 0x3F) > 29)
 604                 mem_end = RCV_UPPER_LIMIT << 8;
 605         else {
 606                 mem_end = mem_end * 1024 + (RCV_LOWER_LIMIT << 8);
 607                 rcv_ram = mem_end - (RCV_LOWER_LIMIT << 8);
 608         }
 609         printf(", Rx mem %dK, if %s\n", (mem_end - mem_start) >> 10,
 610                 GetBit(read_eeprom(nic->ioaddr,5), ee_BNC_TPE) ? "BNC" : "TP");
 611
 612         eepro_reset(nic);
 613
 614         /* point to NIC specific routines */
 615         nic->nic_op     = &eepro_operations;
 616         return 1;
 617 }
 618
 619 static isa_probe_addr_t eepro_probe_addrs[] = {
 620         0x300, 0x210, 0x240, 0x280, 0x2C0, 0x200, 0x320, 0x340, 0x360,
 621 };
 622
 623 ISA_DRIVER ( eepro_driver, eepro_probe_addrs, eepro_probe1,
 624                      GENERIC_ISAPNP_VENDOR, 0x828a );
 625
 626 DRIVER ( "eepro", nic_driver, isa_driver, eepro_driver,
 627          eepro_probe, eepro_disable );
 628
 629 ISA_ROM ( "eepro", "Intel Etherexpress Pro/10" );