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Add errfile definition for new e1000.c
[gpxe.git] / src / drivers / net / etherfabric.c
blob6b76345160e51b64ad279edc82fc09dcaccbb622
1 /**************************************************************************
2 *
3 * Etherboot driver for Level 5 Etherfabric network cards
4 *
5 * Written by Michael Brown <mbrown@fensystems.co.uk>
6 *
7 * Copyright Fen Systems Ltd. 2005
8 * Copyright Level 5 Networks Inc. 2005
9 *
10 * This software may be used and distributed according to the terms of
11 * the GNU General Public License (GPL), incorporated herein by
12 * reference. Drivers based on or derived from this code fall under
13 * the GPL and must retain the authorship, copyright and license
14 * notice.
15 *
16 **************************************************************************
17 */
18
19 #include "etherboot.h"
20 #include "nic.h"
21 #include <errno.h>
22 #include <gpxe/pci.h>
23 #include <gpxe/bitbash.h>
24 #include <gpxe/i2c.h>
25 #include <gpxe/spi.h>
26 #include <gpxe/nvo.h>
27 #include "timer.h"
28 #define dma_addr_t unsigned long
29 #include "etherfabric.h"
30
31 /**************************************************************************
32 *
33 * Constants and macros
34 *
35 **************************************************************************
36 */
37
38 #define EFAB_ASSERT(x) \
39 do { \
40 if ( ! (x) ) { \
41 DBG ( "ASSERT(%s) failed at %s line %d [%s]\n", #x, \
42 __FILE__, __LINE__, __FUNCTION__ ); \
43 } \
44 } while (0)
45
46 #define EFAB_TRACE(...) DBG ( __VA_ARGS__ )
47
48 #define EFAB_REGDUMP(...)
49
50 #define EFAB_LOG(...) printf ( __VA_ARGS__ )
51 #define EFAB_ERR(...) printf ( __VA_ARGS__ )
52
53 #define FALCON_USE_IO_BAR 1
54
55 /*
56 * EtherFabric constants
57 *
58 */
59
60 /* PCI Definitions */
61 #define EFAB_VENDID_LEVEL5 0x1924
62 #define FALCON_P_DEVID 0x0703 /* Temporary PCI ID */
63 #define EF1002_DEVID 0xC101
64
65 /**************************************************************************
66 *
67 * Data structures
68 *
69 **************************************************************************
70 */
71
72 /*
73 * Buffers used for TX, RX and event queue
74 *
75 */
76 #define EFAB_BUF_ALIGN 4096
77 #define EFAB_DATA_BUF_SIZE 2048
78 #define EFAB_RX_BUFS 16
79 #define EFAB_RXD_SIZE 512
80 #define EFAB_TXD_SIZE 512
81 #define EFAB_EVQ_SIZE 512
82 struct efab_buffers {
83 uint8_t eventq[4096];
84 uint8_t rxd[4096];
85 uint8_t txd[4096];
86 uint8_t tx_buf[EFAB_DATA_BUF_SIZE];
87 uint8_t rx_buf[EFAB_RX_BUFS][EFAB_DATA_BUF_SIZE];
88 uint8_t padding[EFAB_BUF_ALIGN-1];
89 };
90 static struct efab_buffers efab_buffers;
91
92 /** An RX buffer */
93 struct efab_rx_buf {
94 uint8_t *addr;
95 unsigned int len;
96 int id;
97 };
98
99 /** A TX buffer */
100 struct efab_tx_buf {
101 uint8_t *addr;
102 unsigned int len;
103 int id;
104 };
105
106 /** Etherfabric event type */
107 enum efab_event_type {
108 EFAB_EV_NONE = 0,
109 EFAB_EV_TX,
110 EFAB_EV_RX,
111 };
112
113 /** Etherfabric event */
114 struct efab_event {
115 /** Event type */
116 enum efab_event_type type;
117 /** RX buffer ID */
118 int rx_id;
119 /** RX length */
120 unsigned int rx_len;
121 /** Packet should be dropped */
122 int drop;
123 };
124
125 /*
126 * Etherfabric abstraction layer
127 *
128 */
129 struct efab_nic;
130 struct efab_operations {
131 void ( * get_membase ) ( struct efab_nic *efab );
132 int ( * reset ) ( struct efab_nic *efab );
133 int ( * init_nic ) ( struct efab_nic *efab );
134 int ( * read_eeprom ) ( struct efab_nic *efab );
135 void ( * build_rx_desc ) ( struct efab_nic *efab,
136 struct efab_rx_buf *rx_buf );
137 void ( * notify_rx_desc ) ( struct efab_nic *efab );
138 void ( * build_tx_desc ) ( struct efab_nic *efab,
139 struct efab_tx_buf *tx_buf );
140 void ( * notify_tx_desc ) ( struct efab_nic *efab );
141 int ( * fetch_event ) ( struct efab_nic *efab,
142 struct efab_event *event );
143 void ( * mask_irq ) ( struct efab_nic *efab, int enabled );
144 void ( * generate_irq ) ( struct efab_nic *efab );
145 void ( * mdio_write ) ( struct efab_nic *efab, int location,
146 int value );
147 int ( * mdio_read ) ( struct efab_nic *efab, int location );
148 };
149
150 struct efab_mac_operations {
151 void ( * mac_writel ) ( struct efab_nic *efab, efab_dword_t *value,
152 unsigned int mac_reg );
153 void ( * mac_readl ) ( struct efab_nic *efab, efab_dword_t *value,
154 unsigned int mac_reg );
155 int ( * init ) ( struct efab_nic *efab );
156 int ( * reset ) ( struct efab_nic *efab );
157 };
158
159 /*
160 * Driver private data structure
161 *
162 */
163 struct efab_nic {
164
165 /** PCI device */
166 struct pci_device *pci;
167
168 /** Operations table */
169 struct efab_operations *op;
170
171 /** MAC operations table */
172 struct efab_mac_operations *mac_op;
173
174 /** Memory base */
175 void *membase;
176
177 /** I/O base */
178 unsigned int iobase;
179
180 /** Buffers */
181 uint8_t *eventq; /* Falcon only */
182 uint8_t *txd; /* Falcon only */
183 uint8_t *rxd; /* Falcon only */
184 struct efab_tx_buf tx_buf;
185 struct efab_rx_buf rx_bufs[EFAB_RX_BUFS];
186
187 /** Buffer pointers */
188 unsigned int eventq_read_ptr; /* Falcon only */
189 unsigned int tx_write_ptr;
190 unsigned int rx_write_ptr;
191
192 /** Port 0/1 on the NIC */
193 int port;
194
195 /** MAC address */
196 uint8_t mac_addr[ETH_ALEN];
197 /** GMII link options */
198 unsigned int link_options;
199 /** Link status */
200 int link_up;
201
202 /* Nic type fields */
203 int has_flash : 1;
204 int has_eeprom : 1;
205 int is_10g : 1;
206 int is_dual : 1;
207 int is_asic : 1;
208
209 /** INT_REG_KER for Falcon */
210 efab_oword_t int_ker __attribute__ (( aligned ( 16 ) ));
211
212 /** I2C access */
213 struct i2c_bit_basher ef1002_i2c;
214 unsigned long ef1002_i2c_outputs;
215 struct i2c_device ef1002_eeprom;
216
217 /** SPI access */
218 struct spi_bus spi;
219 struct spi_device falcon_flash;
220 struct spi_device falcon_eeprom;
221
222 /** Non-volatile options */
223 struct nvo_block nvo;
224 };
225
226 /**************************************************************************
227 *
228 * GMII routines
229 *
230 **************************************************************************
231 */
232
233 /* GMII registers */
234 #define MII_BMSR 0x01 /* Basic mode status register */
235 #define MII_ADVERTISE 0x04 /* Advertisement control register */
236 #define MII_LPA 0x05 /* Link partner ability register*/
237 #define GMII_GTCR 0x09 /* 1000BASE-T control register */
238 #define GMII_GTSR 0x0a /* 1000BASE-T status register */
239 #define GMII_PSSR 0x11 /* PHY-specific status register */
240
241 /* Basic mode status register. */
242 #define BMSR_LSTATUS 0x0004 /* Link status */
243
244 /* Link partner ability register. */
245 #define LPA_10HALF 0x0020 /* Can do 10mbps half-duplex */
246 #define LPA_10FULL 0x0040 /* Can do 10mbps full-duplex */
247 #define LPA_100HALF 0x0080 /* Can do 100mbps half-duplex */
248 #define LPA_100FULL 0x0100 /* Can do 100mbps full-duplex */
249 #define LPA_100BASE4 0x0200 /* Can do 100mbps 4k packets */
250 #define LPA_PAUSE 0x0400 /* Bit 10 - MAC pause */
251
252 /* Pseudo extensions to the link partner ability register */
253 #define LPA_1000FULL 0x00020000
254 #define LPA_1000HALF 0x00010000
255 #define LPA_10000FULL 0x00040000
256 #define LPA_10000HALF 0x00080000
257
258 #define LPA_100 (LPA_100FULL | LPA_100HALF | LPA_100BASE4)
259 #define LPA_1000 ( LPA_1000FULL | LPA_1000HALF )
260 #define LPA_10000 ( LPA_10000FULL | LPA_10000HALF )
261 #define LPA_DUPLEX ( LPA_10FULL | LPA_100FULL | LPA_1000FULL )
262
263 /* Mask of bits not associated with speed or duplexity. */
264 #define LPA_OTHER ~( LPA_10FULL | LPA_10HALF | LPA_100FULL | \
265 LPA_100HALF | LPA_1000FULL | LPA_1000HALF )
266
267 /* PHY-specific status register */
268 #define PSSR_LSTATUS 0x0400 /* Bit 10 - link status */
269
270 /**
271 * Retrieve GMII autonegotiation advertised abilities
272 *
273 */
274 static unsigned int gmii_autoneg_advertised ( struct efab_nic *efab ) {
275 unsigned int mii_advertise;
276 unsigned int gmii_advertise;
277
278 /* Extended bits are in bits 8 and 9 of GMII_GTCR */
279 mii_advertise = efab->op->mdio_read ( efab, MII_ADVERTISE );
280 gmii_advertise = ( ( efab->op->mdio_read ( efab, GMII_GTCR ) >> 8 )
281 & 0x03 );
282 return ( ( gmii_advertise << 16 ) | mii_advertise );
283 }
284
285 /**
286 * Retrieve GMII autonegotiation link partner abilities
287 *
288 */
289 static unsigned int gmii_autoneg_lpa ( struct efab_nic *efab ) {
290 unsigned int mii_lpa;
291 unsigned int gmii_lpa;
292
293 /* Extended bits are in bits 10 and 11 of GMII_GTSR */
294 mii_lpa = efab->op->mdio_read ( efab, MII_LPA );
295 gmii_lpa = ( efab->op->mdio_read ( efab, GMII_GTSR ) >> 10 ) & 0x03;
296 return ( ( gmii_lpa << 16 ) | mii_lpa );
297 }
298
299 /**
300 * Calculate GMII autonegotiated link technology
301 *
302 */
303 static unsigned int gmii_nway_result ( unsigned int negotiated ) {
304 unsigned int other_bits;
305
306 /* Mask out the speed and duplexity bits */
307 other_bits = negotiated & LPA_OTHER;
308
309 if ( negotiated & LPA_1000FULL )
310 return ( other_bits | LPA_1000FULL );
311 else if ( negotiated & LPA_1000HALF )
312 return ( other_bits | LPA_1000HALF );
313 else if ( negotiated & LPA_100FULL )
314 return ( other_bits | LPA_100FULL );
315 else if ( negotiated & LPA_100BASE4 )
316 return ( other_bits | LPA_100BASE4 );
317 else if ( negotiated & LPA_100HALF )
318 return ( other_bits | LPA_100HALF );
319 else if ( negotiated & LPA_10FULL )
320 return ( other_bits | LPA_10FULL );
321 else return ( other_bits | LPA_10HALF );
322 }
323
324 /**
325 * Check GMII PHY link status
326 *
327 */
328 static int gmii_link_ok ( struct efab_nic *efab ) {
329 int status;
330 int phy_status;
331
332 /* BMSR is latching - it returns "link down" if the link has
333 * been down at any point since the last read. To get a
334 * real-time status, we therefore read the register twice and
335 * use the result of the second read.
336 */
337 efab->op->mdio_read ( efab, MII_BMSR );
338 status = efab->op->mdio_read ( efab, MII_BMSR );
339
340 /* Read the PHY-specific Status Register. This is
341 * non-latching, so we need do only a single read.
342 */
343 phy_status = efab->op->mdio_read ( efab, GMII_PSSR );
344
345 return ( ( status & BMSR_LSTATUS ) && ( phy_status & PSSR_LSTATUS ) );
346 }
347
348 /**************************************************************************
349 *
350 * Alaska PHY
351 *
352 **************************************************************************
353 */
354
355 /**
356 * Initialise Alaska PHY
357 *
358 */
359 static void alaska_init ( struct efab_nic *efab ) {
360 unsigned int advertised, lpa;
361
362 /* Read link up status */
363 efab->link_up = gmii_link_ok ( efab );
364
365 if ( ! efab->link_up )
366 return;
367
368 /* Determine link options from PHY. */
369 advertised = gmii_autoneg_advertised ( efab );
370 lpa = gmii_autoneg_lpa ( efab );
371 efab->link_options = gmii_nway_result ( advertised & lpa );
372
373 /* print out the link speed */
374 EFAB_LOG ( "%dMbps %s-duplex (%04x,%04x)\n",
375 ( efab->link_options & LPA_10000 ? 1000 :
376 ( efab->link_options & LPA_1000 ? 1000 :
377 ( efab->link_options & LPA_100 ? 100 : 10 ) ) ),
378 ( efab->link_options & LPA_DUPLEX ? "full" : "half" ),
379 advertised, lpa );
380 }
381
382
383 /**************************************************************************
384 *
385 * Mentor MAC
386 *
387 **************************************************************************
388 */
389
390 /* GMAC configuration register 1 */
391 #define GM_CFG1_REG_MAC 0x00
392 #define GM_SW_RST_LBN 31
393 #define GM_SW_RST_WIDTH 1
394 #define GM_RX_FC_EN_LBN 5
395 #define GM_RX_FC_EN_WIDTH 1
396 #define GM_TX_FC_EN_LBN 4
397 #define GM_TX_FC_EN_WIDTH 1
398 #define GM_RX_EN_LBN 2
399 #define GM_RX_EN_WIDTH 1
400 #define GM_TX_EN_LBN 0
401 #define GM_TX_EN_WIDTH 1
402
403 /* GMAC configuration register 2 */
404 #define GM_CFG2_REG_MAC 0x01
405 #define GM_PAMBL_LEN_LBN 12
406 #define GM_PAMBL_LEN_WIDTH 4
407 #define GM_IF_MODE_LBN 8
408 #define GM_IF_MODE_WIDTH 2
409 #define GM_PAD_CRC_EN_LBN 2
410 #define GM_PAD_CRC_EN_WIDTH 1
411 #define GM_FD_LBN 0
412 #define GM_FD_WIDTH 1
413
414 /* GMAC maximum frame length register */
415 #define GM_MAX_FLEN_REG_MAC 0x04
416 #define GM_MAX_FLEN_LBN 0
417 #define GM_MAX_FLEN_WIDTH 16
418
419 /* GMAC MII management configuration register */
420 #define GM_MII_MGMT_CFG_REG_MAC 0x08
421 #define GM_MGMT_CLK_SEL_LBN 0
422 #define GM_MGMT_CLK_SEL_WIDTH 3
423
424 /* GMAC MII management command register */
425 #define GM_MII_MGMT_CMD_REG_MAC 0x09
426 #define GM_MGMT_SCAN_CYC_LBN 1
427 #define GM_MGMT_SCAN_CYC_WIDTH 1
428 #define GM_MGMT_RD_CYC_LBN 0
429 #define GM_MGMT_RD_CYC_WIDTH 1
430
431 /* GMAC MII management address register */
432 #define GM_MII_MGMT_ADR_REG_MAC 0x0a
433 #define GM_MGMT_PHY_ADDR_LBN 8
434 #define GM_MGMT_PHY_ADDR_WIDTH 5
435 #define GM_MGMT_REG_ADDR_LBN 0
436 #define GM_MGMT_REG_ADDR_WIDTH 5
437
438 /* GMAC MII management control register */
439 #define GM_MII_MGMT_CTL_REG_MAC 0x0b
440 #define GM_MGMT_CTL_LBN 0
441 #define GM_MGMT_CTL_WIDTH 16
442
443 /* GMAC MII management status register */
444 #define GM_MII_MGMT_STAT_REG_MAC 0x0c
445 #define GM_MGMT_STAT_LBN 0
446 #define GM_MGMT_STAT_WIDTH 16
447
448 /* GMAC MII management indicators register */
449 #define GM_MII_MGMT_IND_REG_MAC 0x0d
450 #define GM_MGMT_BUSY_LBN 0
451 #define GM_MGMT_BUSY_WIDTH 1
452
453 /* GMAC station address register 1 */
454 #define GM_ADR1_REG_MAC 0x10
455 #define GM_HWADDR_5_LBN 24
456 #define GM_HWADDR_5_WIDTH 8
457 #define GM_HWADDR_4_LBN 16
458 #define GM_HWADDR_4_WIDTH 8
459 #define GM_HWADDR_3_LBN 8
460 #define GM_HWADDR_3_WIDTH 8
461 #define GM_HWADDR_2_LBN 0
462 #define GM_HWADDR_2_WIDTH 8
463
464 /* GMAC station address register 2 */
465 #define GM_ADR2_REG_MAC 0x11
466 #define GM_HWADDR_1_LBN 24
467 #define GM_HWADDR_1_WIDTH 8
468 #define GM_HWADDR_0_LBN 16
469 #define GM_HWADDR_0_WIDTH 8
470
471 /* GMAC FIFO configuration register 0 */
472 #define GMF_CFG0_REG_MAC 0x12
473 #define GMF_FTFENREQ_LBN 12
474 #define GMF_FTFENREQ_WIDTH 1
475 #define GMF_STFENREQ_LBN 11
476 #define GMF_STFENREQ_WIDTH 1
477 #define GMF_FRFENREQ_LBN 10
478 #define GMF_FRFENREQ_WIDTH 1
479 #define GMF_SRFENREQ_LBN 9
480 #define GMF_SRFENREQ_WIDTH 1
481 #define GMF_WTMENREQ_LBN 8
482 #define GMF_WTMENREQ_WIDTH 1
483
484 /* GMAC FIFO configuration register 1 */
485 #define GMF_CFG1_REG_MAC 0x13
486 #define GMF_CFGFRTH_LBN 16
487 #define GMF_CFGFRTH_WIDTH 5
488 #define GMF_CFGXOFFRTX_LBN 0
489 #define GMF_CFGXOFFRTX_WIDTH 16
490
491 /* GMAC FIFO configuration register 2 */
492 #define GMF_CFG2_REG_MAC 0x14
493 #define GMF_CFGHWM_LBN 16
494 #define GMF_CFGHWM_WIDTH 6
495 #define GMF_CFGLWM_LBN 0
496 #define GMF_CFGLWM_WIDTH 6
497
498 /* GMAC FIFO configuration register 3 */
499 #define GMF_CFG3_REG_MAC 0x15
500 #define GMF_CFGHWMFT_LBN 16
501 #define GMF_CFGHWMFT_WIDTH 6
502 #define GMF_CFGFTTH_LBN 0
503 #define GMF_CFGFTTH_WIDTH 6
504
505 /* GMAC FIFO configuration register 4 */
506 #define GMF_CFG4_REG_MAC 0x16
507 #define GMF_HSTFLTRFRM_PAUSE_LBN 12
508 #define GMF_HSTFLTRFRM_PAUSE_WIDTH 12
509
510 /* GMAC FIFO configuration register 5 */
511 #define GMF_CFG5_REG_MAC 0x17
512 #define GMF_CFGHDPLX_LBN 22
513 #define GMF_CFGHDPLX_WIDTH 1
514 #define GMF_CFGBYTMODE_LBN 19
515 #define GMF_CFGBYTMODE_WIDTH 1
516 #define GMF_HSTDRPLT64_LBN 18
517 #define GMF_HSTDRPLT64_WIDTH 1
518 #define GMF_HSTFLTRFRMDC_PAUSE_LBN 12
519 #define GMF_HSTFLTRFRMDC_PAUSE_WIDTH 1
520
521 struct efab_mentormac_parameters {
522 int gmf_cfgfrth;
523 int gmf_cfgftth;
524 int gmf_cfghwmft;
525 int gmf_cfghwm;
526 int gmf_cfglwm;
527 };
528
529 /**
530 * Reset Mentor MAC
531 *
532 */
533 static void mentormac_reset ( struct efab_nic *efab ) {
534 efab_dword_t reg;
535 int save_port;
536
537 /* Take into reset */
538 EFAB_POPULATE_DWORD_1 ( reg, GM_SW_RST, 1 );
539 efab->mac_op->mac_writel ( efab, &reg, GM_CFG1_REG_MAC );
540 udelay ( 1000 );
541
542 /* Take out of reset */
543 EFAB_POPULATE_DWORD_1 ( reg, GM_SW_RST, 0 );
544 efab->mac_op->mac_writel ( efab, &reg, GM_CFG1_REG_MAC );
545 udelay ( 1000 );
546
547 /* Mentor MAC connects both PHYs to MAC 0 */
548 save_port = efab->port;
549 efab->port = 0;
550 /* Configure GMII interface so PHY is accessible. Note that
551 * GMII interface is connected only to port 0, and that on
552 * Falcon this is a no-op.
553 */
554 EFAB_POPULATE_DWORD_1 ( reg, GM_MGMT_CLK_SEL, 0x4 );
555 efab->mac_op->mac_writel ( efab, &reg, GM_MII_MGMT_CFG_REG_MAC );
556 udelay ( 10 );
557 efab->port = save_port;
558 }
559
560 /**
561 * Initialise Mentor MAC
562 *
563 */
564 static void mentormac_init ( struct efab_nic *efab,
565 struct efab_mentormac_parameters *params ) {
566 int pause, if_mode, full_duplex, bytemode, half_duplex;
567 efab_dword_t reg;
568
569 /* Configuration register 1 */
570 pause = ( efab->link_options & LPA_PAUSE ) ? 1 : 0;
571 if ( ! ( efab->link_options & LPA_DUPLEX ) ) {
572 /* Half-duplex operation requires TX flow control */
573 pause = 1;
574 }
575 EFAB_POPULATE_DWORD_4 ( reg,
576 GM_TX_EN, 1,
577 GM_TX_FC_EN, pause,
578 GM_RX_EN, 1,
579 GM_RX_FC_EN, 1 );
580 efab->mac_op->mac_writel ( efab, &reg, GM_CFG1_REG_MAC );
581 udelay ( 10 );
582
583 /* Configuration register 2 */
584 if_mode = ( efab->link_options & LPA_1000 ) ? 2 : 1;
585 full_duplex = ( efab->link_options & LPA_DUPLEX ) ? 1 : 0;
586 EFAB_POPULATE_DWORD_4 ( reg,
587 GM_IF_MODE, if_mode,
588 GM_PAD_CRC_EN, 1,
589 GM_FD, full_duplex,
590 GM_PAMBL_LEN, 0x7 /* ? */ );
591 efab->mac_op->mac_writel ( efab, &reg, GM_CFG2_REG_MAC );
592 udelay ( 10 );
593
594 /* Max frame len register */
595 EFAB_POPULATE_DWORD_1 ( reg, GM_MAX_FLEN, ETH_FRAME_LEN + 4 /* FCS */);
596 efab->mac_op->mac_writel ( efab, &reg, GM_MAX_FLEN_REG_MAC );
597 udelay ( 10 );
598
599 /* FIFO configuration register 0 */
600 EFAB_POPULATE_DWORD_5 ( reg,
601 GMF_FTFENREQ, 1,
602 GMF_STFENREQ, 1,
603 GMF_FRFENREQ, 1,
604 GMF_SRFENREQ, 1,
605 GMF_WTMENREQ, 1 );
606 efab->mac_op->mac_writel ( efab, &reg, GMF_CFG0_REG_MAC );
607 udelay ( 10 );
608
609 /* FIFO configuration register 1 */
610 EFAB_POPULATE_DWORD_2 ( reg,
611 GMF_CFGFRTH, params->gmf_cfgfrth,
612 GMF_CFGXOFFRTX, 0xffff );
613 efab->mac_op->mac_writel ( efab, &reg, GMF_CFG1_REG_MAC );
614 udelay ( 10 );
615
616 /* FIFO configuration register 2 */
617 EFAB_POPULATE_DWORD_2 ( reg,
618 GMF_CFGHWM, params->gmf_cfghwm,
619 GMF_CFGLWM, params->gmf_cfglwm );
620 efab->mac_op->mac_writel ( efab, &reg, GMF_CFG2_REG_MAC );
621 udelay ( 10 );
622
623 /* FIFO configuration register 3 */
624 EFAB_POPULATE_DWORD_2 ( reg,
625 GMF_CFGHWMFT, params->gmf_cfghwmft,
626 GMF_CFGFTTH, params->gmf_cfgftth );
627 efab->mac_op->mac_writel ( efab, &reg, GMF_CFG3_REG_MAC );
628 udelay ( 10 );
629
630 /* FIFO configuration register 4 */
631 EFAB_POPULATE_DWORD_1 ( reg, GMF_HSTFLTRFRM_PAUSE, 1 );
632 efab->mac_op->mac_writel ( efab, &reg, GMF_CFG4_REG_MAC );
633 udelay ( 10 );
634
635 /* FIFO configuration register 5 */
636 bytemode = ( efab->link_options & LPA_1000 ) ? 1 : 0;
637 half_duplex = ( efab->link_options & LPA_DUPLEX ) ? 0 : 1;
638 efab->mac_op->mac_readl ( efab, &reg, GMF_CFG5_REG_MAC );
639 EFAB_SET_DWORD_FIELD ( reg, GMF_CFGBYTMODE, bytemode );
640 EFAB_SET_DWORD_FIELD ( reg, GMF_CFGHDPLX, half_duplex );
641 EFAB_SET_DWORD_FIELD ( reg, GMF_HSTDRPLT64, half_duplex );
642 EFAB_SET_DWORD_FIELD ( reg, GMF_HSTFLTRFRMDC_PAUSE, 0 );
643 efab->mac_op->mac_writel ( efab, &reg, GMF_CFG5_REG_MAC );
644 udelay ( 10 );
645
646 /* MAC address */
647 EFAB_POPULATE_DWORD_4 ( reg,
648 GM_HWADDR_5, efab->mac_addr[5],
649 GM_HWADDR_4, efab->mac_addr[4],
650 GM_HWADDR_3, efab->mac_addr[3],
651 GM_HWADDR_2, efab->mac_addr[2] );
652 efab->mac_op->mac_writel ( efab, &reg, GM_ADR1_REG_MAC );
653 udelay ( 10 );
654 EFAB_POPULATE_DWORD_2 ( reg,
655 GM_HWADDR_1, efab->mac_addr[1],
656 GM_HWADDR_0, efab->mac_addr[0] );
657 efab->mac_op->mac_writel ( efab, &reg, GM_ADR2_REG_MAC );
658 udelay ( 10 );
659 }
660
661 /**
662 * Wait for GMII access to complete
663 *
664 */
665 static int mentormac_gmii_wait ( struct efab_nic *efab ) {
666 int count;
667 efab_dword_t indicator;
668
669 for ( count = 0 ; count < 1000 ; count++ ) {
670 udelay ( 10 );
671 efab->mac_op->mac_readl ( efab, &indicator,
672 GM_MII_MGMT_IND_REG_MAC );
673 if ( EFAB_DWORD_FIELD ( indicator, GM_MGMT_BUSY ) == 0 )
674 return 1;
675 }
676 EFAB_ERR ( "Timed out waiting for GMII\n" );
677 return 0;
678 }
679
680 /**
681 * Write a GMII register
682 *
683 */
684 static void mentormac_mdio_write ( struct efab_nic *efab, int phy_id,
685 int location, int value ) {
686 efab_dword_t reg;
687 int save_port;
688
689 EFAB_TRACE ( "Writing GMII %d register %02x with %04x\n", phy_id,
690 location, value );
691
692 /* Mentor MAC connects both PHYs to MAC 0 */
693 save_port = efab->port;
694 efab->port = 0;
695
696 /* Check MII not currently being accessed */
697 if ( ! mentormac_gmii_wait ( efab ) )
698 goto out;
699
700 /* Write the address register */
701 EFAB_POPULATE_DWORD_2 ( reg,
702 GM_MGMT_PHY_ADDR, phy_id,
703 GM_MGMT_REG_ADDR, location );
704 efab->mac_op->mac_writel ( efab, &reg, GM_MII_MGMT_ADR_REG_MAC );
705 udelay ( 10 );
706
707 /* Write data */
708 EFAB_POPULATE_DWORD_1 ( reg, GM_MGMT_CTL, value );
709 efab->mac_op->mac_writel ( efab, &reg, GM_MII_MGMT_CTL_REG_MAC );
710
711 /* Wait for data to be written */
712 mentormac_gmii_wait ( efab );
713
714 out:
715 /* Restore efab->port */
716 efab->port = save_port;
717 }
718
719 /**
720 * Read a GMII register
721 *
722 */
723 static int mentormac_mdio_read ( struct efab_nic *efab, int phy_id,
724 int location ) {
725 efab_dword_t reg;
726 int value = 0xffff;
727 int save_port;
728
729 /* Mentor MAC connects both PHYs to MAC 0 */
730 save_port = efab->port;
731 efab->port = 0;
732
733 /* Check MII not currently being accessed */
734 if ( ! mentormac_gmii_wait ( efab ) )
735 goto out;
736
737 /* Write the address register */
738 EFAB_POPULATE_DWORD_2 ( reg,
739 GM_MGMT_PHY_ADDR, phy_id,
740 GM_MGMT_REG_ADDR, location );
741 efab->mac_op->mac_writel ( efab, &reg, GM_MII_MGMT_ADR_REG_MAC );
742 udelay ( 10 );
743
744 /* Request data to be read */
745 EFAB_POPULATE_DWORD_1 ( reg, GM_MGMT_RD_CYC, 1 );
746 efab->mac_op->mac_writel ( efab, &reg, GM_MII_MGMT_CMD_REG_MAC );
747
748 /* Wait for data to be become available */
749 if ( mentormac_gmii_wait ( efab ) ) {
750 /* Read data */
751 efab->mac_op->mac_readl ( efab, &reg, GM_MII_MGMT_STAT_REG_MAC );
752 value = EFAB_DWORD_FIELD ( reg, GM_MGMT_STAT );
753 EFAB_TRACE ( "Read from GMII %d register %02x, got %04x\n",
754 phy_id, location, value );
755 }
756
757 /* Signal completion */
758 EFAB_ZERO_DWORD ( reg );
759 efab->mac_op->mac_writel ( efab, &reg, GM_MII_MGMT_CMD_REG_MAC );
760 udelay ( 10 );
761
762 out:
763 /* Restore efab->port */
764 efab->port = save_port;
765
766 return value;
767 }
768
769 /**************************************************************************
770 *
771 * EF1002 routines
772 *
773 **************************************************************************
774 */
775
776 /** Control and General Status */
777 #define EF1_CTR_GEN_STATUS0_REG 0x0
778 #define EF1_MASTER_EVENTS_LBN 12
779 #define EF1_MASTER_EVENTS_WIDTH 1
780 #define EF1_TX_ENGINE_EN_LBN 19
781 #define EF1_TX_ENGINE_EN_WIDTH 1
782 #define EF1_RX_ENGINE_EN_LBN 18
783 #define EF1_RX_ENGINE_EN_WIDTH 1
784 #define EF1_TURBO2_LBN 17
785 #define EF1_TURBO2_WIDTH 1
786 #define EF1_TURBO1_LBN 16
787 #define EF1_TURBO1_WIDTH 1
788 #define EF1_TURBO3_LBN 14
789 #define EF1_TURBO3_WIDTH 1
790 #define EF1_LB_RESET_LBN 3
791 #define EF1_LB_RESET_WIDTH 1
792 #define EF1_MAC_RESET_LBN 2
793 #define EF1_MAC_RESET_WIDTH 1
794 #define EF1_CAM_ENABLE_LBN 1
795 #define EF1_CAM_ENABLE_WIDTH 1
796
797 /** IRQ sources */
798 #define EF1_IRQ_SRC_REG 0x0008
799
800 /** IRQ mask */
801 #define EF1_IRQ_MASK_REG 0x000c
802 #define EF1_IRQ_PHY1_LBN 11
803 #define EF1_IRQ_PHY1_WIDTH 1
804 #define EF1_IRQ_PHY0_LBN 10
805 #define EF1_IRQ_PHY0_WIDTH 1
806 #define EF1_IRQ_SERR_LBN 7
807 #define EF1_IRQ_SERR_WIDTH 1
808 #define EF1_IRQ_EVQ_LBN 3
809 #define EF1_IRQ_EVQ_WIDTH 1
810
811 /** Event generation */
812 #define EF1_EVT3_REG 0x38
813
814 /** EEPROMaccess */
815 #define EF1_EEPROM_REG 0x40
816 #define EF1_EEPROM_SDA_LBN 31
817 #define EF1_EEPROM_SDA_WIDTH 1
818 #define EF1_EEPROM_SCL_LBN 30
819 #define EF1_EEPROM_SCL_WIDTH 1
820 #define EF1_JTAG_DISCONNECT_LBN 17
821 #define EF1_JTAG_DISCONNECT_WIDTH 1
822 #define EF1_EEPROM_LBN 0
823 #define EF1_EEPROM_WIDTH 32
824
825 /** Control register 2 */
826 #define EF1_CTL2_REG 0x4c
827 #define EF1_PLL_TRAP_LBN 31
828 #define EF1_PLL_TRAP_WIDTH 1
829 #define EF1_MEM_MAP_4MB_LBN 11
830 #define EF1_MEM_MAP_4MB_WIDTH 1
831 #define EF1_EV_INTR_CLR_WRITE_LBN 6
832 #define EF1_EV_INTR_CLR_WRITE_WIDTH 1
833 #define EF1_BURST_MERGE_LBN 5
834 #define EF1_BURST_MERGE_WIDTH 1
835 #define EF1_CLEAR_NULL_PAD_LBN 4
836 #define EF1_CLEAR_NULL_PAD_WIDTH 1
837 #define EF1_SW_RESET_LBN 2
838 #define EF1_SW_RESET_WIDTH 1
839 #define EF1_INTR_AFTER_EVENT_LBN 1
840 #define EF1_INTR_AFTER_EVENT_WIDTH 1
841
842 /** Event FIFO */
843 #define EF1_EVENT_FIFO_REG 0x50
844
845 /** Event FIFO count */
846 #define EF1_EVENT_FIFO_COUNT_REG 0x5c
847 #define EF1_EV_COUNT_LBN 0
848 #define EF1_EV_COUNT_WIDTH 16
849
850 /** TX DMA control and status */
851 #define EF1_DMA_TX_CSR_REG 0x80
852 #define EF1_DMA_TX_CSR_CHAIN_EN_LBN 8
853 #define EF1_DMA_TX_CSR_CHAIN_EN_WIDTH 1
854 #define EF1_DMA_TX_CSR_ENABLE_LBN 4
855 #define EF1_DMA_TX_CSR_ENABLE_WIDTH 1
856 #define EF1_DMA_TX_CSR_INT_EN_LBN 0
857 #define EF1_DMA_TX_CSR_INT_EN_WIDTH 1
858
859 /** RX DMA control and status */
860 #define EF1_DMA_RX_CSR_REG 0xa0
861 #define EF1_DMA_RX_ABOVE_1GB_EN_LBN 6
862 #define EF1_DMA_RX_ABOVE_1GB_EN_WIDTH 1
863 #define EF1_DMA_RX_BELOW_1MB_EN_LBN 5
864 #define EF1_DMA_RX_BELOW_1MB_EN_WIDTH 1
865 #define EF1_DMA_RX_CSR_ENABLE_LBN 0
866 #define EF1_DMA_RX_CSR_ENABLE_WIDTH 1
867
868 /** Level 5 watermark register (in MAC space) */
869 #define EF1_GMF_L5WM_REG_MAC 0x20
870 #define EF1_L5WM_LBN 0
871 #define EF1_L5WM_WIDTH 32
872
873 /** MAC clock */
874 #define EF1_GM_MAC_CLK_REG 0x112000
875 #define EF1_GM_PORT0_MAC_CLK_LBN 0
876 #define EF1_GM_PORT0_MAC_CLK_WIDTH 1
877 #define EF1_GM_PORT1_MAC_CLK_LBN 1
878 #define EF1_GM_PORT1_MAC_CLK_WIDTH 1
879
880 /** TX descriptor FIFO */
881 #define EF1_TX_DESC_FIFO 0x141000
882 #define EF1_TX_KER_EVQ_LBN 80
883 #define EF1_TX_KER_EVQ_WIDTH 12
884 #define EF1_TX_KER_IDX_LBN 64
885 #define EF1_TX_KER_IDX_WIDTH 16
886 #define EF1_TX_KER_MODE_LBN 63
887 #define EF1_TX_KER_MODE_WIDTH 1
888 #define EF1_TX_KER_PORT_LBN 60
889 #define EF1_TX_KER_PORT_WIDTH 1
890 #define EF1_TX_KER_CONT_LBN 56
891 #define EF1_TX_KER_CONT_WIDTH 1
892 #define EF1_TX_KER_BYTE_CNT_LBN 32
893 #define EF1_TX_KER_BYTE_CNT_WIDTH 24
894 #define EF1_TX_KER_BUF_ADR_LBN 0
895 #define EF1_TX_KER_BUF_ADR_WIDTH 32
896
897 /** TX descriptor FIFO flush */
898 #define EF1_TX_DESC_FIFO_FLUSH 0x141ffc
899
900 /** RX descriptor FIFO */
901 #define EF1_RX_DESC_FIFO 0x145000
902 #define EF1_RX_KER_EVQ_LBN 48
903 #define EF1_RX_KER_EVQ_WIDTH 12
904 #define EF1_RX_KER_IDX_LBN 32
905 #define EF1_RX_KER_IDX_WIDTH 16
906 #define EF1_RX_KER_BUF_ADR_LBN 0
907 #define EF1_RX_KER_BUF_ADR_WIDTH 32
908
909 /** RX descriptor FIFO flush */
910 #define EF1_RX_DESC_FIFO_FLUSH 0x145ffc
911
912 /** CAM */
913 #define EF1_CAM_BASE 0x1c0000
914 #define EF1_CAM_WTF_DOES_THIS_DO_LBN 0
915 #define EF1_CAM_WTF_DOES_THIS_DO_WIDTH 32
916
917 /** Event queue pointers */
918 #define EF1_EVQ_PTR_BASE 0x260000
919 #define EF1_EVQ_SIZE_LBN 29
920 #define EF1_EVQ_SIZE_WIDTH 2
921 #define EF1_EVQ_SIZE_4K 3
922 #define EF1_EVQ_SIZE_2K 2
923 #define EF1_EVQ_SIZE_1K 1
924 #define EF1_EVQ_SIZE_512 0
925 #define EF1_EVQ_BUF_BASE_ID_LBN 0
926 #define EF1_EVQ_BUF_BASE_ID_WIDTH 29
927
928 /* MAC registers */
929 #define EF1002_MAC_REGBANK 0x110000
930 #define EF1002_MAC_REGBANK_SIZE 0x1000
931 #define EF1002_MAC_REG_SIZE 0x08
932
933 /** Offset of a MAC register within EF1002 */
934 #define EF1002_MAC_REG( efab, mac_reg ) \
935 ( EF1002_MAC_REGBANK + \
936 ( (efab)->port * EF1002_MAC_REGBANK_SIZE ) + \
937 ( (mac_reg) * EF1002_MAC_REG_SIZE ) )
938
939 /* Event queue entries */
940 #define EF1_EV_CODE_LBN 20
941 #define EF1_EV_CODE_WIDTH 8
942 #define EF1_RX_EV_DECODE 0x01
943 #define EF1_TX_EV_DECODE 0x02
944 #define EF1_TIMER_EV_DECODE 0x0b
945 #define EF1_DRV_GEN_EV_DECODE 0x0f
946
947 /* Receive events */
948 #define EF1_RX_EV_LEN_LBN 48
949 #define EF1_RX_EV_LEN_WIDTH 16
950 #define EF1_RX_EV_PORT_LBN 17
951 #define EF1_RX_EV_PORT_WIDTH 3
952 #define EF1_RX_EV_OK_LBN 16
953 #define EF1_RX_EV_OK_WIDTH 1
954 #define EF1_RX_EV_IDX_LBN 0
955 #define EF1_RX_EV_IDX_WIDTH 16
956
957 /* Transmit events */
958 #define EF1_TX_EV_PORT_LBN 17
959 #define EF1_TX_EV_PORT_WIDTH 3
960 #define EF1_TX_EV_OK_LBN 16
961 #define EF1_TX_EV_OK_WIDTH 1
962 #define EF1_TX_EV_IDX_LBN 0
963 #define EF1_TX_EV_IDX_WIDTH 16
964
965 /* forward decleration */
966 static struct efab_mac_operations ef1002_mac_operations;
967
968 /* I2C ID of the EEPROM */
969 #define EF1_EEPROM_I2C_ID 0x50
970
971 /* Offset of MAC address within EEPROM */
972 #define EF1_EEPROM_HWADDR_OFFSET 0x0
973
974 /**
975 * Write dword to EF1002 register
976 *
977 */
978 static inline void ef1002_writel ( struct efab_nic *efab, efab_dword_t *value,
979 unsigned int reg ) {
980 EFAB_REGDUMP ( "Writing register %x with " EFAB_DWORD_FMT "\n",
981 reg, EFAB_DWORD_VAL ( *value ) );
982 writel ( value->u32[0], efab->membase + reg );
983 }
984
985 /**
986 * Read dword from an EF1002 register
987 *
988 */
989 static inline void ef1002_readl ( struct efab_nic *efab, efab_dword_t *value,
990 unsigned int reg ) {
991 value->u32[0] = readl ( efab->membase + reg );
992 EFAB_REGDUMP ( "Read from register %x, got " EFAB_DWORD_FMT "\n",
993 reg, EFAB_DWORD_VAL ( *value ) );
994 }
995
996 /**
997 * Read dword from an EF1002 register, silently
998 *
999 */
1000 static inline void ef1002_readl_silent ( struct efab_nic *efab,
1001 efab_dword_t *value,
1002 unsigned int reg ) {
1003 value->u32[0] = readl ( efab->membase + reg );
1004 }
1005
1006 /**
1007 * Get memory base
1008 *
1009 */
1010 static void ef1002_get_membase ( struct efab_nic *efab ) {
1011 unsigned long membase_phys;
1012
1013 membase_phys = pci_bar_start ( efab->pci, PCI_BASE_ADDRESS_0 );
1014 efab->membase = ioremap ( membase_phys, 0x800000 );
1015 }
1016
1017 /** PCI registers to backup/restore over a device reset */
1018 static const unsigned int efab_pci_reg_addr[] = {
1019 PCI_COMMAND, 0x0c /* PCI_CACHE_LINE_SIZE */,
1020 PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_1, PCI_BASE_ADDRESS_2,
1021 PCI_BASE_ADDRESS_3, PCI_ROM_ADDRESS, PCI_INTERRUPT_LINE,
1022 };
1023 /** Number of registers in efab_pci_reg_addr */
1024 #define EFAB_NUM_PCI_REG \
1025 ( sizeof ( efab_pci_reg_addr ) / sizeof ( efab_pci_reg_addr[0] ) )
1026 /** PCI configuration space backup */
1027 struct efab_pci_reg {
1028 uint32_t reg[EFAB_NUM_PCI_REG];
1029 };
1030
1031 /*
1032 * I2C interface and EEPROM
1033 *
1034 */
1035
1036 static unsigned long ef1002_i2c_bits[] = {
1037 [I2C_BIT_SCL] = ( 1 << 30 ),
1038 [I2C_BIT_SDA] = ( 1 << 31 ),
1039 };
1040
1041 static void ef1002_i2c_write_bit ( struct bit_basher *basher,
1042 unsigned int bit_id, unsigned long data ) {
1043 struct efab_nic *efab = container_of ( basher, struct efab_nic,
1044 ef1002_i2c.basher );
1045 unsigned long mask;
1046 efab_dword_t reg;
1047
1048 mask = ef1002_i2c_bits[bit_id];
1049 efab->ef1002_i2c_outputs &= ~mask;
1050 efab->ef1002_i2c_outputs |= ( data & mask );
1051 EFAB_POPULATE_DWORD_1 ( reg, EF1_EEPROM, efab->ef1002_i2c_outputs );
1052 ef1002_writel ( efab, &reg, EF1_EEPROM_REG );
1053 }
1054
1055 static int ef1002_i2c_read_bit ( struct bit_basher *basher,
1056 unsigned int bit_id ) {
1057 struct efab_nic *efab = container_of ( basher, struct efab_nic,
1058 ef1002_i2c.basher );
1059 unsigned long mask;
1060 efab_dword_t reg;
1061
1062 mask = ef1002_i2c_bits[bit_id];
1063 ef1002_readl ( efab, &reg, EF1_EEPROM_REG );
1064 return ( EFAB_DWORD_FIELD ( reg, EF1_EEPROM ) & mask );
1065 }
1066
1067 static struct bit_basher_operations ef1002_basher_ops = {
1068 .read = ef1002_i2c_read_bit,
1069 .write = ef1002_i2c_write_bit,
1070 };
1071
1072 static void ef1002_init_eeprom ( struct efab_nic *efab ) {
1073 efab->ef1002_i2c.basher.op = &ef1002_basher_ops;
1074 init_i2c_bit_basher ( &efab->ef1002_i2c );
1075 efab->ef1002_eeprom.address = EF1_EEPROM_I2C_ID;
1076 }
1077
1078 /**
1079 * Reset device
1080 *
1081 */
1082 static int ef1002_reset ( struct efab_nic *efab ) {
1083 struct efab_pci_reg pci_reg;
1084 struct pci_device *pci_dev = efab->pci;
1085 efab_dword_t reg;
1086 unsigned int i;
1087 uint32_t tmp;
1088
1089 /* Back up PCI configuration registers */
1090 for ( i = 0 ; i < EFAB_NUM_PCI_REG ; i++ ) {
1091 pci_read_config_dword ( pci_dev, efab_pci_reg_addr[i],
1092 &pci_reg.reg[i] );
1093 }
1094
1095 /* Reset the whole device. */
1096 EFAB_POPULATE_DWORD_1 ( reg, EF1_SW_RESET, 1 );
1097 ef1002_writel ( efab, &reg, EF1_CTL2_REG );
1098 mdelay ( 200 );
1099
1100 /* Restore PCI configuration space */
1101 for ( i = 0 ; i < EFAB_NUM_PCI_REG ; i++ ) {
1102 pci_write_config_dword ( pci_dev, efab_pci_reg_addr[i],
1103 pci_reg.reg[i] );
1104 }
1105
1106 /* Verify PCI configuration space */
1107 for ( i = 0 ; i < EFAB_NUM_PCI_REG ; i++ ) {
1108 pci_read_config_dword ( pci_dev, efab_pci_reg_addr[i], &tmp );
1109 if ( tmp != pci_reg.reg[i] ) {
1110 EFAB_LOG ( "PCI restore failed on register %02x "
1111 "(is %08lx, should be %08lx); reboot\n",
1112 i, tmp, pci_reg.reg[i] );
1113 return 0;
1114 }
1115 }
1116
1117 /* Verify device reset complete */
1118 ef1002_readl ( efab, &reg, EF1_CTR_GEN_STATUS0_REG );
1119 if ( EFAB_DWORD_IS_ALL_ONES ( reg ) ) {
1120 EFAB_ERR ( "Reset failed\n" );
1121 return 0;
1122 }
1123
1124 return 1;
1125 }
1126
1127 /**
1128 * Initialise NIC
1129 *
1130 */
1131 static int ef1002_init_nic ( struct efab_nic *efab ) {
1132 efab_dword_t reg;
1133
1134 /* patch in the MAC operations */
1135 efab->mac_op = &ef1002_mac_operations;
1136
1137 /* No idea what CAM is, but the 'datasheet' says that we have
1138 * to write these values in at start of day
1139 */
1140 EFAB_POPULATE_DWORD_1 ( reg, EF1_CAM_WTF_DOES_THIS_DO, 0x6 );
1141 ef1002_writel ( efab, &reg, EF1_CAM_BASE + 0x20018 );
1142 udelay ( 1000 );
1143 EFAB_POPULATE_DWORD_1 ( reg, EF1_CAM_WTF_DOES_THIS_DO, 0x01000000 );
1144 ef1002_writel ( efab, &reg, EF1_CAM_BASE + 0x00018 );
1145 udelay ( 1000 );
1146
1147 /* General control register 0 */
1148 ef1002_readl ( efab, &reg, EF1_CTR_GEN_STATUS0_REG );
1149 EFAB_SET_DWORD_FIELD ( reg, EF1_MASTER_EVENTS, 0 );
1150 EFAB_SET_DWORD_FIELD ( reg, EF1_TX_ENGINE_EN, 0 );
1151 EFAB_SET_DWORD_FIELD ( reg, EF1_RX_ENGINE_EN, 0 );
1152 EFAB_SET_DWORD_FIELD ( reg, EF1_TURBO2, 1 );
1153 EFAB_SET_DWORD_FIELD ( reg, EF1_TURBO1, 1 );
1154 EFAB_SET_DWORD_FIELD ( reg, EF1_TURBO3, 1 );
1155 EFAB_SET_DWORD_FIELD ( reg, EF1_CAM_ENABLE, 1 );
1156 ef1002_writel ( efab, &reg, EF1_CTR_GEN_STATUS0_REG );
1157 udelay ( 1000 );
1158
1159 /* General control register 2 */
1160 ef1002_readl ( efab, &reg, EF1_CTL2_REG );
1161 EFAB_SET_DWORD_FIELD ( reg, EF1_PLL_TRAP, 1 );
1162 EFAB_SET_DWORD_FIELD ( reg, EF1_MEM_MAP_4MB, 0 );
1163 EFAB_SET_DWORD_FIELD ( reg, EF1_EV_INTR_CLR_WRITE, 0 );
1164 EFAB_SET_DWORD_FIELD ( reg, EF1_BURST_MERGE, 0 );
1165 EFAB_SET_DWORD_FIELD ( reg, EF1_CLEAR_NULL_PAD, 1 );
1166 EFAB_SET_DWORD_FIELD ( reg, EF1_INTR_AFTER_EVENT, 1 );
1167 ef1002_writel ( efab, &reg, EF1_CTL2_REG );
1168 udelay ( 1000 );
1169
1170 /* Enable RX DMA */
1171 ef1002_readl ( efab, &reg, EF1_DMA_RX_CSR_REG );
1172 EFAB_SET_DWORD_FIELD ( reg, EF1_DMA_RX_CSR_ENABLE, 1 );
1173 EFAB_SET_DWORD_FIELD ( reg, EF1_DMA_RX_BELOW_1MB_EN, 1 );
1174 EFAB_SET_DWORD_FIELD ( reg, EF1_DMA_RX_ABOVE_1GB_EN, 1 );
1175 ef1002_writel ( efab, &reg, EF1_DMA_RX_CSR_REG );
1176 udelay ( 1000 );
1177
1178 /* Enable TX DMA */
1179 ef1002_readl ( efab, &reg, EF1_DMA_TX_CSR_REG );
1180 EFAB_SET_DWORD_FIELD ( reg, EF1_DMA_TX_CSR_CHAIN_EN, 1 );
1181 EFAB_SET_DWORD_FIELD ( reg, EF1_DMA_TX_CSR_ENABLE, 0 /* ?? */ );
1182 EFAB_SET_DWORD_FIELD ( reg, EF1_DMA_TX_CSR_INT_EN, 0 /* ?? */ );
1183 ef1002_writel ( efab, &reg, EF1_DMA_TX_CSR_REG );
1184 udelay ( 1000 );
1185
1186 /* Disconnect the JTAG chain. Read-modify-write is impossible
1187 * on the I2C control bits, since reading gives the state of
1188 * the line inputs rather than the last written state.
1189 */
1190 ef1002_readl ( efab, &reg, EF1_EEPROM_REG );
1191 EFAB_SET_DWORD_FIELD ( reg, EF1_EEPROM_SDA, 1 );
1192 EFAB_SET_DWORD_FIELD ( reg, EF1_EEPROM_SCL, 1 );
1193 EFAB_SET_DWORD_FIELD ( reg, EF1_JTAG_DISCONNECT, 1 );
1194 ef1002_writel ( efab, &reg, EF1_EEPROM_REG );
1195 udelay ( 10 );
1196
1197 /* Flush descriptor queues */
1198 EFAB_ZERO_DWORD ( reg );
1199 ef1002_writel ( efab, &reg, EF1_RX_DESC_FIFO_FLUSH );
1200 ef1002_writel ( efab, &reg, EF1_TX_DESC_FIFO_FLUSH );
1201 wmb();
1202 udelay ( 10000 );
1203
1204 /* Reset MAC */
1205 efab->mac_op->reset ( efab );
1206
1207 /* Attach I2C bus */
1208 ef1002_init_eeprom ( efab );
1209
1210 return 1;
1211 }
1212
1213 /**
1214 * Read MAC address from EEPROM
1215 *
1216 */
1217 static int ef1002_read_eeprom ( struct efab_nic *efab ) {
1218 struct i2c_interface *i2c = &efab->ef1002_i2c.i2c;
1219 struct i2c_device *i2cdev = &efab->ef1002_eeprom;
1220
1221 if ( i2c->read ( i2c, i2cdev, EF1_EEPROM_HWADDR_OFFSET,
1222 efab->mac_addr, sizeof ( efab->mac_addr ) ) != 0 )
1223 return 0;
1224
1225 efab->mac_addr[ETH_ALEN-1] += efab->port;
1226
1227 return 1;
1228 }
1229
1230 /** RX descriptor */
1231 typedef efab_qword_t ef1002_rx_desc_t;
1232
1233 /**
1234 * Build RX descriptor
1235 *
1236 */
1237 static void ef1002_build_rx_desc ( struct efab_nic *efab,
1238 struct efab_rx_buf *rx_buf ) {
1239 ef1002_rx_desc_t rxd;
1240
1241 EFAB_POPULATE_QWORD_3 ( rxd,
1242 EF1_RX_KER_EVQ, 0,
1243 EF1_RX_KER_IDX, rx_buf->id,
1244 EF1_RX_KER_BUF_ADR,
1245 virt_to_bus ( rx_buf->addr ) );
1246 ef1002_writel ( efab, &rxd.dword[0], EF1_RX_DESC_FIFO + 0 );
1247 wmb();
1248 ef1002_writel ( efab, &rxd.dword[1], EF1_RX_DESC_FIFO + 4 );
1249 udelay ( 10 );
1250 }
1251
1252 /**
1253 * Update RX descriptor write pointer
1254 *
1255 */
1256 static void ef1002_notify_rx_desc ( struct efab_nic *efab __unused ) {
1257 /* Nothing to do */
1258 }
1259
1260 /** TX descriptor */
1261 typedef efab_oword_t ef1002_tx_desc_t;
1262
1263 /**
1264 * Build TX descriptor
1265 *
1266 */
1267 static void ef1002_build_tx_desc ( struct efab_nic *efab,
1268 struct efab_tx_buf *tx_buf ) {
1269 ef1002_tx_desc_t txd;
1270
1271 EFAB_POPULATE_OWORD_7 ( txd,
1272 EF1_TX_KER_EVQ, 0,
1273 EF1_TX_KER_IDX, tx_buf->id,
1274 EF1_TX_KER_MODE, 0 /* IP mode */,
1275 EF1_TX_KER_PORT, efab->port,
1276 EF1_TX_KER_CONT, 0,
1277 EF1_TX_KER_BYTE_CNT, tx_buf->len,
1278 EF1_TX_KER_BUF_ADR,
1279 virt_to_bus ( tx_buf->addr ) );
1280
1281 ef1002_writel ( efab, &txd.dword[0], EF1_TX_DESC_FIFO + 0 );
1282 ef1002_writel ( efab, &txd.dword[1], EF1_TX_DESC_FIFO + 4 );
1283 wmb();
1284 ef1002_writel ( efab, &txd.dword[2], EF1_TX_DESC_FIFO + 8 );
1285 udelay ( 10 );
1286 }
1287
1288 /**
1289 * Update TX descriptor write pointer
1290 *
1291 */
1292 static void ef1002_notify_tx_desc ( struct efab_nic *efab __unused ) {
1293 /* Nothing to do */
1294 }
1295
1296 /** An event */
1297 typedef efab_qword_t ef1002_event_t;
1298
1299 /**
1300 * Retrieve event from event queue
1301 *
1302 */
1303 static int ef1002_fetch_event ( struct efab_nic *efab,
1304 struct efab_event *event ) {
1305 efab_dword_t reg;
1306 int ev_code;
1307 int words;
1308
1309 /* Check event FIFO depth */
1310 ef1002_readl_silent ( efab, &reg, EF1_EVENT_FIFO_COUNT_REG );
1311 words = EFAB_DWORD_FIELD ( reg, EF1_EV_COUNT );
1312 if ( ! words )
1313 return 0;
1314
1315 /* Read event data */
1316 ef1002_readl ( efab, &reg, EF1_EVENT_FIFO_REG );
1317 DBG ( "Event is " EFAB_DWORD_FMT "\n", EFAB_DWORD_VAL ( reg ) );
1318
1319 /* Decode event */
1320 ev_code = EFAB_DWORD_FIELD ( reg, EF1_EV_CODE );
1321 event->drop = 0;
1322 switch ( ev_code ) {
1323 case EF1_TX_EV_DECODE:
1324 event->type = EFAB_EV_TX;
1325 break;
1326 case EF1_RX_EV_DECODE:
1327 event->type = EFAB_EV_RX;
1328 event->rx_id = EFAB_DWORD_FIELD ( reg, EF1_RX_EV_IDX );
1329 /* RX len not available via event FIFO */
1330 event->rx_len = ETH_FRAME_LEN;
1331 break;
1332 case EF1_TIMER_EV_DECODE:
1333 /* These are safe to ignore. We seem to get some at
1334 * start of day, presumably due to the timers starting
1335 * up with random contents.
1336 */
1337 event->type = EFAB_EV_NONE;
1338 break;
1339 default:
1340 EFAB_ERR ( "Unknown event type %d\n", ev_code );
1341 event->type = EFAB_EV_NONE;
1342 }
1343
1344 /* Clear any pending interrupts */
1345 ef1002_readl ( efab, &reg, EF1_IRQ_SRC_REG );
1346
1347 return 1;
1348 }
1349
1350 /**
1351 * Enable/disable interrupts
1352 *
1353 */
1354 static void ef1002_mask_irq ( struct efab_nic *efab, int enabled ) {
1355 efab_dword_t irq_mask;
1356
1357 EFAB_POPULATE_DWORD_2 ( irq_mask,
1358 EF1_IRQ_SERR, enabled,
1359 EF1_IRQ_EVQ, enabled );
1360 ef1002_writel ( efab, &irq_mask, EF1_IRQ_MASK_REG );
1361 }
1362
1363 /**
1364 * Generate interrupt
1365 *
1366 */
1367 static void ef1002_generate_irq ( struct efab_nic *efab ) {
1368 ef1002_event_t test_event;
1369
1370 EFAB_POPULATE_QWORD_1 ( test_event,
1371 EF1_EV_CODE, EF1_DRV_GEN_EV_DECODE );
1372 ef1002_writel ( efab, &test_event.dword[0], EF1_EVT3_REG );
1373 }
1374
1375 /**
1376 * Write dword to an EF1002 MAC register
1377 *
1378 */
1379 static void ef1002_mac_writel ( struct efab_nic *efab,
1380 efab_dword_t *value, unsigned int mac_reg ) {
1381 ef1002_writel ( efab, value, EF1002_MAC_REG ( efab, mac_reg ) );
1382 }
1383
1384 /**
1385 * Read dword from an EF1002 MAC register
1386 *
1387 */
1388 static void ef1002_mac_readl ( struct efab_nic *efab,
1389 efab_dword_t *value, unsigned int mac_reg ) {
1390 ef1002_readl ( efab, value, EF1002_MAC_REG ( efab, mac_reg ) );
1391 }
1392
1393 /**
1394 * Initialise MAC
1395 *
1396 */
1397 static int ef1002_init_mac ( struct efab_nic *efab ) {
1398 static struct efab_mentormac_parameters ef1002_mentormac_params = {
1399 .gmf_cfgfrth = 0x13,
1400 .gmf_cfgftth = 0x10,
1401 .gmf_cfghwmft = 0x555,
1402 .gmf_cfghwm = 0x2a,
1403 .gmf_cfglwm = 0x15,
1404 };
1405 efab_dword_t reg;
1406 unsigned int mac_clk;
1407
1408 /* Initialise PHY */
1409 alaska_init ( efab );
1410
1411 /* Initialise MAC */
1412 mentormac_init ( efab, &ef1002_mentormac_params );
1413
1414 /* Write Level 5 watermark register */
1415 EFAB_POPULATE_DWORD_1 ( reg, EF1_L5WM, 0x10040000 );
1416 efab->mac_op->mac_writel ( efab, &reg, EF1_GMF_L5WM_REG_MAC );
1417 udelay ( 10 );
1418
1419 /* Set MAC clock speed */
1420 ef1002_readl ( efab, &reg, EF1_GM_MAC_CLK_REG );
1421 mac_clk = ( efab->link_options & LPA_1000 ) ? 0 : 1;
1422 if ( efab->port == 0 ) {
1423 EFAB_SET_DWORD_FIELD ( reg, EF1_GM_PORT0_MAC_CLK, mac_clk );
1424 } else {
1425 EFAB_SET_DWORD_FIELD ( reg, EF1_GM_PORT1_MAC_CLK, mac_clk );
1426 }
1427 ef1002_writel ( efab, &reg, EF1_GM_MAC_CLK_REG );
1428 udelay ( 10 );
1429
1430 return 1;
1431 }
1432
1433 /**
1434 * Reset MAC
1435 *
1436 */
1437 static int ef1002_reset_mac ( struct efab_nic *efab ) {
1438 mentormac_reset ( efab );
1439 return 1;
1440 }
1441
1442 /** MDIO write */
1443 static void ef1002_mdio_write ( struct efab_nic *efab, int location,
1444 int value ) {
1445 mentormac_mdio_write ( efab, efab->port + 2, location, value );
1446 }
1447
1448 /** MDIO read */
1449 static int ef1002_mdio_read ( struct efab_nic *efab, int location ) {
1450 return mentormac_mdio_read ( efab, efab->port + 2, location );
1451 }
1452
1453 static struct efab_operations ef1002_operations = {
1454 .get_membase = ef1002_get_membase,
1455 .reset = ef1002_reset,
1456 .init_nic = ef1002_init_nic,
1457 .read_eeprom = ef1002_read_eeprom,
1458 .build_rx_desc = ef1002_build_rx_desc,
1459 .notify_rx_desc = ef1002_notify_rx_desc,
1460 .build_tx_desc = ef1002_build_tx_desc,
1461 .notify_tx_desc = ef1002_notify_tx_desc,
1462 .fetch_event = ef1002_fetch_event,
1463 .mask_irq = ef1002_mask_irq,
1464 .generate_irq = ef1002_generate_irq,
1465 .mdio_write = ef1002_mdio_write,
1466 .mdio_read = ef1002_mdio_read,
1467 };
1468
1469 static struct efab_mac_operations ef1002_mac_operations = {
1470 .mac_writel = ef1002_mac_writel,
1471 .mac_readl = ef1002_mac_readl,
1472 .init = ef1002_init_mac,
1473 .reset = ef1002_reset_mac,
1474 };
1475
1476 /**************************************************************************
1477 *
1478 * Falcon routines
1479 *
1480 **************************************************************************
1481 */
1482
1483 /* I/O BAR address register */
1484 #define FCN_IOM_IND_ADR_REG 0x0
1485
1486 /* I/O BAR data register */
1487 #define FCN_IOM_IND_DAT_REG 0x4
1488
1489 /* Interrupt enable register */
1490 #define FCN_INT_EN_REG_KER 0x0010
1491 #define FCN_MEM_PERR_INT_EN_KER_LBN 5
1492 #define FCN_MEM_PERR_INT_EN_KER_WIDTH 1
1493 #define FCN_KER_INT_CHAR_LBN 4
1494 #define FCN_KER_INT_CHAR_WIDTH 1
1495 #define FCN_KER_INT_KER_LBN 3
1496 #define FCN_KER_INT_KER_WIDTH 1
1497 #define FCN_ILL_ADR_ERR_INT_EN_KER_LBN 2
1498 #define FCN_ILL_ADR_ERR_INT_EN_KER_WIDTH 1
1499 #define FCN_SRM_PERR_INT_EN_KER_LBN 1
1500 #define FCN_SRM_PERR_INT_EN_KER_WIDTH 1
1501 #define FCN_DRV_INT_EN_KER_LBN 0
1502 #define FCN_DRV_INT_EN_KER_WIDTH 1
1503
1504 /* Interrupt status register */
1505 #define FCN_INT_ADR_REG_KER 0x0030
1506 #define FCN_INT_ADR_KER_LBN 0
1507 #define FCN_INT_ADR_KER_WIDTH EFAB_DMA_TYPE_WIDTH ( 64 )
1508
1509 /* Interrupt acknowledge register */
1510 #define FCN_INT_ACK_KER_REG 0x0050
1511
1512 /* SPI host command register */
1513 #define FCN_EE_SPI_HCMD_REG_KER 0x0100
1514 #define FCN_EE_SPI_HCMD_CMD_EN_LBN 31
1515 #define FCN_EE_SPI_HCMD_CMD_EN_WIDTH 1
1516 #define FCN_EE_WR_TIMER_ACTIVE_LBN 28
1517 #define FCN_EE_WR_TIMER_ACTIVE_WIDTH 1
1518 #define FCN_EE_SPI_HCMD_SF_SEL_LBN 24
1519 #define FCN_EE_SPI_HCMD_SF_SEL_WIDTH 1
1520 #define FCN_EE_SPI_EEPROM 0
1521 #define FCN_EE_SPI_FLASH 1
1522 #define FCN_EE_SPI_HCMD_DABCNT_LBN 16
1523 #define FCN_EE_SPI_HCMD_DABCNT_WIDTH 5
1524 #define FCN_EE_SPI_HCMD_READ_LBN 15
1525 #define FCN_EE_SPI_HCMD_READ_WIDTH 1
1526 #define FCN_EE_SPI_READ 1
1527 #define FCN_EE_SPI_WRITE 0
1528 #define FCN_EE_SPI_HCMD_DUBCNT_LBN 12
1529 #define FCN_EE_SPI_HCMD_DUBCNT_WIDTH 2
1530 #define FCN_EE_SPI_HCMD_ADBCNT_LBN 8
1531 #define FCN_EE_SPI_HCMD_ADBCNT_WIDTH 2
1532 #define FCN_EE_SPI_HCMD_ENC_LBN 0
1533 #define FCN_EE_SPI_HCMD_ENC_WIDTH 8
1534
1535 /* SPI host address register */
1536 #define FCN_EE_SPI_HADR_REG_KER 0x0110
1537 #define FCN_EE_SPI_HADR_DUBYTE_LBN 24
1538 #define FCN_EE_SPI_HADR_DUBYTE_WIDTH 8
1539 #define FCN_EE_SPI_HADR_ADR_LBN 0
1540 #define FCN_EE_SPI_HADR_ADR_WIDTH 24
1541
1542 /* SPI host data register */
1543 #define FCN_EE_SPI_HDATA_REG_KER 0x0120
1544 #define FCN_EE_SPI_HDATA3_LBN 96
1545 #define FCN_EE_SPI_HDATA3_WIDTH 32
1546 #define FCN_EE_SPI_HDATA2_LBN 64
1547 #define FCN_EE_SPI_HDATA2_WIDTH 32
1548 #define FCN_EE_SPI_HDATA1_LBN 32
1549 #define FCN_EE_SPI_HDATA1_WIDTH 32
1550 #define FCN_EE_SPI_HDATA0_LBN 0
1551 #define FCN_EE_SPI_HDATA0_WIDTH 32
1552
1553 /* VPI configuration register */
1554 #define FCN_VPD_CONFIG_REG_KER 0x0140
1555 #define FCN_VPD_9BIT_LBN 1
1556 #define FCN_VPD_9BIT_WIDTH 1
1557
1558 /* NIC status register */
1559 #define FCN_NIC_STAT_REG 0x0200
1560 #define ONCHIP_SRAM_LBN 16
1561 #define ONCHIP_SRAM_WIDTH 1
1562 #define SF_PRST_LBN 9
1563 #define SF_PRST_WIDTH 1
1564 #define EE_PRST_LBN 8
1565 #define EE_PRST_WIDTH 1
1566 #define EE_STRAP_LBN 7
1567 #define EE_STRAP_WIDTH 1
1568 #define PCI_PCIX_MODE_LBN 4
1569 #define PCI_PCIX_MODE_WIDTH 3
1570 #define PCI_PCIX_MODE_PCI33_DECODE 0
1571 #define PCI_PCIX_MODE_PCI66_DECODE 1
1572 #define PCI_PCIX_MODE_PCIX66_DECODE 5
1573 #define PCI_PCIX_MODE_PCIX100_DECODE 6
1574 #define PCI_PCIX_MODE_PCIX133_DECODE 7
1575 #define STRAP_ISCSI_EN_LBN 3
1576 #define STRAP_ISCSI_EN_WIDTH 1
1577 #define STRAP_PINS_LBN 0
1578 #define STRAP_PINS_WIDTH 3
1579 /* These bit definitions are extrapolated from the list of numerical
1580 * values for STRAP_PINS. If you want a laugh, read the datasheet's
1581 * definition for when bits 2:0 are set to 7.
1582 */
1583 #define STRAP_10G_LBN 2
1584 #define STRAP_10G_WIDTH 1
1585 #define STRAP_DUAL_PORT_LBN 1
1586 #define STRAP_DUAL_PORT_WIDTH 1
1587 #define STRAP_PCIE_LBN 0
1588 #define STRAP_PCIE_WIDTH 1
1589
1590 /* GPIO control register */
1591 #define FCN_GPIO_CTL_REG_KER 0x0210
1592 #define FCN_FLASH_PRESENT_LBN 7
1593 #define FCN_FLASH_PRESENT_WIDTH 1
1594 #define FCN_EEPROM_PRESENT_LBN 6
1595 #define FCN_EEPROM_PRESENT_WIDTH 1
1596
1597 /* Global control register */
1598 #define FCN_GLB_CTL_REG_KER 0x0220
1599 #define EXT_PHY_RST_CTL_LBN 63
1600 #define EXT_PHY_RST_CTL_WIDTH 1
1601 #define PCIE_SD_RST_CTL_LBN 61
1602 #define PCIE_SD_RST_CTL_WIDTH 1
1603 #define PCIX_RST_CTL_LBN 60
1604 #define PCIX_RST_CTL_WIDTH 1
1605 #define PCIE_STCK_RST_CTL_LBN 59
1606 #define PCIE_STCK_RST_CTL_WIDTH 1
1607 #define PCIE_NSTCK_RST_CTL_LBN 58
1608 #define PCIE_NSTCK_RST_CTL_WIDTH 1
1609 #define PCIE_CORE_RST_CTL_LBN 57
1610 #define PCIE_CORE_RST_CTL_WIDTH 1
1611 #define EE_RST_CTL_LBN 49
1612 #define EE_RST_CTL_WIDTH 1
1613 #define CS_RST_CTL_LBN 48
1614 #define CS_RST_CTL_WIDTH 1
1615 #define RST_EXT_PHY_LBN 31
1616 #define RST_EXT_PHY_WIDTH 1
1617 #define INT_RST_DUR_LBN 4
1618 #define INT_RST_DUR_WIDTH 3
1619 #define EXT_PHY_RST_DUR_LBN 1
1620 #define EXT_PHY_RST_DUR_WIDTH 3
1621 #define SWRST_LBN 0
1622 #define SWRST_WIDTH 1
1623 #define INCLUDE_IN_RESET 0
1624 #define EXCLUDE_FROM_RESET 1
1625
1626 /* FPGA build version */
1627 #define ALTERA_BUILD_REG_KER 0x0300
1628 #define VER_MAJOR_LBN 24
1629 #define VER_MAJOR_WIDTH 8
1630 #define VER_MINOR_LBN 16
1631 #define VER_MINOR_WIDTH 8
1632 #define VER_BUILD_LBN 0
1633 #define VER_BUILD_WIDTH 16
1634 #define VER_ALL_LBN 0
1635 #define VER_ALL_WIDTH 32
1636
1637 /* Timer table for kernel access */
1638 #define FCN_TIMER_CMD_REG_KER 0x420
1639 #define FCN_TIMER_MODE_LBN 12
1640 #define FCN_TIMER_MODE_WIDTH 2
1641 #define FCN_TIMER_MODE_DIS 0
1642 #define FCN_TIMER_MODE_INT_HLDOFF 1
1643 #define FCN_TIMER_VAL_LBN 0
1644 #define FCN_TIMER_VAL_WIDTH 12
1645
1646 /* Receive configuration register */
1647 #define FCN_RX_CFG_REG_KER 0x800
1648 #define FCN_RX_XOFF_EN_LBN 0
1649 #define FCN_RX_XOFF_EN_WIDTH 1
1650
1651 /* SRAM receive descriptor cache configuration register */
1652 #define FCN_SRM_RX_DC_CFG_REG_KER 0x610
1653 #define FCN_SRM_RX_DC_BASE_ADR_LBN 0
1654 #define FCN_SRM_RX_DC_BASE_ADR_WIDTH 21
1655
1656 /* SRAM transmit descriptor cache configuration register */
1657 #define FCN_SRM_TX_DC_CFG_REG_KER 0x620
1658 #define FCN_SRM_TX_DC_BASE_ADR_LBN 0
1659 #define FCN_SRM_TX_DC_BASE_ADR_WIDTH 21
1660
1661 /* Receive filter control register */
1662 #define FCN_RX_FILTER_CTL_REG_KER 0x810
1663 #define FCN_NUM_KER_LBN 24
1664 #define FCN_NUM_KER_WIDTH 2
1665
1666 /* Receive descriptor update register */
1667 #define FCN_RX_DESC_UPD_REG_KER 0x0830
1668 #define FCN_RX_DESC_WPTR_LBN 96
1669 #define FCN_RX_DESC_WPTR_WIDTH 12
1670 #define FCN_RX_DESC_UPD_REG_KER_DWORD ( FCN_RX_DESC_UPD_REG_KER + 12 )
1671 #define FCN_RX_DESC_WPTR_DWORD_LBN 0
1672 #define FCN_RX_DESC_WPTR_DWORD_WIDTH 12
1673
1674 /* Receive descriptor cache configuration register */
1675 #define FCN_RX_DC_CFG_REG_KER 0x840
1676 #define FCN_RX_DC_SIZE_LBN 0
1677 #define FCN_RX_DC_SIZE_WIDTH 2
1678
1679 /* Transmit descriptor update register */
1680 #define FCN_TX_DESC_UPD_REG_KER 0x0a10
1681 #define FCN_TX_DESC_WPTR_LBN 96
1682 #define FCN_TX_DESC_WPTR_WIDTH 12
1683 #define FCN_TX_DESC_UPD_REG_KER_DWORD ( FCN_TX_DESC_UPD_REG_KER + 12 )
1684 #define FCN_TX_DESC_WPTR_DWORD_LBN 0
1685 #define FCN_TX_DESC_WPTR_DWORD_WIDTH 12
1686
1687 /* Transmit descriptor cache configuration register */
1688 #define FCN_TX_DC_CFG_REG_KER 0xa20
1689 #define FCN_TX_DC_SIZE_LBN 0
1690 #define FCN_TX_DC_SIZE_WIDTH 2
1691
1692 /* PHY management transmit data register */
1693 #define FCN_MD_TXD_REG_KER 0xc00
1694 #define FCN_MD_TXD_LBN 0
1695 #define FCN_MD_TXD_WIDTH 16
1696
1697 /* PHY management receive data register */
1698 #define FCN_MD_RXD_REG_KER 0xc10
1699 #define FCN_MD_RXD_LBN 0
1700 #define FCN_MD_RXD_WIDTH 16
1701
1702 /* PHY management configuration & status register */
1703 #define FCN_MD_CS_REG_KER 0xc20
1704 #define FCN_MD_GC_LBN 4
1705 #define FCN_MD_GC_WIDTH 1
1706 #define FCN_MD_RIC_LBN 2
1707 #define FCN_MD_RIC_WIDTH 1
1708 #define FCN_MD_WRC_LBN 0
1709 #define FCN_MD_WRC_WIDTH 1
1710
1711 /* PHY management PHY address register */
1712 #define FCN_MD_PHY_ADR_REG_KER 0xc30
1713 #define FCN_MD_PHY_ADR_LBN 0
1714 #define FCN_MD_PHY_ADR_WIDTH 16
1715
1716 /* PHY management ID register */
1717 #define FCN_MD_ID_REG_KER 0xc40
1718 #define FCN_MD_PRT_ADR_LBN 11
1719 #define FCN_MD_PRT_ADR_WIDTH 5
1720 #define FCN_MD_DEV_ADR_LBN 6
1721 #define FCN_MD_DEV_ADR_WIDTH 5
1722
1723 /* PHY management status & mask register */
1724 #define FCN_MD_STAT_REG_KER 0xc50
1725 #define FCN_MD_BSY_LBN 0
1726 #define FCN_MD_BSY_WIDTH 1
1727
1728 /* Port 0 and 1 MAC control registers */
1729 #define FCN_MAC0_CTRL_REG_KER 0xc80
1730 #define FCN_MAC1_CTRL_REG_KER 0xc90
1731 #define FCN_MAC_XOFF_VAL_LBN 16
1732 #define FCN_MAC_XOFF_VAL_WIDTH 16
1733 #define FCN_MAC_BCAD_ACPT_LBN 4
1734 #define FCN_MAC_BCAD_ACPT_WIDTH 1
1735 #define FCN_MAC_UC_PROM_LBN 3
1736 #define FCN_MAC_UC_PROM_WIDTH 1
1737 #define FCN_MAC_LINK_STATUS_LBN 2
1738 #define FCN_MAC_LINK_STATUS_WIDTH 1
1739 #define FCN_MAC_SPEED_LBN 0
1740 #define FCN_MAC_SPEED_WIDTH 2
1741
1742 /* GMAC registers */
1743 #define FALCON_GMAC_REGBANK 0xe00
1744 #define FALCON_GMAC_REGBANK_SIZE 0x200
1745 #define FALCON_GMAC_REG_SIZE 0x10
1746
1747 /* XGMAC registers */
1748 #define FALCON_XMAC_REGBANK 0x1200
1749 #define FALCON_XMAC_REGBANK_SIZE 0x200
1750 #define FALCON_XMAC_REG_SIZE 0x10
1751
1752 /* XGMAC address register low */
1753 #define FCN_XM_ADR_LO_REG_MAC 0x00
1754 #define FCN_XM_ADR_3_LBN 24
1755 #define FCN_XM_ADR_3_WIDTH 8
1756 #define FCN_XM_ADR_2_LBN 16
1757 #define FCN_XM_ADR_2_WIDTH 8
1758 #define FCN_XM_ADR_1_LBN 8
1759 #define FCN_XM_ADR_1_WIDTH 8
1760 #define FCN_XM_ADR_0_LBN 0
1761 #define FCN_XM_ADR_0_WIDTH 8
1762
1763 /* XGMAC address register high */
1764 #define FCN_XM_ADR_HI_REG_MAC 0x01
1765 #define FCN_XM_ADR_5_LBN 8
1766 #define FCN_XM_ADR_5_WIDTH 8
1767 #define FCN_XM_ADR_4_LBN 0
1768 #define FCN_XM_ADR_4_WIDTH 8
1769
1770 /* XGMAC global configuration - port 0*/
1771 #define FCN_XM_GLB_CFG_REG_MAC 0x02
1772 #define FCN_XM_RX_STAT_EN_LBN 11
1773 #define FCN_XM_RX_STAT_EN_WIDTH 1
1774 #define FCN_XM_TX_STAT_EN_LBN 10
1775 #define FCN_XM_TX_STAT_EN_WIDTH 1
1776 #define FCN_XM_RX_JUMBO_MODE_LBN 6
1777 #define FCN_XM_RX_JUMBO_MODE_WIDTH 1
1778 #define FCN_XM_CORE_RST_LBN 0
1779 #define FCN_XM_CORE_RST_WIDTH 1
1780
1781 /* XGMAC transmit configuration - port 0 */
1782 #define FCN_XM_TX_CFG_REG_MAC 0x03
1783 #define FCN_XM_IPG_LBN 16
1784 #define FCN_XM_IPG_WIDTH 4
1785 #define FCN_XM_FCNTL_LBN 10
1786 #define FCN_XM_FCNTL_WIDTH 1
1787 #define FCN_XM_TXCRC_LBN 8
1788 #define FCN_XM_TXCRC_WIDTH 1
1789 #define FCN_XM_AUTO_PAD_LBN 5
1790 #define FCN_XM_AUTO_PAD_WIDTH 1
1791 #define FCN_XM_TX_PRMBL_LBN 2
1792 #define FCN_XM_TX_PRMBL_WIDTH 1
1793 #define FCN_XM_TXEN_LBN 1
1794 #define FCN_XM_TXEN_WIDTH 1
1795
1796 /* XGMAC receive configuration - port 0 */
1797 #define FCN_XM_RX_CFG_REG_MAC 0x04
1798 #define FCN_XM_PASS_CRC_ERR_LBN 25
1799 #define FCN_XM_PASS_CRC_ERR_WIDTH 1
1800 #define FCN_XM_AUTO_DEPAD_LBN 8
1801 #define FCN_XM_AUTO_DEPAD_WIDTH 1
1802 #define FCN_XM_RXEN_LBN 1
1803 #define FCN_XM_RXEN_WIDTH 1
1804
1805 /* XGMAC transmit parameter register */
1806 #define FCN_XM_TX_PARAM_REG_MAC 0x0d
1807 #define FCN_XM_TX_JUMBO_MODE_LBN 31
1808 #define FCN_XM_TX_JUMBO_MODE_WIDTH 1
1809 #define FCN_XM_MAX_TX_FRM_SIZE_LBN 16
1810 #define FCN_XM_MAX_TX_FRM_SIZE_WIDTH 14
1811
1812 /* XGMAC receive parameter register */
1813 #define FCN_XM_RX_PARAM_REG_MAC 0x0e
1814 #define FCN_XM_MAX_RX_FRM_SIZE_LBN 0
1815 #define FCN_XM_MAX_RX_FRM_SIZE_WIDTH 14
1816
1817 /* XAUI XGXS core status register */
1818 #define FCN_XX_ALIGN_DONE_LBN 20
1819 #define FCN_XX_ALIGN_DONE_WIDTH 1
1820 #define FCN_XX_CORE_STAT_REG_MAC 0x16
1821 #define FCN_XX_SYNC_STAT_LBN 16
1822 #define FCN_XX_SYNC_STAT_WIDTH 4
1823 #define FCN_XX_SYNC_STAT_DECODE_SYNCED 0xf
1824 #define FCN_XX_COMMA_DET_LBN 12
1825 #define FCN_XX_COMMA_DET_WIDTH 4
1826 #define FCN_XX_COMMA_DET_RESET 0xf
1827
1828
1829 /* XGXS/XAUI powerdown/reset register */
1830 #define FCN_XX_PWR_RST_REG_MAC 0x10
1831 #define FCN_XX_RSTXGXSRX_EN_LBN 2
1832 #define FCN_XX_RSTXGXSRX_EN_WIDTH 1
1833 #define FCN_XX_RSTXGXSTX_EN_LBN 1
1834 #define FCN_XX_RSTXGXSTX_EN_WIDTH 1
1835 #define FCN_XX_RST_XX_EN_LBN 0
1836 #define FCN_XX_RST_XX_EN_WIDTH 1
1837
1838 /* Receive descriptor pointer table */
1839 #define FCN_RX_DESC_PTR_TBL_KER 0x11800
1840 #define FCN_RX_DESCQ_BUF_BASE_ID_LBN 36
1841 #define FCN_RX_DESCQ_BUF_BASE_ID_WIDTH 20
1842 #define FCN_RX_DESCQ_EVQ_ID_LBN 24
1843 #define FCN_RX_DESCQ_EVQ_ID_WIDTH 12
1844 #define FCN_RX_DESCQ_OWNER_ID_LBN 10
1845 #define FCN_RX_DESCQ_OWNER_ID_WIDTH 14
1846 #define FCN_RX_DESCQ_SIZE_LBN 3
1847 #define FCN_RX_DESCQ_SIZE_WIDTH 2
1848 #define FCN_RX_DESCQ_SIZE_4K 3
1849 #define FCN_RX_DESCQ_SIZE_2K 2
1850 #define FCN_RX_DESCQ_SIZE_1K 1
1851 #define FCN_RX_DESCQ_SIZE_512 0
1852 #define FCN_RX_DESCQ_TYPE_LBN 2
1853 #define FCN_RX_DESCQ_TYPE_WIDTH 1
1854 #define FCN_RX_DESCQ_JUMBO_LBN 1
1855 #define FCN_RX_DESCQ_JUMBO_WIDTH 1
1856 #define FCN_RX_DESCQ_EN_LBN 0
1857 #define FCN_RX_DESCQ_EN_WIDTH 1
1858
1859 /* Transmit descriptor pointer table */
1860 #define FCN_TX_DESC_PTR_TBL_KER 0x11900
1861 #define FCN_TX_DESCQ_EN_LBN 88
1862 #define FCN_TX_DESCQ_EN_WIDTH 1
1863 #define FCN_TX_DESCQ_BUF_BASE_ID_LBN 36
1864 #define FCN_TX_DESCQ_BUF_BASE_ID_WIDTH 20
1865 #define FCN_TX_DESCQ_EVQ_ID_LBN 24
1866 #define FCN_TX_DESCQ_EVQ_ID_WIDTH 12
1867 #define FCN_TX_DESCQ_OWNER_ID_LBN 10
1868 #define FCN_TX_DESCQ_OWNER_ID_WIDTH 14
1869 #define FCN_TX_DESCQ_SIZE_LBN 3
1870 #define FCN_TX_DESCQ_SIZE_WIDTH 2
1871 #define FCN_TX_DESCQ_SIZE_4K 3
1872 #define FCN_TX_DESCQ_SIZE_2K 2
1873 #define FCN_TX_DESCQ_SIZE_1K 1
1874 #define FCN_TX_DESCQ_SIZE_512 0
1875 #define FCN_TX_DESCQ_TYPE_LBN 1
1876 #define FCN_TX_DESCQ_TYPE_WIDTH 2
1877 #define FCN_TX_DESCQ_FLUSH_LBN 0
1878 #define FCN_TX_DESCQ_FLUSH_WIDTH 1
1879
1880 /* Event queue pointer */
1881 #define FCN_EVQ_PTR_TBL_KER 0x11a00
1882 #define FCN_EVQ_EN_LBN 23
1883 #define FCN_EVQ_EN_WIDTH 1
1884 #define FCN_EVQ_SIZE_LBN 20
1885 #define FCN_EVQ_SIZE_WIDTH 3
1886 #define FCN_EVQ_SIZE_32K 6
1887 #define FCN_EVQ_SIZE_16K 5
1888 #define FCN_EVQ_SIZE_8K 4
1889 #define FCN_EVQ_SIZE_4K 3
1890 #define FCN_EVQ_SIZE_2K 2
1891 #define FCN_EVQ_SIZE_1K 1
1892 #define FCN_EVQ_SIZE_512 0
1893 #define FCN_EVQ_BUF_BASE_ID_LBN 0
1894 #define FCN_EVQ_BUF_BASE_ID_WIDTH 20
1895
1896 /* Event queue read pointer */
1897 #define FCN_EVQ_RPTR_REG_KER 0x11b00
1898 #define FCN_EVQ_RPTR_LBN 0
1899 #define FCN_EVQ_RPTR_WIDTH 14
1900 #define FCN_EVQ_RPTR_REG_KER_DWORD ( FCN_EVQ_RPTR_REG_KER + 0 )
1901 #define FCN_EVQ_RPTR_DWORD_LBN 0
1902 #define FCN_EVQ_RPTR_DWORD_WIDTH 14
1903
1904 /* Special buffer descriptors */
1905 #define FCN_BUF_FULL_TBL_KER 0x18000
1906 #define FCN_IP_DAT_BUF_SIZE_LBN 50
1907 #define FCN_IP_DAT_BUF_SIZE_WIDTH 1
1908 #define FCN_IP_DAT_BUF_SIZE_8K 1
1909 #define FCN_IP_DAT_BUF_SIZE_4K 0
1910 #define FCN_BUF_ADR_FBUF_LBN 14
1911 #define FCN_BUF_ADR_FBUF_WIDTH 34
1912 #define FCN_BUF_OWNER_ID_FBUF_LBN 0
1913 #define FCN_BUF_OWNER_ID_FBUF_WIDTH 14
1914
1915 /** Offset of a GMAC register within Falcon */
1916 #define FALCON_GMAC_REG( efab, mac_reg ) \
1917 ( FALCON_GMAC_REGBANK + \
1918 ( (efab)->port * FALCON_GMAC_REGBANK_SIZE ) + \
1919 ( (mac_reg) * FALCON_GMAC_REG_SIZE ) )
1920
1921 /** Offset of an XMAC register within Falcon */
1922 #define FALCON_XMAC_REG( efab_port, mac_reg ) \
1923 ( FALCON_XMAC_REGBANK + \
1924 ( (efab_port)->port * FALCON_XMAC_REGBANK_SIZE ) + \
1925 ( (mac_reg) * FALCON_XMAC_REG_SIZE ) )
1926
1927 #define FCN_MAC_DATA_LBN 0
1928 #define FCN_MAC_DATA_WIDTH 32
1929
1930 /* Transmit descriptor */
1931 #define FCN_TX_KER_PORT_LBN 63
1932 #define FCN_TX_KER_PORT_WIDTH 1
1933 #define FCN_TX_KER_BYTE_CNT_LBN 48
1934 #define FCN_TX_KER_BYTE_CNT_WIDTH 14
1935 #define FCN_TX_KER_BUF_ADR_LBN 0
1936 #define FCN_TX_KER_BUF_ADR_WIDTH EFAB_DMA_TYPE_WIDTH ( 46 )
1937
1938
1939 /* Receive descriptor */
1940 #define FCN_RX_KER_BUF_SIZE_LBN 48
1941 #define FCN_RX_KER_BUF_SIZE_WIDTH 14
1942 #define FCN_RX_KER_BUF_ADR_LBN 0
1943 #define FCN_RX_KER_BUF_ADR_WIDTH EFAB_DMA_TYPE_WIDTH ( 46 )
1944
1945 /* Event queue entries */
1946 #define FCN_EV_CODE_LBN 60
1947 #define FCN_EV_CODE_WIDTH 4
1948 #define FCN_RX_IP_EV_DECODE 0
1949 #define FCN_TX_IP_EV_DECODE 2
1950 #define FCN_DRIVER_EV_DECODE 5
1951
1952 /* Receive events */
1953 #define FCN_RX_EV_PKT_OK_LBN 56
1954 #define FCN_RX_EV_PKT_OK_WIDTH 1
1955 #define FCN_RX_PORT_LBN 30
1956 #define FCN_RX_PORT_WIDTH 1
1957 #define FCN_RX_EV_BYTE_CNT_LBN 16
1958 #define FCN_RX_EV_BYTE_CNT_WIDTH 14
1959 #define FCN_RX_EV_DESC_PTR_LBN 0
1960 #define FCN_RX_EV_DESC_PTR_WIDTH 12
1961
1962 /* Transmit events */
1963 #define FCN_TX_EV_DESC_PTR_LBN 0
1964 #define FCN_TX_EV_DESC_PTR_WIDTH 12
1965
1966 /* Fixed special buffer numbers to use */
1967 #define FALCON_EVQ_ID 0
1968 #define FALCON_TXD_ID 1
1969 #define FALCON_RXD_ID 2
1970
1971 #if FALCON_USE_IO_BAR
1972
1973 /* Write dword via the I/O BAR */
1974 static inline void _falcon_writel ( struct efab_nic *efab, uint32_t value,
1975 unsigned int reg ) {
1976 outl ( reg, efab->iobase + FCN_IOM_IND_ADR_REG );
1977 outl ( value, efab->iobase + FCN_IOM_IND_DAT_REG );
1978 }
1979
1980 /* Read dword via the I/O BAR */
1981 static inline uint32_t _falcon_readl ( struct efab_nic *efab,
1982 unsigned int reg ) {
1983 outl ( reg, efab->iobase + FCN_IOM_IND_ADR_REG );
1984 return inl ( efab->iobase + FCN_IOM_IND_DAT_REG );
1985 }
1986
1987 #else /* FALCON_USE_IO_BAR */
1988
1989 #define _falcon_writel( efab, value, reg ) \
1990 writel ( (value), (efab)->membase + (reg) )
1991 #define _falcon_readl( efab, reg ) readl ( (efab)->membase + (reg) )
1992
1993 #endif /* FALCON_USE_IO_BAR */
1994
1995 /**
1996 * Write to a Falcon register
1997 *
1998 */
1999 static inline void falcon_write ( struct efab_nic *efab, efab_oword_t *value,
2000 unsigned int reg ) {
2001
2002 EFAB_REGDUMP ( "Writing register %x with " EFAB_OWORD_FMT "\n",
2003 reg, EFAB_OWORD_VAL ( *value ) );
2004
2005 _falcon_writel ( efab, value->u32[0], reg + 0 );
2006 _falcon_writel ( efab, value->u32[1], reg + 4 );
2007 _falcon_writel ( efab, value->u32[2], reg + 8 );
2008 _falcon_writel ( efab, value->u32[3], reg + 12 );
2009 wmb();
2010 }
2011
2012 /**
2013 * Write to Falcon SRAM
2014 *
2015 */
2016 static inline void falcon_write_sram ( struct efab_nic *efab,
2017 efab_qword_t *value,
2018 unsigned int index ) {
2019 unsigned int reg = ( FCN_BUF_FULL_TBL_KER +
2020 ( index * sizeof ( *value ) ) );
2021
2022 EFAB_REGDUMP ( "Writing SRAM register %x with " EFAB_QWORD_FMT "\n",
2023 reg, EFAB_QWORD_VAL ( *value ) );
2024
2025 _falcon_writel ( efab, value->u32[0], reg + 0 );
2026 _falcon_writel ( efab, value->u32[1], reg + 4 );
2027 wmb();
2028 }
2029
2030 /**
2031 * Write dword to Falcon register that allows partial writes
2032 *
2033 */
2034 static inline void falcon_writel ( struct efab_nic *efab, efab_dword_t *value,
2035 unsigned int reg ) {
2036 EFAB_REGDUMP ( "Writing partial register %x with " EFAB_DWORD_FMT "\n",
2037 reg, EFAB_DWORD_VAL ( *value ) );
2038 _falcon_writel ( efab, value->u32[0], reg );
2039 }
2040
2041 /**
2042 * Read from a Falcon register
2043 *
2044 */
2045 static inline void falcon_read ( struct efab_nic *efab, efab_oword_t *value,
2046 unsigned int reg ) {
2047 value->u32[0] = _falcon_readl ( efab, reg + 0 );
2048 value->u32[1] = _falcon_readl ( efab, reg + 4 );
2049 value->u32[2] = _falcon_readl ( efab, reg + 8 );
2050 value->u32[3] = _falcon_readl ( efab, reg + 12 );
2051
2052 EFAB_REGDUMP ( "Read from register %x, got " EFAB_OWORD_FMT "\n",
2053 reg, EFAB_OWORD_VAL ( *value ) );
2054 }
2055
2056 /**
2057 * Read from Falcon SRAM
2058 *
2059 */
2060 static inline void falcon_read_sram ( struct efab_nic *efab,
2061 efab_qword_t *value,
2062 unsigned int index ) {
2063 unsigned int reg = ( FCN_BUF_FULL_TBL_KER +
2064 ( index * sizeof ( *value ) ) );
2065
2066 value->u32[0] = _falcon_readl ( efab, reg + 0 );
2067 value->u32[1] = _falcon_readl ( efab, reg + 4 );
2068 EFAB_REGDUMP ( "Read from SRAM register %x, got " EFAB_QWORD_FMT "\n",
2069 reg, EFAB_QWORD_VAL ( *value ) );
2070 }
2071
2072 /**
2073 * Read dword from a portion of a Falcon register
2074 *
2075 */
2076 static inline void falcon_readl ( struct efab_nic *efab, efab_dword_t *value,
2077 unsigned int reg ) {
2078 value->u32[0] = _falcon_readl ( efab, reg );
2079 EFAB_REGDUMP ( "Read from register %x, got " EFAB_DWORD_FMT "\n",
2080 reg, EFAB_DWORD_VAL ( *value ) );
2081 }
2082
2083 /**
2084 * Verified write to Falcon SRAM
2085 *
2086 */
2087 static inline void falcon_write_sram_verify ( struct efab_nic *efab,
2088 efab_qword_t *value,
2089 unsigned int index ) {
2090 efab_qword_t verify;
2091
2092 falcon_write_sram ( efab, value, index );
2093 udelay ( 1000 );
2094 falcon_read_sram ( efab, &verify, index );
2095 if ( memcmp ( &verify, value, sizeof ( verify ) ) != 0 ) {
2096 EFAB_ERR ( "SRAM index %x failure: wrote " EFAB_QWORD_FMT
2097 " got " EFAB_QWORD_FMT "\n", index,
2098 EFAB_QWORD_VAL ( *value ),
2099 EFAB_QWORD_VAL ( verify ) );
2100 }
2101 }
2102
2103 /**
2104 * Get memory base
2105 *
2106 */
2107 static void falcon_get_membase ( struct efab_nic *efab ) {
2108 unsigned long membase_phys;
2109
2110 membase_phys = pci_bar_start ( efab->pci, PCI_BASE_ADDRESS_2 );
2111 efab->membase = ioremap ( membase_phys, 0x20000 );
2112 }
2113
2114 #define FCN_DUMP_REG( efab, _reg ) do { \
2115 efab_oword_t reg; \
2116 falcon_read ( efab, &reg, _reg ); \
2117 EFAB_LOG ( #_reg " = " EFAB_OWORD_FMT "\n", \
2118 EFAB_OWORD_VAL ( reg ) ); \
2119 } while ( 0 );
2120
2121 #define FCN_DUMP_MAC_REG( efab, _mac_reg ) do { \
2122 efab_dword_t reg; \
2123 efab->mac_op->mac_readl ( efab, &reg, _mac_reg ); \
2124 EFAB_LOG ( #_mac_reg " = " EFAB_DWORD_FMT "\n", \
2125 EFAB_DWORD_VAL ( reg ) ); \
2126 } while ( 0 );
2127
2128 /**
2129 * Dump register contents (for debugging)
2130 *
2131 * Marked as static inline so that it will not be compiled in if not
2132 * used.
2133 */
2134 static inline void falcon_dump_regs ( struct efab_nic *efab ) {
2135 FCN_DUMP_REG ( efab, FCN_INT_EN_REG_KER );
2136 FCN_DUMP_REG ( efab, FCN_INT_ADR_REG_KER );
2137 FCN_DUMP_REG ( efab, FCN_GLB_CTL_REG_KER );
2138 FCN_DUMP_REG ( efab, FCN_TIMER_CMD_REG_KER );
2139 FCN_DUMP_REG ( efab, FCN_SRM_RX_DC_CFG_REG_KER );
2140 FCN_DUMP_REG ( efab, FCN_SRM_TX_DC_CFG_REG_KER );
2141 FCN_DUMP_REG ( efab, FCN_RX_FILTER_CTL_REG_KER );
2142 FCN_DUMP_REG ( efab, FCN_RX_DC_CFG_REG_KER );
2143 FCN_DUMP_REG ( efab, FCN_TX_DC_CFG_REG_KER );
2144 FCN_DUMP_REG ( efab, FCN_MAC0_CTRL_REG_KER );
2145 FCN_DUMP_REG ( efab, FCN_MAC1_CTRL_REG_KER );
2146 FCN_DUMP_REG ( efab, FCN_RX_DESC_PTR_TBL_KER );
2147 FCN_DUMP_REG ( efab, FCN_TX_DESC_PTR_TBL_KER );
2148 FCN_DUMP_REG ( efab, FCN_EVQ_PTR_TBL_KER );
2149 FCN_DUMP_MAC_REG ( efab, GM_CFG1_REG_MAC );
2150 FCN_DUMP_MAC_REG ( efab, GM_CFG2_REG_MAC );
2151 FCN_DUMP_MAC_REG ( efab, GM_MAX_FLEN_REG_MAC );
2152 FCN_DUMP_MAC_REG ( efab, GM_MII_MGMT_CFG_REG_MAC );
2153 FCN_DUMP_MAC_REG ( efab, GM_ADR1_REG_MAC );
2154 FCN_DUMP_MAC_REG ( efab, GM_ADR2_REG_MAC );
2155 FCN_DUMP_MAC_REG ( efab, GMF_CFG0_REG_MAC );
2156 FCN_DUMP_MAC_REG ( efab, GMF_CFG1_REG_MAC );
2157 FCN_DUMP_MAC_REG ( efab, GMF_CFG2_REG_MAC );
2158 FCN_DUMP_MAC_REG ( efab, GMF_CFG3_REG_MAC );
2159 FCN_DUMP_MAC_REG ( efab, GMF_CFG4_REG_MAC );
2160 FCN_DUMP_MAC_REG ( efab, GMF_CFG5_REG_MAC );
2161 }
2162
2163 /**
2164 * Create special buffer
2165 *
2166 */
2167 static void falcon_create_special_buffer ( struct efab_nic *efab,
2168 void *addr, unsigned int index ) {
2169 efab_qword_t buf_desc;
2170 unsigned long dma_addr;
2171
2172 memset ( addr, 0, 4096 );
2173 dma_addr = virt_to_bus ( addr );
2174 EFAB_ASSERT ( ( dma_addr & ( EFAB_BUF_ALIGN - 1 ) ) == 0 );
2175 EFAB_POPULATE_QWORD_3 ( buf_desc,
2176 FCN_IP_DAT_BUF_SIZE, FCN_IP_DAT_BUF_SIZE_4K,
2177 FCN_BUF_ADR_FBUF, ( dma_addr >> 12 ),
2178 FCN_BUF_OWNER_ID_FBUF, 0 );
2179 falcon_write_sram_verify ( efab, &buf_desc, index );
2180 }
2181
2182 /**
2183 * Update event queue read pointer
2184 *
2185 */
2186 static void falcon_eventq_read_ack ( struct efab_nic *efab ) {
2187 efab_dword_t reg;
2188
2189 EFAB_ASSERT ( efab->eventq_read_ptr < EFAB_EVQ_SIZE );
2190
2191 EFAB_POPULATE_DWORD_1 ( reg, FCN_EVQ_RPTR_DWORD,
2192 efab->eventq_read_ptr );
2193 falcon_writel ( efab, &reg, FCN_EVQ_RPTR_REG_KER_DWORD );
2194 }
2195
2196 /**
2197 * Reset device
2198 *
2199 */
2200 static int falcon_reset ( struct efab_nic *efab ) {
2201 efab_oword_t glb_ctl_reg_ker;
2202
2203 /* Initiate software reset */
2204 EFAB_POPULATE_OWORD_7 ( glb_ctl_reg_ker,
2205 PCIE_CORE_RST_CTL, EXCLUDE_FROM_RESET,
2206 PCIE_NSTCK_RST_CTL, EXCLUDE_FROM_RESET,
2207 PCIE_SD_RST_CTL, EXCLUDE_FROM_RESET,
2208 EE_RST_CTL, EXCLUDE_FROM_RESET,
2209 PCIX_RST_CTL, EXCLUDE_FROM_RESET,
2210 EXT_PHY_RST_DUR, 0x7 /* datasheet recommended */,
2211 SWRST, 1 );
2212
2213 falcon_write ( efab, &glb_ctl_reg_ker, FCN_GLB_CTL_REG_KER );
2214
2215 /* Allow 20ms for reset */
2216 mdelay ( 20 );
2217
2218 /* Check for device reset complete */
2219 falcon_read ( efab, &glb_ctl_reg_ker, FCN_GLB_CTL_REG_KER );
2220 if ( EFAB_OWORD_FIELD ( glb_ctl_reg_ker, SWRST ) != 0 ) {
2221 EFAB_ERR ( "Reset failed\n" );
2222 return 0;
2223 }
2224
2225 return 1;
2226 }
2227
2228 /**
2229 * Wait for SPI command completion
2230 *
2231 */
2232 static int falcon_spi_wait ( struct efab_nic *efab ) {
2233 efab_oword_t reg;
2234 int count;
2235
2236 count = 0;
2237 do {
2238 udelay ( 100 );
2239 falcon_read ( efab, &reg, FCN_EE_SPI_HCMD_REG_KER );
2240 if ( EFAB_OWORD_FIELD ( reg, FCN_EE_SPI_HCMD_CMD_EN ) == 0 )
2241 return 1;
2242 } while ( ++count < 1000 );
2243 printf ( "Timed out waiting for SPI\n" );
2244 return 0;
2245 }
2246
2247 /**
2248 * Perform SPI read/write
2249 *
2250 */
2251 static int falcon_spi_rw ( struct spi_bus *bus, struct spi_device *device,
2252 unsigned int command, int address,
2253 const void *data_out, void *data_in, size_t len ) {
2254 struct efab_nic *efab = container_of ( bus, struct efab_nic, spi );
2255 efab_oword_t reg;
2256
2257 /* Program address register */
2258 EFAB_POPULATE_OWORD_1 ( reg, FCN_EE_SPI_HADR_ADR, address );
2259 falcon_write ( efab, &reg, FCN_EE_SPI_HADR_REG_KER );
2260
2261 /* Program data register, if applicable */
2262 if ( data_out ) {
2263 memcpy ( &reg, data_out, len );
2264 falcon_write ( efab, &reg, FCN_EE_SPI_HDATA_REG_KER );
2265 }
2266
2267 /* Issue command */
2268 EFAB_POPULATE_OWORD_7 ( reg,
2269 FCN_EE_SPI_HCMD_CMD_EN, 1,
2270 FCN_EE_SPI_HCMD_SF_SEL, device->slave,
2271 FCN_EE_SPI_HCMD_DABCNT, len,
2272 FCN_EE_SPI_HCMD_READ, ( data_out ?
2273 FCN_EE_SPI_WRITE : FCN_EE_SPI_READ ),
2274 FCN_EE_SPI_HCMD_DUBCNT, 0,
2275 FCN_EE_SPI_HCMD_ADBCNT,
2276 ( device->address_len / 8 ),
2277 FCN_EE_SPI_HCMD_ENC, command );
2278 falcon_write ( efab, &reg, FCN_EE_SPI_HCMD_REG_KER );
2279
2280 /* Wait for operation to complete */
2281 if ( ! falcon_spi_wait ( efab ) )
2282 return 0;
2283
2284 /* Read data, if applicable */
2285 if ( data_in ) {
2286 falcon_read ( efab, &reg, FCN_EE_SPI_HDATA_REG_KER );
2287 memcpy ( data_in, &reg, len );
2288 }
2289
2290 return 0;
2291 }
2292
2293 /**
2294 * Initialise SPI bus and devices
2295 *
2296 */
2297 static void falcon_init_spi ( struct efab_nic *efab ) {
2298 efab_oword_t reg;
2299 int eeprom_9bit;
2300
2301 /* Initialise SPI bus */
2302 efab->spi.rw = falcon_spi_rw;
2303 efab->falcon_eeprom.bus = &efab->spi;
2304 efab->falcon_eeprom.slave = FCN_EE_SPI_EEPROM;
2305 efab->falcon_flash.bus = &efab->spi;
2306 efab->falcon_flash.slave = FCN_EE_SPI_FLASH;
2307
2308 /* Initialise flash if present */
2309 if ( efab->has_flash ) {
2310 DBG ( "Flash is present\n" );
2311 init_at25f1024 ( &efab->falcon_flash );
2312 }
2313
2314 /* Initialise EEPROM if present */
2315 if ( efab->has_eeprom ) {
2316 if ( efab->is_asic ) {
2317 falcon_read ( efab, &reg, FCN_VPD_CONFIG_REG_KER );
2318 eeprom_9bit = EFAB_OWORD_FIELD ( reg, FCN_VPD_9BIT );
2319 } else {
2320 eeprom_9bit = 1;
2321 }
2322 if ( eeprom_9bit ) {
2323 DBG ( "Small EEPROM is present\n" );
2324 init_at25040 ( &efab->falcon_eeprom );
2325 } else {
2326 DBG ( "Large EEPROM is present\n" );
2327 init_mc25xx640 ( &efab->falcon_eeprom );
2328 /* Falcon's SPI interface cannot support a block
2329 size larger than 16, so forcibly reduce it
2330 */
2331 efab->falcon_eeprom.nvs.block_size = 16;
2332 }
2333 }
2334 }
2335
2336 /** Offset of MAC address within EEPROM or Flash */
2337 #define FALCON_MAC_ADDRESS_OFFSET(port) ( 0x310 + 0x08 * (port) )
2338
2339 static struct nvo_fragment falcon_eeprom_fragments[] = {
2340 { 0x100, 0x100 },
2341 { 0, 0 }
2342 };
2343
2344 /**
2345 * Read MAC address from EEPROM
2346 *
2347 */
2348 static int falcon_read_eeprom ( struct efab_nic *efab ) {
2349 struct nvs_device *nvs;
2350
2351 /* Determine the NVS device containing the MAC address */
2352 nvs = ( efab->has_flash ?
2353 &efab->falcon_flash.nvs : &efab->falcon_eeprom.nvs );
2354
2355 return ( nvs_read ( nvs, FALCON_MAC_ADDRESS_OFFSET ( efab->port ),
2356 efab->mac_addr, sizeof ( efab->mac_addr ) ) == 0 );
2357 }
2358
2359 /** RX descriptor */
2360 typedef efab_qword_t falcon_rx_desc_t;
2361
2362 /**
2363 * Build RX descriptor
2364 *
2365 */
2366 static void falcon_build_rx_desc ( struct efab_nic *efab,
2367 struct efab_rx_buf *rx_buf ) {
2368 falcon_rx_desc_t *rxd;
2369
2370 rxd = ( ( falcon_rx_desc_t * ) efab->rxd ) + rx_buf->id;
2371 EFAB_POPULATE_QWORD_2 ( *rxd,
2372 FCN_RX_KER_BUF_SIZE, EFAB_DATA_BUF_SIZE,
2373 FCN_RX_KER_BUF_ADR,
2374 virt_to_bus ( rx_buf->addr ) );
2375 }
2376
2377 /**
2378 * Update RX descriptor write pointer
2379 *
2380 */
2381 static void falcon_notify_rx_desc ( struct efab_nic *efab ) {
2382 efab_dword_t reg;
2383
2384 EFAB_POPULATE_DWORD_1 ( reg, FCN_RX_DESC_WPTR_DWORD,
2385 efab->rx_write_ptr );
2386 falcon_writel ( efab, &reg, FCN_RX_DESC_UPD_REG_KER_DWORD );
2387 }
2388
2389 /** TX descriptor */
2390 typedef efab_qword_t falcon_tx_desc_t;
2391
2392 /**
2393 * Build TX descriptor
2394 *
2395 */
2396 static void falcon_build_tx_desc ( struct efab_nic *efab,
2397 struct efab_tx_buf *tx_buf ) {
2398 falcon_rx_desc_t *txd;
2399
2400 txd = ( ( falcon_rx_desc_t * ) efab->txd ) + tx_buf->id;
2401 EFAB_POPULATE_QWORD_3 ( *txd,
2402 FCN_TX_KER_PORT, efab->port,
2403 FCN_TX_KER_BYTE_CNT, tx_buf->len,
2404 FCN_TX_KER_BUF_ADR,
2405 virt_to_bus ( tx_buf->addr ) );
2406 }
2407
2408 /**
2409 * Update TX descriptor write pointer
2410 *
2411 */
2412 static void falcon_notify_tx_desc ( struct efab_nic *efab ) {
2413 efab_dword_t reg;
2414
2415 EFAB_POPULATE_DWORD_1 ( reg, FCN_TX_DESC_WPTR_DWORD,
2416 efab->tx_write_ptr );
2417 falcon_writel ( efab, &reg, FCN_TX_DESC_UPD_REG_KER_DWORD );
2418 }
2419
2420 /** An event */
2421 typedef efab_qword_t falcon_event_t;
2422
2423 /**
2424 * See if an event is present
2425 *
2426 * @v event Falcon event structure
2427 * @ret True An event is pending
2428 * @ret False No event is pending
2429 *
2430 * We check both the high and low dword of the event for all ones. We
2431 * wrote all ones when we cleared the event, and no valid event can
2432 * have all ones in either its high or low dwords. This approach is
2433 * robust against reordering.
2434 *
2435 * Note that using a single 64-bit comparison is incorrect; even
2436 * though the CPU read will be atomic, the DMA write may not be.
2437 */
2438 static inline int falcon_event_present ( falcon_event_t* event ) {
2439 return ( ! ( EFAB_DWORD_IS_ALL_ONES ( event->dword[0] ) |
2440 EFAB_DWORD_IS_ALL_ONES ( event->dword[1] ) ) );
2441 }
2442
2443 /**
2444 * Retrieve event from event queue
2445 *
2446 */
2447 static int falcon_fetch_event ( struct efab_nic *efab,
2448 struct efab_event *event ) {
2449 falcon_event_t *evt;
2450 int ev_code;
2451 int rx_port;
2452
2453 /* Check for event */
2454 evt = ( ( falcon_event_t * ) efab->eventq ) + efab->eventq_read_ptr;
2455 if ( !falcon_event_present ( evt ) ) {
2456 /* No event */
2457 return 0;
2458 }
2459
2460 DBG ( "Event is " EFAB_QWORD_FMT "\n", EFAB_QWORD_VAL ( *evt ) );
2461
2462 /* Decode event */
2463 ev_code = EFAB_QWORD_FIELD ( *evt, FCN_EV_CODE );
2464 event->drop = 0;
2465 switch ( ev_code ) {
2466 case FCN_TX_IP_EV_DECODE:
2467 event->type = EFAB_EV_TX;
2468 break;
2469 case FCN_RX_IP_EV_DECODE:
2470 event->type = EFAB_EV_RX;
2471 event->rx_id = EFAB_QWORD_FIELD ( *evt, FCN_RX_EV_DESC_PTR );
2472 event->rx_len = EFAB_QWORD_FIELD ( *evt, FCN_RX_EV_BYTE_CNT );
2473 event->drop = !EFAB_QWORD_FIELD ( *evt, FCN_RX_EV_PKT_OK );
2474 rx_port = EFAB_QWORD_FIELD ( *evt, FCN_RX_PORT );
2475 if ( rx_port != efab->port ) {
2476 /* Ignore packets on the wrong port. We can't
2477 * just set event->type = EFAB_EV_NONE,
2478 * because then the descriptor ring won't get
2479 * refilled.
2480 */
2481 event->rx_len = 0;
2482 }
2483 break;
2484 case FCN_DRIVER_EV_DECODE:
2485 /* Ignore start-of-day events */
2486 event->type = EFAB_EV_NONE;
2487 break;
2488 default:
2489 EFAB_ERR ( "Unknown event type %d data %08lx\n", ev_code,
2490 EFAB_DWORD_FIELD ( *evt, EFAB_DWORD_0 ) );
2491 event->type = EFAB_EV_NONE;
2492 }
2493
2494 /* Clear event and any pending interrupts */
2495 EFAB_SET_QWORD ( *evt );
2496 falcon_writel ( efab, 0, FCN_INT_ACK_KER_REG );
2497 udelay ( 10 );
2498
2499 /* Increment and update event queue read pointer */
2500 efab->eventq_read_ptr = ( ( efab->eventq_read_ptr + 1 )
2501 % EFAB_EVQ_SIZE );
2502 falcon_eventq_read_ack ( efab );
2503
2504 return 1;
2505 }
2506
2507 /**
2508 * Enable/disable/generate interrupt
2509 *
2510 */
2511 static inline void falcon_interrupts ( struct efab_nic *efab, int enabled,
2512 int force ) {
2513 efab_oword_t int_en_reg_ker;
2514
2515 EFAB_POPULATE_OWORD_2 ( int_en_reg_ker,
2516 FCN_KER_INT_KER, force,
2517 FCN_DRV_INT_EN_KER, enabled );
2518 falcon_write ( efab, &int_en_reg_ker, FCN_INT_EN_REG_KER );
2519 }
2520
2521 /**
2522 * Enable/disable interrupts
2523 *
2524 */
2525 static void falcon_mask_irq ( struct efab_nic *efab, int enabled ) {
2526 falcon_interrupts ( efab, enabled, 0 );
2527 if ( enabled ) {
2528 /* Events won't trigger interrupts until we do this */
2529 falcon_eventq_read_ack ( efab );
2530 }
2531 }
2532
2533 /**
2534 * Generate interrupt
2535 *
2536 */
2537 static void falcon_generate_irq ( struct efab_nic *efab ) {
2538 falcon_interrupts ( efab, 1, 1 );
2539 }
2540
2541
2542 /**
2543 * Reconfigure MAC wrapper
2544 *
2545 */
2546 static void falcon_reconfigure_mac_wrapper ( struct efab_nic *efab ) {
2547 efab_oword_t reg;
2548 int link_speed;
2549
2550 if ( efab->link_options & LPA_10000 ) {
2551 link_speed = 0x3;
2552 } else if ( efab->link_options & LPA_1000 ) {
2553 link_speed = 0x2;
2554 } else if ( efab->link_options & LPA_100 ) {
2555 link_speed = 0x1;
2556 } else {
2557 link_speed = 0x0;
2558 }
2559 EFAB_POPULATE_OWORD_5 ( reg,
2560 FCN_MAC_XOFF_VAL, 0xffff /* datasheet */,
2561 FCN_MAC_BCAD_ACPT, 1,
2562 FCN_MAC_UC_PROM, 0,
2563 FCN_MAC_LINK_STATUS, 1,
2564 FCN_MAC_SPEED, link_speed );
2565 falcon_write ( efab, &reg,
2566 ( efab->port == 0 ?
2567 FCN_MAC0_CTRL_REG_KER : FCN_MAC1_CTRL_REG_KER ) );
2568
2569 /* Disable flow-control (i.e. never generate pause frames) */
2570 falcon_read ( efab, &reg, FCN_RX_CFG_REG_KER );
2571 EFAB_SET_OWORD_FIELD ( reg, FCN_RX_XOFF_EN, 0 );
2572 falcon_write ( efab, &reg, FCN_RX_CFG_REG_KER );
2573 }
2574
2575 /**
2576 * Write dword to a Falcon MAC register
2577 *
2578 */
2579 static void falcon_gmac_writel ( struct efab_nic *efab,
2580 efab_dword_t *value, unsigned int mac_reg ) {
2581 efab_oword_t temp;
2582
2583 EFAB_POPULATE_OWORD_1 ( temp, FCN_MAC_DATA,
2584 EFAB_DWORD_FIELD ( *value, FCN_MAC_DATA ) );
2585 falcon_write ( efab, &temp, FALCON_GMAC_REG ( efab, mac_reg ) );
2586 }
2587
2588 /**
2589 * Read dword from a Falcon GMAC register
2590 *
2591 */
2592 static void falcon_gmac_readl ( struct efab_nic *efab, efab_dword_t *value,
2593 unsigned int mac_reg ) {
2594 efab_oword_t temp;
2595
2596 falcon_read ( efab, &temp, FALCON_GMAC_REG ( efab, mac_reg ) );
2597 EFAB_POPULATE_DWORD_1 ( *value, FCN_MAC_DATA,
2598 EFAB_OWORD_FIELD ( temp, FCN_MAC_DATA ) );
2599 }
2600
2601 /**
2602 * Write dword to a Falcon XMAC register
2603 *
2604 */
2605 static void falcon_xmac_writel ( struct efab_nic *efab,
2606 efab_dword_t *value, unsigned int mac_reg ) {
2607 efab_oword_t temp;
2608
2609 EFAB_POPULATE_OWORD_1 ( temp, FCN_MAC_DATA,
2610 EFAB_DWORD_FIELD ( *value, FCN_MAC_DATA ) );
2611 falcon_write ( efab, &temp,
2612 FALCON_XMAC_REG ( efab, mac_reg ) );
2613 }
2614
2615 /**
2616 * Read dword from a Falcon XMAC register
2617 *
2618 */
2619 static void falcon_xmac_readl ( struct efab_nic *efab,
2620 efab_dword_t *value,
2621 unsigned int mac_reg ) {
2622 efab_oword_t temp;
2623
2624 falcon_read ( efab, &temp,
2625 FALCON_XMAC_REG ( efab, mac_reg ) );
2626 EFAB_POPULATE_DWORD_1 ( *value, FCN_MAC_DATA,
2627 EFAB_OWORD_FIELD ( temp, FCN_MAC_DATA ) );
2628 }
2629
2630 /**
2631 * Initialise GMAC
2632 *
2633 */
2634 static int falcon_init_gmac ( struct efab_nic *efab ) {
2635 static struct efab_mentormac_parameters falcon_mentormac_params = {
2636 .gmf_cfgfrth = 0x12,
2637 .gmf_cfgftth = 0x08,
2638 .gmf_cfghwmft = 0x1c,
2639 .gmf_cfghwm = 0x3f,
2640 .gmf_cfglwm = 0xa,
2641 };
2642
2643 /* Initialise PHY */
2644 alaska_init ( efab );
2645
2646 /* check the link is up */
2647 if ( !efab->link_up )
2648 return 0;
2649
2650 /* Initialise MAC */
2651 mentormac_init ( efab, &falcon_mentormac_params );
2652
2653 /* reconfigure the MAC wrapper */
2654 falcon_reconfigure_mac_wrapper ( efab );
2655
2656 return 1;
2657 }
2658
2659 /**
2660 * Reset GMAC
2661 *
2662 */
2663 static int falcon_reset_gmac ( struct efab_nic *efab ) {
2664 mentormac_reset ( efab );
2665 return 1;
2666 }
2667
2668 /**
2669 * Reset XAUI/XGXS block
2670 *
2671 */
2672 static int falcon_reset_xaui ( struct efab_nic *efab )
2673 {
2674 efab_dword_t reg;
2675 int count;
2676
2677 EFAB_POPULATE_DWORD_1 ( reg, FCN_XX_RST_XX_EN, 1 );
2678 efab->mac_op->mac_writel ( efab, &reg, FCN_XX_PWR_RST_REG_MAC );
2679
2680 for ( count = 0 ; count < 1000 ; count++ ) {
2681 udelay ( 10 );
2682 efab->mac_op->mac_readl ( efab, &reg,
2683 FCN_XX_PWR_RST_REG_MAC );
2684 if ( EFAB_DWORD_FIELD ( reg, FCN_XX_RST_XX_EN ) == 0 )
2685 return 1;
2686 }
2687
2688 /* an error of some kind */
2689 return 0;
2690 }
2691
2692 /**
2693 * Reset 10G MAC connected to port
2694 *
2695 */
2696 static int falcon_reset_xmac ( struct efab_nic *efab ) {
2697 efab_dword_t reg;
2698 int count;
2699
2700 EFAB_POPULATE_DWORD_1 ( reg, FCN_XM_CORE_RST, 1 );
2701 efab->mac_op->mac_writel ( efab, &reg, FCN_XM_GLB_CFG_REG_MAC );
2702
2703 for ( count = 0 ; count < 1000 ; count++ ) {
2704 udelay ( 10 );
2705 efab->mac_op->mac_readl ( efab, &reg,
2706 FCN_XM_GLB_CFG_REG_MAC );
2707 if ( EFAB_DWORD_FIELD ( reg, FCN_XM_CORE_RST ) == 0 )
2708 return 1;
2709 }
2710 return 0;
2711 }
2712
2713 /**
2714 * Get status of 10G link
2715 *
2716 */
2717 static int falcon_xaui_link_ok ( struct efab_nic *efab ) {
2718 efab_dword_t reg;
2719 int align_done;
2720 int sync_status;
2721 int link_ok = 0;
2722
2723 /* Read link status */
2724 efab->mac_op->mac_readl ( efab, &reg, FCN_XX_CORE_STAT_REG_MAC );
2725 align_done = EFAB_DWORD_FIELD ( reg, FCN_XX_ALIGN_DONE );
2726 sync_status = EFAB_DWORD_FIELD ( reg, FCN_XX_SYNC_STAT );
2727 if ( align_done && ( sync_status == FCN_XX_SYNC_STAT_DECODE_SYNCED ) ) {
2728 link_ok = 1;
2729 }
2730
2731 /* Clear link status ready for next read */
2732 EFAB_SET_DWORD_FIELD ( reg, FCN_XX_COMMA_DET, FCN_XX_COMMA_DET_RESET );
2733 efab->mac_op->mac_writel ( efab, &reg, FCN_XX_CORE_STAT_REG_MAC );
2734
2735 return link_ok;
2736 }
2737
2738 /**
2739 * Initialise XMAC
2740 *
2741 */
2742 static int falcon_init_xmac ( struct efab_nic *efab ) {
2743 efab_dword_t reg;
2744 int count;
2745
2746 if ( !falcon_reset_xmac ( efab ) ) {
2747 EFAB_ERR ( "failed resetting XMAC\n" );
2748 return 0;
2749 }
2750 if ( !falcon_reset_xaui ( efab ) ) {
2751 EFAB_ERR ( "failed resetting XAUI\n");
2752 return 0;
2753 }
2754
2755 /* CX4 is always 10000FD only */
2756 efab->link_options = LPA_10000FULL;
2757
2758 /* Configure MAC */
2759 EFAB_POPULATE_DWORD_3 ( reg,
2760 FCN_XM_RX_JUMBO_MODE, 1,
2761 FCN_XM_TX_STAT_EN, 1,
2762 FCN_XM_RX_STAT_EN, 1);
2763 efab->mac_op->mac_writel ( efab, &reg, FCN_XM_GLB_CFG_REG_MAC );
2764
2765 /* Configure TX */
2766 EFAB_POPULATE_DWORD_6 ( reg,
2767 FCN_XM_TXEN, 1,
2768 FCN_XM_TX_PRMBL, 1,
2769 FCN_XM_AUTO_PAD, 1,
2770 FCN_XM_TXCRC, 1,
2771 FCN_XM_FCNTL, 1,
2772 FCN_XM_IPG, 0x3 );
2773 efab->mac_op->mac_writel ( efab, &reg, FCN_XM_TX_CFG_REG_MAC );
2774
2775 /* Configure RX */
2776 EFAB_POPULATE_DWORD_3 ( reg,
2777 FCN_XM_RXEN, 1,
2778 FCN_XM_AUTO_DEPAD, 1,
2779 FCN_XM_PASS_CRC_ERR, 1 );
2780 efab->mac_op->mac_writel ( efab, &reg, FCN_XM_RX_CFG_REG_MAC );
2781
2782 /* Set frame length */
2783 EFAB_POPULATE_DWORD_1 ( reg,
2784 FCN_XM_MAX_RX_FRM_SIZE, ETH_FRAME_LEN );
2785 efab->mac_op->mac_writel ( efab, &reg, FCN_XM_RX_PARAM_REG_MAC );
2786 EFAB_POPULATE_DWORD_2 ( reg,
2787 FCN_XM_MAX_TX_FRM_SIZE, ETH_FRAME_LEN,
2788 FCN_XM_TX_JUMBO_MODE, 1 );
2789 efab->mac_op->mac_writel ( efab, &reg, FCN_XM_TX_PARAM_REG_MAC );
2790
2791 /* Set MAC address */
2792 EFAB_POPULATE_DWORD_4 ( reg,
2793 FCN_XM_ADR_0, efab->mac_addr[0],
2794 FCN_XM_ADR_1, efab->mac_addr[1],
2795 FCN_XM_ADR_2, efab->mac_addr[2],
2796 FCN_XM_ADR_3, efab->mac_addr[3] );
2797 efab->mac_op->mac_writel ( efab, &reg, FCN_XM_ADR_LO_REG_MAC );
2798 EFAB_POPULATE_DWORD_2 ( reg,
2799 FCN_XM_ADR_4, efab->mac_addr[4],
2800 FCN_XM_ADR_5, efab->mac_addr[5] );
2801 efab->mac_op->mac_writel ( efab, &reg, FCN_XM_ADR_HI_REG_MAC );
2802
2803 /* Reconfigure MAC wrapper */
2804 falcon_reconfigure_mac_wrapper ( efab );
2805
2806 /**
2807 * Try resetting XAUI on its own waiting for the link
2808 * to come up
2809 */
2810 for(count=0; count<5; count++) {
2811 /* Check link status */
2812 efab->link_up = falcon_xaui_link_ok ( efab );
2813 if ( efab->link_up ) {
2814 /**
2815 * Print out a speed message since we don't have a PHY
2816 */
2817 EFAB_LOG ( "%dMbps %s-duplex\n",
2818 ( efab->link_options & LPA_10000 ? 1000 :
2819 ( efab->link_options & LPA_1000 ? 1000 :
2820 ( efab->link_options & LPA_100 ? 100 : 10 ) ) ),
2821 ( efab->link_options & LPA_DUPLEX ? "full" : "half" ) );
2822 break;
2823 }
2824
2825 if ( !falcon_reset_xaui ( efab ) ) {
2826 EFAB_ERR ( "failed resetting xaui\n" );
2827 return 0;
2828 }
2829 udelay(100);
2830 }
2831
2832 return 1;
2833 }
2834
2835 /**
2836 * Wait for GMII access to complete
2837 *
2838 */
2839 static int falcon_gmii_wait ( struct efab_nic *efab ) {
2840 efab_oword_t md_stat;
2841 int count;
2842
2843 for ( count = 0 ; count < 1000 ; count++ ) {
2844 udelay ( 10 );
2845 falcon_read ( efab, &md_stat, FCN_MD_STAT_REG_KER );
2846 if ( EFAB_OWORD_FIELD ( md_stat, FCN_MD_BSY ) == 0 )
2847 return 1;
2848 }
2849 EFAB_ERR ( "Timed out waiting for GMII\n" );
2850 return 0;
2851 }
2852
2853
2854 static struct efab_mac_operations falcon_xmac_operations = {
2855 .mac_readl = falcon_xmac_readl,
2856 .mac_writel = falcon_xmac_writel,
2857 .init = falcon_init_xmac,
2858 .reset = falcon_reset_xmac,
2859 };
2860
2861 static struct efab_mac_operations falcon_gmac_operations = {
2862 .mac_readl = falcon_gmac_readl,
2863 .mac_writel = falcon_gmac_writel,
2864 .init = falcon_init_gmac,
2865 .reset = falcon_reset_gmac,
2866 };
2867
2868
2869 /**
2870 * Initialise NIC
2871 *
2872 */
2873 static int falcon_init_nic ( struct efab_nic *efab ) {
2874 efab_oword_t reg;
2875 efab_dword_t timer_cmd;
2876 int version, minor;
2877
2878 /* use card in internal SRAM mode */
2879 falcon_read ( efab, &reg, FCN_NIC_STAT_REG );
2880 EFAB_SET_OWORD_FIELD ( reg, ONCHIP_SRAM, 1 );
2881 falcon_write ( efab, &reg, FCN_NIC_STAT_REG );
2882 wmb();
2883
2884 /* identify FPGA/ASIC, and strapping mode */
2885 falcon_read ( efab, &reg, ALTERA_BUILD_REG_KER );
2886 version = EFAB_OWORD_FIELD ( reg, VER_ALL );
2887 efab->is_asic = version ? 0 : 1;
2888
2889 if ( efab->is_asic ) {
2890 falcon_read ( efab, &reg, FCN_NIC_STAT_REG );
2891 if ( EFAB_OWORD_FIELD ( reg, STRAP_10G ) ) {
2892 efab->is_10g = 1;
2893 }
2894 if ( EFAB_OWORD_FIELD ( reg, STRAP_DUAL_PORT ) ) {
2895 efab->is_dual = 1;
2896 }
2897 }
2898 else {
2899 falcon_read ( efab, &reg, ALTERA_BUILD_REG_KER );
2900 minor = EFAB_OWORD_FIELD ( reg, VER_MINOR );
2901
2902 if ( minor == 0x14 ) {
2903 efab->is_10g = 1;
2904 } else if ( minor == 0x13 ) {
2905 efab->is_dual = 1;
2906 }
2907 }
2908
2909 DBG ( "NIC type: %s %dx%s\n",
2910 efab->is_asic ? "ASIC" : "FPGA",
2911 efab->is_dual ? 2 : 1,
2912 efab->is_10g ? "10G" : "1G" );
2913
2914 /* patch in MAC operations */
2915 if ( efab->is_10g )
2916 efab->mac_op = &falcon_xmac_operations;
2917 else
2918 efab->mac_op = &falcon_gmac_operations;
2919
2920 if ( !efab->is_dual && ( efab->port == 1 ) ) {
2921 /* device doesn't exist */
2922 return 0;
2923 }
2924
2925 /* determine EEPROM / FLASH */
2926 if ( efab->is_asic ) {
2927 falcon_read ( efab, &reg, FCN_NIC_STAT_REG );
2928 efab->has_flash = EFAB_OWORD_FIELD ( reg, SF_PRST );
2929 efab->has_eeprom = EFAB_OWORD_FIELD ( reg, EE_PRST );
2930 } else {
2931 falcon_read ( efab, &reg, FCN_GPIO_CTL_REG_KER );
2932 efab->has_flash = EFAB_OWORD_FIELD ( reg, FCN_FLASH_PRESENT );
2933 efab->has_eeprom = EFAB_OWORD_FIELD ( reg, FCN_EEPROM_PRESENT);
2934 }
2935 DBG ( "flash is %s, EEPROM is %s\n",
2936 ( efab->has_flash ? "present" : "absent" ),
2937 ( efab->has_eeprom ? "present" : "absent" ) );
2938 falcon_init_spi ( efab );
2939
2940 /* Set up TX and RX descriptor caches in SRAM */
2941 EFAB_POPULATE_OWORD_1 ( reg, FCN_SRM_TX_DC_BASE_ADR,
2942 0x130000 /* recommended in datasheet */ );
2943 falcon_write ( efab, &reg, FCN_SRM_TX_DC_CFG_REG_KER );
2944 EFAB_POPULATE_OWORD_1 ( reg, FCN_TX_DC_SIZE, 2 /* 32 descriptors */ );
2945 falcon_write ( efab, &reg, FCN_TX_DC_CFG_REG_KER );
2946 EFAB_POPULATE_OWORD_1 ( reg, FCN_SRM_RX_DC_BASE_ADR,
2947 0x100000 /* recommended in datasheet */ );
2948 falcon_write ( efab, &reg, FCN_SRM_RX_DC_CFG_REG_KER );
2949 EFAB_POPULATE_OWORD_1 ( reg, FCN_RX_DC_SIZE, 2 /* 32 descriptors */ );
2950 falcon_write ( efab, &reg, FCN_RX_DC_CFG_REG_KER );
2951
2952 /* Set number of RSS CPUs */
2953 EFAB_POPULATE_OWORD_1 ( reg, FCN_NUM_KER, 0 );
2954 falcon_write ( efab, &reg, FCN_RX_FILTER_CTL_REG_KER );
2955 udelay ( 1000 );
2956
2957 /* Reset the MAC */
2958 mentormac_reset ( efab );
2959
2960 /* Set up event queue */
2961 falcon_create_special_buffer ( efab, efab->eventq, FALCON_EVQ_ID );
2962 /* Fill eventq with all ones ( empty events ) */
2963 memset(efab->eventq, 0xff, 4096);
2964 /* push eventq to card */
2965 EFAB_POPULATE_OWORD_3 ( reg,
2966 FCN_EVQ_EN, 1,
2967 FCN_EVQ_SIZE, FCN_EVQ_SIZE_512,
2968 FCN_EVQ_BUF_BASE_ID, FALCON_EVQ_ID );
2969 falcon_write ( efab, &reg, FCN_EVQ_PTR_TBL_KER );
2970 udelay ( 1000 );
2971
2972 /* Set timer register */
2973 EFAB_POPULATE_DWORD_2 ( timer_cmd,
2974 FCN_TIMER_MODE, FCN_TIMER_MODE_DIS,
2975 FCN_TIMER_VAL, 0 );
2976 falcon_writel ( efab, &timer_cmd, FCN_TIMER_CMD_REG_KER );
2977 udelay ( 1000 );
2978
2979 /* Initialise event queue read pointer */
2980 falcon_eventq_read_ack ( efab );
2981
2982 /* Set up TX descriptor ring */
2983 falcon_create_special_buffer ( efab, efab->txd, FALCON_TXD_ID );
2984 EFAB_POPULATE_OWORD_5 ( reg,
2985 FCN_TX_DESCQ_EN, 1,
2986 FCN_TX_DESCQ_BUF_BASE_ID, FALCON_TXD_ID,
2987 FCN_TX_DESCQ_EVQ_ID, 0,
2988 FCN_TX_DESCQ_SIZE, FCN_TX_DESCQ_SIZE_512,
2989 FCN_TX_DESCQ_TYPE, 0 /* kernel queue */ );
2990 falcon_write ( efab, &reg, FCN_TX_DESC_PTR_TBL_KER );
2991
2992 /* Set up RX descriptor ring */
2993 falcon_create_special_buffer ( efab, efab->rxd, FALCON_RXD_ID );
2994 EFAB_POPULATE_OWORD_6 ( reg,
2995 FCN_RX_DESCQ_BUF_BASE_ID, FALCON_RXD_ID,
2996 FCN_RX_DESCQ_EVQ_ID, 0,
2997 FCN_RX_DESCQ_SIZE, FCN_RX_DESCQ_SIZE_512,
2998 FCN_RX_DESCQ_TYPE, 0 /* kernel queue */,
2999 FCN_RX_DESCQ_JUMBO, 1,
3000 FCN_RX_DESCQ_EN, 1 );
3001 falcon_write ( efab, &reg, FCN_RX_DESC_PTR_TBL_KER );
3002
3003 /* Program INT_ADR_REG_KER */
3004 EFAB_POPULATE_OWORD_1 ( reg,
3005 FCN_INT_ADR_KER,
3006 virt_to_bus ( &efab->int_ker ) );
3007 falcon_write ( efab, &reg, FCN_INT_ADR_REG_KER );
3008 udelay ( 1000 );
3009
3010 /* Register non-volatile storage */
3011 if ( efab->has_eeprom ) {
3012 efab->nvo.nvs = &efab->falcon_eeprom.nvs;
3013 efab->nvo.fragments = falcon_eeprom_fragments;
3014 if ( nvo_register ( &efab->nvo ) != 0 )
3015 return 0;
3016 }
3017
3018 return 1;
3019 }
3020
3021 /** MDIO write */
3022 static void falcon_mdio_write ( struct efab_nic *efab, int location,
3023 int value ) {
3024 int phy_id = efab->port + 2;
3025 efab_oword_t reg;
3026
3027 EFAB_TRACE ( "Writing GMII %d register %02x with %04x\n",
3028 phy_id, location, value );
3029
3030 /* Check MII not currently being accessed */
3031 if ( ! falcon_gmii_wait ( efab ) )
3032 return;
3033
3034 /* Write the address registers */
3035 EFAB_POPULATE_OWORD_1 ( reg, FCN_MD_PHY_ADR, 0 /* phy_id ? */ );
3036 falcon_write ( efab, &reg, FCN_MD_PHY_ADR_REG_KER );
3037 udelay ( 10 );
3038 EFAB_POPULATE_OWORD_2 ( reg,
3039 FCN_MD_PRT_ADR, phy_id,
3040 FCN_MD_DEV_ADR, location );
3041 falcon_write ( efab, &reg, FCN_MD_ID_REG_KER );
3042 udelay ( 10 );
3043
3044 /* Write data */
3045 EFAB_POPULATE_OWORD_1 ( reg, FCN_MD_TXD, value );
3046 falcon_write ( efab, &reg, FCN_MD_TXD_REG_KER );
3047 udelay ( 10 );
3048 EFAB_POPULATE_OWORD_2 ( reg,
3049 FCN_MD_WRC, 1,
3050 FCN_MD_GC, 1 );
3051 falcon_write ( efab, &reg, FCN_MD_CS_REG_KER );
3052 udelay ( 10 );
3053
3054 /* Wait for data to be written */
3055 falcon_gmii_wait ( efab );
3056 }
3057
3058 /** MDIO read */
3059 static int falcon_mdio_read ( struct efab_nic *efab, int location ) {
3060 int phy_id = efab->port + 2;
3061 efab_oword_t reg;
3062 int value;
3063
3064 /* Check MII not currently being accessed */
3065 if ( ! falcon_gmii_wait ( efab ) )
3066 return 0xffff;
3067
3068 /* Write the address registers */
3069 EFAB_POPULATE_OWORD_1 ( reg, FCN_MD_PHY_ADR, 0 /* phy_id ? */ );
3070 falcon_write ( efab, &reg, FCN_MD_PHY_ADR_REG_KER );
3071 udelay ( 10 );
3072 EFAB_POPULATE_OWORD_2 ( reg,
3073 FCN_MD_PRT_ADR, phy_id,
3074 FCN_MD_DEV_ADR, location );
3075 falcon_write ( efab, &reg, FCN_MD_ID_REG_KER );
3076 udelay ( 10 );
3077
3078 /* Request data to be read */
3079 EFAB_POPULATE_OWORD_2 ( reg,
3080 FCN_MD_RIC, 1,
3081 FCN_MD_GC, 1 );
3082 falcon_write ( efab, &reg, FCN_MD_CS_REG_KER );
3083 udelay ( 10 );
3084
3085 /* Wait for data to become available */
3086 falcon_gmii_wait ( efab );
3087
3088 /* Read the data */
3089 falcon_read ( efab, &reg, FCN_MD_RXD_REG_KER );
3090 value = EFAB_OWORD_FIELD ( reg, FCN_MD_RXD );
3091
3092 EFAB_TRACE ( "Read from GMII %d register %02x, got %04x\n",
3093 phy_id, location, value );
3094
3095 return value;
3096 }
3097
3098 static struct efab_operations falcon_operations = {
3099 .get_membase = falcon_get_membase,
3100 .reset = falcon_reset,
3101 .init_nic = falcon_init_nic,
3102 .read_eeprom = falcon_read_eeprom,
3103 .build_rx_desc = falcon_build_rx_desc,
3104 .notify_rx_desc = falcon_notify_rx_desc,
3105 .build_tx_desc = falcon_build_tx_desc,
3106 .notify_tx_desc = falcon_notify_tx_desc,
3107 .fetch_event = falcon_fetch_event,
3108 .mask_irq = falcon_mask_irq,
3109 .generate_irq = falcon_generate_irq,
3110 .mdio_write = falcon_mdio_write,
3111 .mdio_read = falcon_mdio_read,
3112 };
3113
3114 /**************************************************************************
3115 *
3116 * Etherfabric abstraction layer
3117 *
3118 **************************************************************************
3119 */
3120
3121 /**
3122 * Push RX buffer to RXD ring
3123 *
3124 */
3125 static inline void efab_push_rx_buffer ( struct efab_nic *efab,
3126 struct efab_rx_buf *rx_buf ) {
3127 /* Create RX descriptor */
3128 rx_buf->id = efab->rx_write_ptr;
3129 efab->op->build_rx_desc ( efab, rx_buf );
3130
3131 /* Update RX write pointer */
3132 efab->rx_write_ptr = ( efab->rx_write_ptr + 1 ) % EFAB_RXD_SIZE;
3133 efab->op->notify_rx_desc ( efab );
3134
3135 DBG ( "Added RX id %x\n", rx_buf->id );
3136 }
3137
3138 /**
3139 * Push TX buffer to TXD ring
3140 *
3141 */
3142 static inline void efab_push_tx_buffer ( struct efab_nic *efab,
3143 struct efab_tx_buf *tx_buf ) {
3144 /* Create TX descriptor */
3145 tx_buf->id = efab->tx_write_ptr;
3146 efab->op->build_tx_desc ( efab, tx_buf );
3147
3148 /* Update TX write pointer */
3149 efab->tx_write_ptr = ( efab->tx_write_ptr + 1 ) % EFAB_TXD_SIZE;
3150 efab->op->notify_tx_desc ( efab );
3151
3152 DBG ( "Added TX id %x\n", tx_buf->id );
3153 }
3154
3155 /**
3156 * Initialise MAC and wait for link up
3157 *
3158 */
3159 static int efab_init_mac ( struct efab_nic *efab ) {
3160 int count;
3161
3162 /* This can take several seconds */
3163 EFAB_LOG ( "Waiting for link.." );
3164 for ( count=0; count<5; count++ ) {
3165 putchar ( '.' );
3166
3167 if ( ! efab->mac_op->init ( efab ) ) {
3168 EFAB_ERR ( "Failed reinitialising MAC\n" );
3169 return 0;
3170 }
3171 if ( efab->link_up ) {
3172 /* PHY init printed the message for us */
3173 return 1;
3174 }
3175 EFAB_ERR( "link is down" );
3176 sleep ( 1 );
3177 }
3178 EFAB_ERR ( " timed initialising MAC\n " );
3179
3180 return 0;
3181 }
3182
3183 /**
3184 * Initialise NIC
3185 *
3186 */
3187 static int efab_init_nic ( struct efab_nic *efab ) {
3188 int i;
3189
3190 /* Initialise NIC */
3191 if ( ! efab->op->init_nic ( efab ) )
3192 return 0;
3193
3194 /* Push RX descriptors */
3195 for ( i = 0 ; i < EFAB_RX_BUFS ; i++ ) {
3196 efab_push_rx_buffer ( efab, &efab->rx_bufs[i] );
3197 }
3198
3199 /* Read MAC address from EEPROM */
3200 if ( ! efab->op->read_eeprom ( efab ) )
3201 return 0;
3202
3203 /* Initialise MAC and wait for link up */
3204 if ( ! efab_init_mac ( efab ) )
3205 return 0;
3206
3207 return 1;
3208 }
3209
3210 /**************************************************************************
3211 *
3212 * Etherboot interface
3213 *
3214 **************************************************************************
3215 */
3216
3217 /**************************************************************************
3218 POLL - Wait for a frame
3219 ***************************************************************************/
3220 static int etherfabric_poll ( struct nic *nic, int retrieve ) {
3221 struct efab_nic *efab = nic->priv_data;
3222 struct efab_event event;
3223 static struct efab_rx_buf *rx_buf = NULL;
3224 int i, drop = 0;
3225
3226 /* Process the event queue until we hit either a packet
3227 * received event or an empty event slot.
3228 */
3229 while ( ( rx_buf == NULL ) &&
3230 efab->op->fetch_event ( efab, &event ) ) {
3231 drop = event.drop;
3232 if ( event.type == EFAB_EV_TX ) {
3233 /* TX completed - mark as done */
3234 DBG ( "TX id %x complete\n",
3235 efab->tx_buf.id );
3236 } else if ( event.type == EFAB_EV_RX ) {
3237 /* RX - find corresponding buffer */
3238 for ( i = 0 ; i < EFAB_RX_BUFS ; i++ ) {
3239 if ( efab->rx_bufs[i].id == event.rx_id ) {
3240 rx_buf = &efab->rx_bufs[i];
3241 rx_buf->len = event.rx_len;
3242 DBG ( "RX id %x (len %x) received\n",
3243 rx_buf->id, rx_buf->len );
3244 break;
3245 }
3246 }
3247 if ( ! rx_buf ) {
3248 EFAB_ERR ( "Invalid RX ID %x\n", event.rx_id );
3249 }
3250 } else if ( event.type == EFAB_EV_NONE ) {
3251 DBG ( "Ignorable event\n" );
3252 } else {
3253 DBG ( "Unknown event\n" );
3254 }
3255 }
3256
3257 /* If there is no packet, return 0 */
3258 if ( ! rx_buf )
3259 return 0;
3260
3261 /* drop this event if necessary */
3262 if ( drop ) {
3263 DBG( "discarding RX event\n" );
3264 return 0;
3265 }
3266
3267 /* If we don't want to retrieve it just yet, return 1 */
3268 if ( ! retrieve )
3269 return 1;
3270
3271 /* There seems to be a hardware race. The event can show up
3272 * on the event FIFO before the DMA has completed, so we
3273 * insert a tiny delay. If this proves unreliable, we should
3274 * switch to using event DMA rather than the event FIFO, since
3275 * event DMA ordering is guaranteed.
3276 */
3277 udelay ( 2 );
3278
3279 /* Copy packet contents */
3280 nic->packetlen = rx_buf->len;
3281 memcpy ( nic->packet, rx_buf->addr, nic->packetlen );
3282
3283 /* Give this buffer back to the NIC */
3284 efab_push_rx_buffer ( efab, rx_buf );
3285
3286 /* Prepare to receive next packet */
3287 rx_buf = NULL;
3288
3289 return 1;
3290 }
3291
3292 /**************************************************************************
3293 TRANSMIT - Transmit a frame
3294 ***************************************************************************/
3295 static void etherfabric_transmit ( struct nic *nic, const char *dest,
3296 unsigned int type, unsigned int size,
3297 const char *data ) {
3298 struct efab_nic *efab = nic->priv_data;
3299 unsigned int nstype = htons ( type );
3300
3301 /* Fill TX buffer, pad to ETH_ZLEN */
3302 memcpy ( efab->tx_buf.addr, dest, ETH_ALEN );
3303 memcpy ( efab->tx_buf.addr + ETH_ALEN, nic->node_addr, ETH_ALEN );
3304 memcpy ( efab->tx_buf.addr + 2 * ETH_ALEN, &nstype, 2 );
3305 memcpy ( efab->tx_buf.addr + ETH_HLEN, data, size );
3306 size += ETH_HLEN;
3307 while ( size < ETH_ZLEN ) {
3308 efab->tx_buf.addr[size++] = '\0';
3309 }
3310 efab->tx_buf.len = size;
3311
3312 /* Push TX descriptor */
3313 efab_push_tx_buffer ( efab, &efab->tx_buf );
3314
3315 /* Allow enough time for the packet to be transmitted. This
3316 * is a temporary hack until we update to the new driver API.
3317 */
3318 udelay ( 20 );
3319
3320 return;
3321 }
3322
3323 /**************************************************************************
3324 DISABLE - Turn off ethernet interface
3325 ***************************************************************************/
3326 static void etherfabric_disable ( struct nic *nic ) {
3327 struct efab_nic *efab = nic->priv_data;
3328
3329 efab->op->reset ( efab );
3330 if ( efab->membase )
3331 iounmap ( efab->membase );
3332 }
3333
3334 /**************************************************************************
3335 IRQ - handle interrupts
3336 ***************************************************************************/
3337 static void etherfabric_irq ( struct nic *nic, irq_action_t action ) {
3338 struct efab_nic *efab = nic->priv_data;
3339
3340 switch ( action ) {
3341 case DISABLE :
3342 efab->op->mask_irq ( efab, 1 );
3343 break;
3344 case ENABLE :
3345 efab->op->mask_irq ( efab, 0 );
3346 break;
3347 case FORCE :
3348 /* Force NIC to generate a receive interrupt */
3349 efab->op->generate_irq ( efab );
3350 break;
3351 }
3352
3353 return;
3354 }
3355
3356 static struct nic_operations etherfabric_operations = {
3357 .connect = dummy_connect,
3358 .poll = etherfabric_poll,
3359 .transmit = etherfabric_transmit,
3360 .irq = etherfabric_irq,
3361 };
3362
3363 /**************************************************************************
3364 PROBE - Look for an adapter, this routine's visible to the outside
3365 ***************************************************************************/
3366 static int etherfabric_probe ( struct nic *nic, struct pci_device *pci ) {
3367 static struct efab_nic efab;
3368 static int nic_port = 1;
3369 struct efab_buffers *buffers;
3370 int i;
3371
3372 /* Set up our private data structure */
3373 nic->priv_data = &efab;
3374 memset ( &efab, 0, sizeof ( efab ) );
3375 memset ( &efab_buffers, 0, sizeof ( efab_buffers ) );
3376
3377 /* Hook in appropriate operations table. Do this early. */
3378 if ( pci->device == EF1002_DEVID ) {
3379 efab.op = &ef1002_operations;
3380 } else {
3381 efab.op = &falcon_operations;
3382 }
3383
3384 /* Initialise efab data structure */
3385 efab.pci = pci;
3386 buffers = ( ( struct efab_buffers * )
3387 ( ( ( void * ) &efab_buffers ) +
3388 ( - virt_to_bus ( &efab_buffers ) ) % EFAB_BUF_ALIGN ) );
3389 efab.eventq = buffers->eventq;
3390 efab.txd = buffers->txd;
3391 efab.rxd = buffers->rxd;
3392 efab.tx_buf.addr = buffers->tx_buf;
3393 for ( i = 0 ; i < EFAB_RX_BUFS ; i++ ) {
3394 efab.rx_bufs[i].addr = buffers->rx_buf[i];
3395 }
3396
3397 /* Enable the PCI device */
3398 adjust_pci_device ( pci );
3399 nic->ioaddr = pci->ioaddr & ~3;
3400 nic->irqno = pci->irq;
3401
3402 /* Get iobase/membase */
3403 efab.iobase = nic->ioaddr;
3404 efab.op->get_membase ( &efab );
3405
3406 /* Switch NIC ports (i.e. try different ports on each probe) */
3407 nic_port = 1 - nic_port;
3408 efab.port = nic_port;
3409
3410 /* Initialise hardware */
3411 if ( ! efab_init_nic ( &efab ) )
3412 return 0;
3413 memcpy ( nic->node_addr, efab.mac_addr, ETH_ALEN );
3414
3415 /* point to NIC specific routines */
3416 nic->nic_op = &etherfabric_operations;
3417
3418 return 1;
3419 }
3420
3421 static struct pci_device_id etherfabric_nics[] = {
3422 PCI_ROM(0x1924, 0xC101, "ef1002", "EtherFabric EF1002"),
3423 PCI_ROM(0x1924, 0x0703, "falcon", "EtherFabric Falcon"),
3424 };
3425
3426 PCI_DRIVER ( etherfabric_driver, etherfabric_nics, PCI_NO_CLASS );
3427
3428 DRIVER ( "EFAB", nic_driver, pci_driver, etherfabric_driver,
3429 etherfabric_probe, etherfabric_disable );
3430
3431 /*
3432 * Local variables:
3433 * c-basic-offset: 8
3434 * c-indent-level: 8
3435 * tab-width: 8
3436 * End:
3437 */
gPXE - free pxe roms