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Add errfile definition for new e1000.c
[gpxe.git] / src / drivers / net / forcedeth.c
blob2008c39a1523423aad3460105f8d28437ace2f75
1 /**************************************************************************
2 * forcedeth.c -- Etherboot device driver for the NVIDIA nForce
3 * media access controllers.
4 *
5 * Note: This driver is based on the Linux driver that was based on
6 * a cleanroom reimplementation which was based on reverse
7 * engineered documentation written by Carl-Daniel Hailfinger
8 * and Andrew de Quincey. It's neither supported nor endorsed
9 * by NVIDIA Corp. Use at your own risk.
10 *
11 * Written 2004 by Timothy Legge <tlegge@rogers.com>
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2 of the License, or
16 * (at your option) any later version.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
26 *
27 * Portions of this code based on:
28 * forcedeth: Ethernet driver for NVIDIA nForce media access controllers:
29 *
30 * (C) 2003 Manfred Spraul
31 * See Linux Driver for full information
32 *
33 * Linux Driver Version 0.30, 25 Sep 2004
34 * Linux Kernel 2.6.10
35 *
36 *
37 * REVISION HISTORY:
38 * ================
39 * v1.0 01-31-2004 timlegge Initial port of Linux driver
40 * v1.1 02-03-2004 timlegge Large Clean up, first release
41 * v1.2 05-14-2005 timlegge Add Linux 0.22 to .030 features
42 *
43 * Indent Options: indent -kr -i8
44 ***************************************************************************/
45
46 /* to get some global routines like printf */
47 #include "etherboot.h"
48 /* to get the interface to the body of the program */
49 #include "nic.h"
50 /* to get the PCI support functions, if this is a PCI NIC */
51 #include <gpxe/pci.h>
52 /* Include timer support functions */
53 #include <gpxe/ethernet.h>
54 #include "timer.h"
55 #include "mii.h"
56
57 #define drv_version "v1.2"
58 #define drv_date "05-14-2005"
59
60 //#define TFTM_DEBUG
61 #ifdef TFTM_DEBUG
62 #define dprintf(x) printf x
63 #else
64 #define dprintf(x)
65 #endif
66
67 #define ETH_DATA_LEN 1500
68
69 /* Condensed operations for readability. */
70 #define virt_to_le32desc(addr) cpu_to_le32(virt_to_bus(addr))
71 #define le32desc_to_virt(addr) bus_to_virt(le32_to_cpu(addr))
72
73 static unsigned long BASE;
74 /* NIC specific static variables go here */
75 #define PCI_DEVICE_ID_NVIDIA_NVENET_1 0x01c3
76 #define PCI_DEVICE_ID_NVIDIA_NVENET_2 0x0066
77 #define PCI_DEVICE_ID_NVIDIA_NVENET_4 0x0086
78 #define PCI_DEVICE_ID_NVIDIA_NVENET_5 0x008c
79 #define PCI_DEVICE_ID_NVIDIA_NVENET_3 0x00d6
80 #define PCI_DEVICE_ID_NVIDIA_NVENET_7 0x00df
81 #define PCI_DEVICE_ID_NVIDIA_NVENET_6 0x00e6
82 #define PCI_DEVICE_ID_NVIDIA_NVENET_8 0x0056
83 #define PCI_DEVICE_ID_NVIDIA_NVENET_9 0x0057
84 #define PCI_DEVICE_ID_NVIDIA_NVENET_10 0x0037
85 #define PCI_DEVICE_ID_NVIDIA_NVENET_11 0x0038
86
87
88 /*
89 * Hardware access:
90 */
91
92 #define DEV_NEED_LASTPACKET1 0x0001 /* set LASTPACKET1 in tx flags */
93 #define DEV_IRQMASK_1 0x0002 /* use NVREG_IRQMASK_WANTED_1 for irq mask */
94 #define DEV_IRQMASK_2 0x0004 /* use NVREG_IRQMASK_WANTED_2 for irq mask */
95 #define DEV_NEED_TIMERIRQ 0x0008 /* set the timer irq flag in the irq mask */
96 #define DEV_NEED_LINKTIMER 0x0010 /* poll link settings. Relies on the timer irq */
97
98 enum {
99 NvRegIrqStatus = 0x000,
100 #define NVREG_IRQSTAT_MIIEVENT 0040
101 #define NVREG_IRQSTAT_MASK 0x1ff
102 NvRegIrqMask = 0x004,
103 #define NVREG_IRQ_RX_ERROR 0x0001
104 #define NVREG_IRQ_RX 0x0002
105 #define NVREG_IRQ_RX_NOBUF 0x0004
106 #define NVREG_IRQ_TX_ERR 0x0008
107 #define NVREG_IRQ_TX2 0x0010
108 #define NVREG_IRQ_TIMER 0x0020
109 #define NVREG_IRQ_LINK 0x0040
110 #define NVREG_IRQ_TX1 0x0100
111 #define NVREG_IRQMASK_WANTED_1 0x005f
112 #define NVREG_IRQMASK_WANTED_2 0x0147
113 #define NVREG_IRQ_UNKNOWN (~(NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_TX_ERR|NVREG_IRQ_TX2|NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_TX1))
114
115 NvRegUnknownSetupReg6 = 0x008,
116 #define NVREG_UNKSETUP6_VAL 3
117
118 /*
119 * NVREG_POLL_DEFAULT is the interval length of the timer source on the nic
120 * NVREG_POLL_DEFAULT=97 would result in an interval length of 1 ms
121 */
122 NvRegPollingInterval = 0x00c,
123 #define NVREG_POLL_DEFAULT 970
124 NvRegMisc1 = 0x080,
125 #define NVREG_MISC1_HD 0x02
126 #define NVREG_MISC1_FORCE 0x3b0f3c
127
128 NvRegTransmitterControl = 0x084,
129 #define NVREG_XMITCTL_START 0x01
130 NvRegTransmitterStatus = 0x088,
131 #define NVREG_XMITSTAT_BUSY 0x01
132
133 NvRegPacketFilterFlags = 0x8c,
134 #define NVREG_PFF_ALWAYS 0x7F0008
135 #define NVREG_PFF_PROMISC 0x80
136 #define NVREG_PFF_MYADDR 0x20
137
138 NvRegOffloadConfig = 0x90,
139 #define NVREG_OFFLOAD_HOMEPHY 0x601
140 #define NVREG_OFFLOAD_NORMAL RX_NIC_BUFSIZE
141 NvRegReceiverControl = 0x094,
142 #define NVREG_RCVCTL_START 0x01
143 NvRegReceiverStatus = 0x98,
144 #define NVREG_RCVSTAT_BUSY 0x01
145
146 NvRegRandomSeed = 0x9c,
147 #define NVREG_RNDSEED_MASK 0x00ff
148 #define NVREG_RNDSEED_FORCE 0x7f00
149 #define NVREG_RNDSEED_FORCE2 0x2d00
150 #define NVREG_RNDSEED_FORCE3 0x7400
151
152 NvRegUnknownSetupReg1 = 0xA0,
153 #define NVREG_UNKSETUP1_VAL 0x16070f
154 NvRegUnknownSetupReg2 = 0xA4,
155 #define NVREG_UNKSETUP2_VAL 0x16
156 NvRegMacAddrA = 0xA8,
157 NvRegMacAddrB = 0xAC,
158 NvRegMulticastAddrA = 0xB0,
159 #define NVREG_MCASTADDRA_FORCE 0x01
160 NvRegMulticastAddrB = 0xB4,
161 NvRegMulticastMaskA = 0xB8,
162 NvRegMulticastMaskB = 0xBC,
163
164 NvRegPhyInterface = 0xC0,
165 #define PHY_RGMII 0x10000000
166
167 NvRegTxRingPhysAddr = 0x100,
168 NvRegRxRingPhysAddr = 0x104,
169 NvRegRingSizes = 0x108,
170 #define NVREG_RINGSZ_TXSHIFT 0
171 #define NVREG_RINGSZ_RXSHIFT 16
172 NvRegUnknownTransmitterReg = 0x10c,
173 NvRegLinkSpeed = 0x110,
174 #define NVREG_LINKSPEED_FORCE 0x10000
175 #define NVREG_LINKSPEED_10 1000
176 #define NVREG_LINKSPEED_100 100
177 #define NVREG_LINKSPEED_1000 50
178 NvRegUnknownSetupReg5 = 0x130,
179 #define NVREG_UNKSETUP5_BIT31 (1<<31)
180 NvRegUnknownSetupReg3 = 0x13c,
181 #define NVREG_UNKSETUP3_VAL1 0x200010
182 NvRegTxRxControl = 0x144,
183 #define NVREG_TXRXCTL_KICK 0x0001
184 #define NVREG_TXRXCTL_BIT1 0x0002
185 #define NVREG_TXRXCTL_BIT2 0x0004
186 #define NVREG_TXRXCTL_IDLE 0x0008
187 #define NVREG_TXRXCTL_RESET 0x0010
188 #define NVREG_TXRXCTL_RXCHECK 0x0400
189 NvRegMIIStatus = 0x180,
190 #define NVREG_MIISTAT_ERROR 0x0001
191 #define NVREG_MIISTAT_LINKCHANGE 0x0008
192 #define NVREG_MIISTAT_MASK 0x000f
193 #define NVREG_MIISTAT_MASK2 0x000f
194 NvRegUnknownSetupReg4 = 0x184,
195 #define NVREG_UNKSETUP4_VAL 8
196
197 NvRegAdapterControl = 0x188,
198 #define NVREG_ADAPTCTL_START 0x02
199 #define NVREG_ADAPTCTL_LINKUP 0x04
200 #define NVREG_ADAPTCTL_PHYVALID 0x40000
201 #define NVREG_ADAPTCTL_RUNNING 0x100000
202 #define NVREG_ADAPTCTL_PHYSHIFT 24
203 NvRegMIISpeed = 0x18c,
204 #define NVREG_MIISPEED_BIT8 (1<<8)
205 #define NVREG_MIIDELAY 5
206 NvRegMIIControl = 0x190,
207 #define NVREG_MIICTL_INUSE 0x08000
208 #define NVREG_MIICTL_WRITE 0x00400
209 #define NVREG_MIICTL_ADDRSHIFT 5
210 NvRegMIIData = 0x194,
211 NvRegWakeUpFlags = 0x200,
212 #define NVREG_WAKEUPFLAGS_VAL 0x7770
213 #define NVREG_WAKEUPFLAGS_BUSYSHIFT 24
214 #define NVREG_WAKEUPFLAGS_ENABLESHIFT 16
215 #define NVREG_WAKEUPFLAGS_D3SHIFT 12
216 #define NVREG_WAKEUPFLAGS_D2SHIFT 8
217 #define NVREG_WAKEUPFLAGS_D1SHIFT 4
218 #define NVREG_WAKEUPFLAGS_D0SHIFT 0
219 #define NVREG_WAKEUPFLAGS_ACCEPT_MAGPAT 0x01
220 #define NVREG_WAKEUPFLAGS_ACCEPT_WAKEUPPAT 0x02
221 #define NVREG_WAKEUPFLAGS_ACCEPT_LINKCHANGE 0x04
222 #define NVREG_WAKEUPFLAGS_ENABLE 0x1111
223
224 NvRegPatternCRC = 0x204,
225 NvRegPatternMask = 0x208,
226 NvRegPowerCap = 0x268,
227 #define NVREG_POWERCAP_D3SUPP (1<<30)
228 #define NVREG_POWERCAP_D2SUPP (1<<26)
229 #define NVREG_POWERCAP_D1SUPP (1<<25)
230 NvRegPowerState = 0x26c,
231 #define NVREG_POWERSTATE_POWEREDUP 0x8000
232 #define NVREG_POWERSTATE_VALID 0x0100
233 #define NVREG_POWERSTATE_MASK 0x0003
234 #define NVREG_POWERSTATE_D0 0x0000
235 #define NVREG_POWERSTATE_D1 0x0001
236 #define NVREG_POWERSTATE_D2 0x0002
237 #define NVREG_POWERSTATE_D3 0x0003
238 };
239
240 #define FLAG_MASK_V1 0xffff0000
241 #define FLAG_MASK_V2 0xffffc000
242 #define LEN_MASK_V1 (0xffffffff ^ FLAG_MASK_V1)
243 #define LEN_MASK_V2 (0xffffffff ^ FLAG_MASK_V2)
244
245 #define NV_TX_LASTPACKET (1<<16)
246 #define NV_TX_RETRYERROR (1<<19)
247 #define NV_TX_LASTPACKET1 (1<<24)
248 #define NV_TX_DEFERRED (1<<26)
249 #define NV_TX_CARRIERLOST (1<<27)
250 #define NV_TX_LATECOLLISION (1<<28)
251 #define NV_TX_UNDERFLOW (1<<29)
252 #define NV_TX_ERROR (1<<30)
253 #define NV_TX_VALID (1<<31)
254
255 #define NV_TX2_LASTPACKET (1<<29)
256 #define NV_TX2_RETRYERROR (1<<18)
257 #define NV_TX2_LASTPACKET1 (1<<23)
258 #define NV_TX2_DEFERRED (1<<25)
259 #define NV_TX2_CARRIERLOST (1<<26)
260 #define NV_TX2_LATECOLLISION (1<<27)
261 #define NV_TX2_UNDERFLOW (1<<28)
262 /* error and valid are the same for both */
263 #define NV_TX2_ERROR (1<<30)
264 #define NV_TX2_VALID (1<<31)
265
266 #define NV_RX_DESCRIPTORVALID (1<<16)
267 #define NV_RX_MISSEDFRAME (1<<17)
268 #define NV_RX_SUBSTRACT1 (1<<18)
269 #define NV_RX_ERROR1 (1<<23)
270 #define NV_RX_ERROR2 (1<<24)
271 #define NV_RX_ERROR3 (1<<25)
272 #define NV_RX_ERROR4 (1<<26)
273 #define NV_RX_CRCERR (1<<27)
274 #define NV_RX_OVERFLOW (1<<28)
275 #define NV_RX_FRAMINGERR (1<<29)
276 #define NV_RX_ERROR (1<<30)
277 #define NV_RX_AVAIL (1<<31)
278
279 #define NV_RX2_CHECKSUMMASK (0x1C000000)
280 #define NV_RX2_CHECKSUMOK1 (0x10000000)
281 #define NV_RX2_CHECKSUMOK2 (0x14000000)
282 #define NV_RX2_CHECKSUMOK3 (0x18000000)
283 #define NV_RX2_DESCRIPTORVALID (1<<29)
284 #define NV_RX2_SUBSTRACT1 (1<<25)
285 #define NV_RX2_ERROR1 (1<<18)
286 #define NV_RX2_ERROR2 (1<<19)
287 #define NV_RX2_ERROR3 (1<<20)
288 #define NV_RX2_ERROR4 (1<<21)
289 #define NV_RX2_CRCERR (1<<22)
290 #define NV_RX2_OVERFLOW (1<<23)
291 #define NV_RX2_FRAMINGERR (1<<24)
292 /* error and avail are the same for both */
293 #define NV_RX2_ERROR (1<<30)
294 #define NV_RX2_AVAIL (1<<31)
295
296 /* Miscelaneous hardware related defines: */
297 #define NV_PCI_REGSZ 0x270
298
299 /* various timeout delays: all in usec */
300 #define NV_TXRX_RESET_DELAY 4
301 #define NV_TXSTOP_DELAY1 10
302 #define NV_TXSTOP_DELAY1MAX 500000
303 #define NV_TXSTOP_DELAY2 100
304 #define NV_RXSTOP_DELAY1 10
305 #define NV_RXSTOP_DELAY1MAX 500000
306 #define NV_RXSTOP_DELAY2 100
307 #define NV_SETUP5_DELAY 5
308 #define NV_SETUP5_DELAYMAX 50000
309 #define NV_POWERUP_DELAY 5
310 #define NV_POWERUP_DELAYMAX 5000
311 #define NV_MIIBUSY_DELAY 50
312 #define NV_MIIPHY_DELAY 10
313 #define NV_MIIPHY_DELAYMAX 10000
314
315 #define NV_WAKEUPPATTERNS 5
316 #define NV_WAKEUPMASKENTRIES 4
317
318 /* General driver defaults */
319 #define NV_WATCHDOG_TIMEO (5*HZ)
320
321 #define RX_RING 4
322 #define TX_RING 2
323
324 /*
325 * If your nic mysteriously hangs then try to reduce the limits
326 * to 1/0: It might be required to set NV_TX_LASTPACKET in the
327 * last valid ring entry. But this would be impossible to
328 * implement - probably a disassembly error.
329 */
330 #define TX_LIMIT_STOP 63
331 #define TX_LIMIT_START 62
332
333 /* rx/tx mac addr + type + vlan + align + slack*/
334 #define RX_NIC_BUFSIZE (ETH_DATA_LEN + 64)
335 /* even more slack */
336 #define RX_ALLOC_BUFSIZE (ETH_DATA_LEN + 128)
337
338 #define OOM_REFILL (1+HZ/20)
339 #define POLL_WAIT (1+HZ/100)
340 #define LINK_TIMEOUT (3*HZ)
341
342 /*
343 * desc_ver values:
344 * This field has two purposes:
345 * - Newer nics uses a different ring layout. The layout is selected by
346 * comparing np->desc_ver with DESC_VER_xy.
347 * - It contains bits that are forced on when writing to NvRegTxRxControl.
348 */
349 #define DESC_VER_1 0x0
350 #define DESC_VER_2 (0x02100|NVREG_TXRXCTL_RXCHECK)
351
352 /* PHY defines */
353 #define PHY_OUI_MARVELL 0x5043
354 #define PHY_OUI_CICADA 0x03f1
355 #define PHYID1_OUI_MASK 0x03ff
356 #define PHYID1_OUI_SHFT 6
357 #define PHYID2_OUI_MASK 0xfc00
358 #define PHYID2_OUI_SHFT 10
359 #define PHY_INIT1 0x0f000
360 #define PHY_INIT2 0x0e00
361 #define PHY_INIT3 0x01000
362 #define PHY_INIT4 0x0200
363 #define PHY_INIT5 0x0004
364 #define PHY_INIT6 0x02000
365 #define PHY_GIGABIT 0x0100
366
367 #define PHY_TIMEOUT 0x1
368 #define PHY_ERROR 0x2
369
370 #define PHY_100 0x1
371 #define PHY_1000 0x2
372 #define PHY_HALF 0x100
373
374 /* FIXME: MII defines that should be added to <linux/mii.h> */
375 #define MII_1000BT_CR 0x09
376 #define MII_1000BT_SR 0x0a
377 #define ADVERTISE_1000FULL 0x0200
378 #define ADVERTISE_1000HALF 0x0100
379 #define LPA_1000FULL 0x0800
380 #define LPA_1000HALF 0x0400
381
382 /* Big endian: should work, but is untested */
383 struct ring_desc {
384 u32 PacketBuffer;
385 u32 FlagLen;
386 };
387
388
389 /* Define the TX and RX Descriptor and Buffers */
390 struct {
391 struct ring_desc tx_ring[TX_RING];
392 unsigned char txb[TX_RING * RX_NIC_BUFSIZE];
393 struct ring_desc rx_ring[RX_RING];
394 unsigned char rxb[RX_RING * RX_NIC_BUFSIZE];
395 } forcedeth_bufs __shared;
396 #define tx_ring forcedeth_bufs.tx_ring
397 #define rx_ring forcedeth_bufs.rx_ring
398 #define txb forcedeth_bufs.txb
399 #define rxb forcedeth_bufs.rxb
400
401 /* Private Storage for the NIC */
402 static struct forcedeth_private {
403 /* General data:
404 * Locking: spin_lock(&np->lock); */
405 int in_shutdown;
406 u32 linkspeed;
407 int duplex;
408 int phyaddr;
409 int wolenabled;
410 unsigned int phy_oui;
411 u16 gigabit;
412
413 /* General data: RO fields */
414 u8 *ring_addr;
415 u32 orig_mac[2];
416 u32 irqmask;
417 u32 desc_ver;
418 /* rx specific fields.
419 * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
420 */
421 unsigned int cur_rx, refill_rx;
422
423 /*
424 * tx specific fields.
425 */
426 unsigned int next_tx, nic_tx;
427 u32 tx_flags;
428 } npx;
429
430 static struct forcedeth_private *np;
431
432 static inline void pci_push(u8 * base)
433 {
434 /* force out pending posted writes */
435 readl(base);
436 }
437
438 static inline u32 nv_descr_getlength(struct ring_desc *prd, u32 v)
439 {
440 return le32_to_cpu(prd->FlagLen)
441 & ((v == DESC_VER_1) ? LEN_MASK_V1 : LEN_MASK_V2);
442 }
443
444 static int reg_delay(int offset, u32 mask,
445 u32 target, int delay, int delaymax, const char *msg)
446 {
447 u8 *base = (u8 *) BASE;
448
449 pci_push(base);
450 do {
451 udelay(delay);
452 delaymax -= delay;
453 if (delaymax < 0) {
454 if (msg)
455 printf(msg);
456 return 1;
457 }
458 } while ((readl(base + offset) & mask) != target);
459 return 0;
460 }
461
462 #define MII_READ (-1)
463 #define MII_PHYSID1 0x02 /* PHYS ID 1 */
464 #define MII_PHYSID2 0x03 /* PHYS ID 2 */
465 #define MII_BMCR 0x00 /* Basic mode control register */
466 #define MII_BMSR 0x01 /* Basic mode status register */
467 #define MII_ADVERTISE 0x04 /* Advertisement control reg */
468 #define MII_LPA 0x05 /* Link partner ability reg */
469
470 #define BMSR_ANEGCOMPLETE 0x0020 /* Auto-negotiation complete */
471
472 /* Link partner ability register. */
473 #define LPA_SLCT 0x001f /* Same as advertise selector */
474 #define LPA_10HALF 0x0020 /* Can do 10mbps half-duplex */
475 #define LPA_10FULL 0x0040 /* Can do 10mbps full-duplex */
476 #define LPA_100HALF 0x0080 /* Can do 100mbps half-duplex */
477 #define LPA_100FULL 0x0100 /* Can do 100mbps full-duplex */
478 #define LPA_100BASE4 0x0200 /* Can do 100mbps 4k packets */
479 #define LPA_RESV 0x1c00 /* Unused... */
480 #define LPA_RFAULT 0x2000 /* Link partner faulted */
481 #define LPA_LPACK 0x4000 /* Link partner acked us */
482 #define LPA_NPAGE 0x8000 /* Next page bit */
483
484 /* mii_rw: read/write a register on the PHY.
485 *
486 * Caller must guarantee serialization
487 */
488 static int mii_rw(struct nic *nic __unused, int addr, int miireg,
489 int value)
490 {
491 u8 *base = (u8 *) BASE;
492 u32 reg;
493 int retval;
494
495 writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus);
496
497 reg = readl(base + NvRegMIIControl);
498 if (reg & NVREG_MIICTL_INUSE) {
499 writel(NVREG_MIICTL_INUSE, base + NvRegMIIControl);
500 udelay(NV_MIIBUSY_DELAY);
501 }
502
503 reg =
504 (addr << NVREG_MIICTL_ADDRSHIFT) | miireg;
505 if (value != MII_READ) {
506 writel(value, base + NvRegMIIData);
507 reg |= NVREG_MIICTL_WRITE;
508 }
509 writel(reg, base + NvRegMIIControl);
510
511 if (reg_delay(NvRegMIIControl, NVREG_MIICTL_INUSE, 0,
512 NV_MIIPHY_DELAY, NV_MIIPHY_DELAYMAX, NULL)) {
513 dprintf(("mii_rw of reg %d at PHY %d timed out.\n",
514 miireg, addr));
515 retval = -1;
516 } else if (value != MII_READ) {
517 /* it was a write operation - fewer failures are detectable */
518 dprintf(("mii_rw wrote 0x%x to reg %d at PHY %d\n",
519 value, miireg, addr));
520 retval = 0;
521 } else if (readl(base + NvRegMIIStatus) & NVREG_MIISTAT_ERROR) {
522 dprintf(("mii_rw of reg %d at PHY %d failed.\n",
523 miireg, addr));
524 retval = -1;
525 } else {
526 retval = readl(base + NvRegMIIData);
527 dprintf(("mii_rw read from reg %d at PHY %d: 0x%x.\n",
528 miireg, addr, retval));
529 }
530 return retval;
531 }
532
533 static int phy_reset(struct nic *nic)
534 {
535
536 u32 miicontrol;
537 unsigned int tries = 0;
538
539 miicontrol = mii_rw(nic, np->phyaddr, MII_BMCR, MII_READ);
540 miicontrol |= BMCR_RESET;
541 if (mii_rw(nic, np->phyaddr, MII_BMCR, miicontrol)) {
542 return -1;
543 }
544
545 /* wait for 500ms */
546 mdelay(500);
547
548 /* must wait till reset is deasserted */
549 while (miicontrol & BMCR_RESET) {
550 mdelay(10);
551 miicontrol = mii_rw(nic, np->phyaddr, MII_BMCR, MII_READ);
552 /* FIXME: 100 tries seem excessive */
553 if (tries++ > 100)
554 return -1;
555 }
556 return 0;
557 }
558
559 static int phy_init(struct nic *nic)
560 {
561 u8 *base = (u8 *) BASE;
562 u32 phyinterface, phy_reserved, mii_status, mii_control,
563 mii_control_1000, reg;
564
565 /* set advertise register */
566 reg = mii_rw(nic, np->phyaddr, MII_ADVERTISE, MII_READ);
567 reg |=
568 (ADVERTISE_10HALF | ADVERTISE_10FULL | ADVERTISE_100HALF |
569 ADVERTISE_100FULL | 0x800 | 0x400);
570 if (mii_rw(nic, np->phyaddr, MII_ADVERTISE, reg)) {
571 printf("phy write to advertise failed.\n");
572 return PHY_ERROR;
573 }
574
575 /* get phy interface type */
576 phyinterface = readl(base + NvRegPhyInterface);
577
578 /* see if gigabit phy */
579 mii_status = mii_rw(nic, np->phyaddr, MII_BMSR, MII_READ);
580
581 if (mii_status & PHY_GIGABIT) {
582 np->gigabit = PHY_GIGABIT;
583 mii_control_1000 =
584 mii_rw(nic, np->phyaddr, MII_1000BT_CR, MII_READ);
585 mii_control_1000 &= ~ADVERTISE_1000HALF;
586 if (phyinterface & PHY_RGMII)
587 mii_control_1000 |= ADVERTISE_1000FULL;
588 else
589 mii_control_1000 &= ~ADVERTISE_1000FULL;
590
591 if (mii_rw
592 (nic, np->phyaddr, MII_1000BT_CR, mii_control_1000)) {
593 printf("phy init failed.\n");
594 return PHY_ERROR;
595 }
596 } else
597 np->gigabit = 0;
598
599 /* reset the phy */
600 if (phy_reset(nic)) {
601 printf("phy reset failed\n");
602 return PHY_ERROR;
603 }
604
605 /* phy vendor specific configuration */
606 if ((np->phy_oui == PHY_OUI_CICADA) && (phyinterface & PHY_RGMII)) {
607 phy_reserved =
608 mii_rw(nic, np->phyaddr, MII_RESV1, MII_READ);
609 phy_reserved &= ~(PHY_INIT1 | PHY_INIT2);
610 phy_reserved |= (PHY_INIT3 | PHY_INIT4);
611 if (mii_rw(nic, np->phyaddr, MII_RESV1, phy_reserved)) {
612 printf("phy init failed.\n");
613 return PHY_ERROR;
614 }
615 phy_reserved =
616 mii_rw(nic, np->phyaddr, MII_NCONFIG, MII_READ);
617 phy_reserved |= PHY_INIT5;
618 if (mii_rw(nic, np->phyaddr, MII_NCONFIG, phy_reserved)) {
619 printf("phy init failed.\n");
620 return PHY_ERROR;
621 }
622 }
623 if (np->phy_oui == PHY_OUI_CICADA) {
624 phy_reserved =
625 mii_rw(nic, np->phyaddr, MII_SREVISION, MII_READ);
626 phy_reserved |= PHY_INIT6;
627 if (mii_rw(nic, np->phyaddr, MII_SREVISION, phy_reserved)) {
628 printf("phy init failed.\n");
629 return PHY_ERROR;
630 }
631 }
632
633 /* restart auto negotiation */
634 mii_control = mii_rw(nic, np->phyaddr, MII_BMCR, MII_READ);
635 mii_control |= (BMCR_ANRESTART | BMCR_ANENABLE);
636 if (mii_rw(nic, np->phyaddr, MII_BMCR, mii_control)) {
637 return PHY_ERROR;
638 }
639
640 return 0;
641 }
642
643 static void start_rx(struct nic *nic __unused)
644 {
645 u8 *base = (u8 *) BASE;
646
647 dprintf(("start_rx\n"));
648 /* Already running? Stop it. */
649 if (readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) {
650 writel(0, base + NvRegReceiverControl);
651 pci_push(base);
652 }
653 writel(np->linkspeed, base + NvRegLinkSpeed);
654 pci_push(base);
655 writel(NVREG_RCVCTL_START, base + NvRegReceiverControl);
656 pci_push(base);
657 }
658
659 static void stop_rx(void)
660 {
661 u8 *base = (u8 *) BASE;
662
663 dprintf(("stop_rx\n"));
664 writel(0, base + NvRegReceiverControl);
665 reg_delay(NvRegReceiverStatus, NVREG_RCVSTAT_BUSY, 0,
666 NV_RXSTOP_DELAY1, NV_RXSTOP_DELAY1MAX,
667 "stop_rx: ReceiverStatus remained busy");
668
669 udelay(NV_RXSTOP_DELAY2);
670 writel(0, base + NvRegLinkSpeed);
671 }
672
673 static void start_tx(struct nic *nic __unused)
674 {
675 u8 *base = (u8 *) BASE;
676
677 dprintf(("start_tx\n"));
678 writel(NVREG_XMITCTL_START, base + NvRegTransmitterControl);
679 pci_push(base);
680 }
681
682 static void stop_tx(void)
683 {
684 u8 *base = (u8 *) BASE;
685
686 dprintf(("stop_tx\n"));
687 writel(0, base + NvRegTransmitterControl);
688 reg_delay(NvRegTransmitterStatus, NVREG_XMITSTAT_BUSY, 0,
689 NV_TXSTOP_DELAY1, NV_TXSTOP_DELAY1MAX,
690 "stop_tx: TransmitterStatus remained busy");
691
692 udelay(NV_TXSTOP_DELAY2);
693 writel(0, base + NvRegUnknownTransmitterReg);
694 }
695
696
697 static void txrx_reset(struct nic *nic __unused)
698 {
699 u8 *base = (u8 *) BASE;
700
701 dprintf(("txrx_reset\n"));
702 writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->desc_ver,
703 base + NvRegTxRxControl);
704
705 pci_push(base);
706 udelay(NV_TXRX_RESET_DELAY);
707 writel(NVREG_TXRXCTL_BIT2 | np->desc_ver, base + NvRegTxRxControl);
708 pci_push(base);
709 }
710
711 /*
712 * alloc_rx: fill rx ring entries.
713 * Return 1 if the allocations for the skbs failed and the
714 * rx engine is without Available descriptors
715 */
716 static int alloc_rx(struct nic *nic __unused)
717 {
718 unsigned int refill_rx = np->refill_rx;
719 int i;
720 //while (np->cur_rx != refill_rx) {
721 for (i = 0; i < RX_RING; i++) {
722 //int nr = refill_rx % RX_RING;
723 rx_ring[i].PacketBuffer =
724 virt_to_le32desc(&rxb[i * RX_NIC_BUFSIZE]);
725 wmb();
726 rx_ring[i].FlagLen =
727 cpu_to_le32(RX_NIC_BUFSIZE | NV_RX_AVAIL);
728 /* printf("alloc_rx: Packet %d marked as Available\n",
729 refill_rx); */
730 refill_rx++;
731 }
732 np->refill_rx = refill_rx;
733 if (np->cur_rx - refill_rx == RX_RING)
734 return 1;
735 return 0;
736 }
737
738 static int update_linkspeed(struct nic *nic)
739 {
740 int adv, lpa;
741 u32 newls;
742 int newdup = np->duplex;
743 u32 mii_status;
744 int retval = 0;
745 u32 control_1000, status_1000, phyreg;
746 u8 *base = (u8 *) BASE;
747 int i;
748
749 /* BMSR_LSTATUS is latched, read it twice:
750 * we want the current value.
751 */
752 mii_rw(nic, np->phyaddr, MII_BMSR, MII_READ);
753 mii_status = mii_rw(nic, np->phyaddr, MII_BMSR, MII_READ);
754
755 #if 1
756 //yhlu
757 for(i=0;i<30;i++) {
758 mii_status = mii_rw(nic, np->phyaddr, MII_BMSR, MII_READ);
759 if((mii_status & BMSR_LSTATUS) && (mii_status & BMSR_ANEGCOMPLETE)) break;
760 mdelay(100);
761 }
762 #endif
763
764 if (!(mii_status & BMSR_LSTATUS)) {
765 printf
766 ("no link detected by phy - falling back to 10HD.\n");
767 newls = NVREG_LINKSPEED_FORCE | NVREG_LINKSPEED_10;
768 newdup = 0;
769 retval = 0;
770 goto set_speed;
771 }
772
773 /* check auto negotiation is complete */
774 if (!(mii_status & BMSR_ANEGCOMPLETE)) {
775 /* still in autonegotiation - configure nic for 10 MBit HD and wait. */
776 newls = NVREG_LINKSPEED_FORCE | NVREG_LINKSPEED_10;
777 newdup = 0;
778 retval = 0;
779 printf("autoneg not completed - falling back to 10HD.\n");
780 goto set_speed;
781 }
782
783 retval = 1;
784 if (np->gigabit == PHY_GIGABIT) {
785 control_1000 =
786 mii_rw(nic, np->phyaddr, MII_1000BT_CR, MII_READ);
787 status_1000 =
788 mii_rw(nic, np->phyaddr, MII_1000BT_SR, MII_READ);
789
790 if ((control_1000 & ADVERTISE_1000FULL) &&
791 (status_1000 & LPA_1000FULL)) {
792 printf
793 ("update_linkspeed: GBit ethernet detected.\n");
794 newls =
795 NVREG_LINKSPEED_FORCE | NVREG_LINKSPEED_1000;
796 newdup = 1;
797 goto set_speed;
798 }
799 }
800
801 adv = mii_rw(nic, np->phyaddr, MII_ADVERTISE, MII_READ);
802 lpa = mii_rw(nic, np->phyaddr, MII_LPA, MII_READ);
803 dprintf(("update_linkspeed: PHY advertises 0x%hX, lpa 0x%hX.\n",
804 adv, lpa));
805
806 /* FIXME: handle parallel detection properly, handle gigabit ethernet */
807 lpa = lpa & adv;
808 if (lpa & LPA_100FULL) {
809 newls = NVREG_LINKSPEED_FORCE | NVREG_LINKSPEED_100;
810 newdup = 1;
811 } else if (lpa & LPA_100HALF) {
812 newls = NVREG_LINKSPEED_FORCE | NVREG_LINKSPEED_100;
813 newdup = 0;
814 } else if (lpa & LPA_10FULL) {
815 newls = NVREG_LINKSPEED_FORCE | NVREG_LINKSPEED_10;
816 newdup = 1;
817 } else if (lpa & LPA_10HALF) {
818 newls = NVREG_LINKSPEED_FORCE | NVREG_LINKSPEED_10;
819 newdup = 0;
820 } else {
821 printf("bad ability %hX - falling back to 10HD.\n", lpa);
822 newls = NVREG_LINKSPEED_FORCE | NVREG_LINKSPEED_10;
823 newdup = 0;
824 }
825
826 set_speed:
827 if (np->duplex == newdup && np->linkspeed == newls)
828 return retval;
829
830 dprintf(("changing link setting from %d/%s to %d/%s.\n",
831 np->linkspeed, np->duplex ? "Full-Duplex": "Half-Duplex", newls, newdup ? "Full-Duplex": "Half-Duplex"));
832
833 np->duplex = newdup;
834 np->linkspeed = newls;
835
836 if (np->gigabit == PHY_GIGABIT) {
837 phyreg = readl(base + NvRegRandomSeed);
838 phyreg &= ~(0x3FF00);
839 if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_10)
840 phyreg |= NVREG_RNDSEED_FORCE3;
841 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_100)
842 phyreg |= NVREG_RNDSEED_FORCE2;
843 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_1000)
844 phyreg |= NVREG_RNDSEED_FORCE;
845 writel(phyreg, base + NvRegRandomSeed);
846 }
847
848 phyreg = readl(base + NvRegPhyInterface);
849 phyreg &= ~(PHY_HALF | PHY_100 | PHY_1000);
850 if (np->duplex == 0)
851 phyreg |= PHY_HALF;
852 if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_100)
853 phyreg |= PHY_100;
854 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_1000)
855 phyreg |= PHY_1000;
856 writel(phyreg, base + NvRegPhyInterface);
857
858 writel(NVREG_MISC1_FORCE | (np->duplex ? 0 : NVREG_MISC1_HD),
859 base + NvRegMisc1);
860 pci_push(base);
861 writel(np->linkspeed, base + NvRegLinkSpeed);
862 pci_push(base);
863
864 return retval;
865 }
866
867 #if 0 /* Not used */
868 static void nv_linkchange(struct nic *nic)
869 {
870 if (update_linkspeed(nic)) {
871 // if (netif_carrier_ok(nic)) {
872 stop_rx();
873 //= } else {
874 // netif_carrier_on(dev);
875 // printk(KERN_INFO "%s: link up.\n", dev->name);
876 // }
877 start_rx(nic);
878 } else {
879 // if (netif_carrier_ok(dev)) {
880 // netif_carrier_off(dev);
881 // printk(KERN_INFO "%s: link down.\n", dev->name);
882 stop_rx();
883 // }
884 }
885 }
886 #endif
887
888 static int init_ring(struct nic *nic)
889 {
890 int i;
891
892 np->next_tx = np->nic_tx = 0;
893 for (i = 0; i < TX_RING; i++)
894 tx_ring[i].FlagLen = 0;
895
896 np->cur_rx = 0;
897 np->refill_rx = 0;
898 for (i = 0; i < RX_RING; i++)
899 rx_ring[i].FlagLen = 0;
900 return alloc_rx(nic);
901 }
902
903 static void set_multicast(struct nic *nic)
904 {
905
906 u8 *base = (u8 *) BASE;
907 u32 addr[2];
908 u32 mask[2];
909 u32 pff;
910 u32 alwaysOff[2];
911 u32 alwaysOn[2];
912
913 memset(addr, 0, sizeof(addr));
914 memset(mask, 0, sizeof(mask));
915
916 pff = NVREG_PFF_MYADDR;
917
918 alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0;
919
920 addr[0] = alwaysOn[0];
921 addr[1] = alwaysOn[1];
922 mask[0] = alwaysOn[0] | alwaysOff[0];
923 mask[1] = alwaysOn[1] | alwaysOff[1];
924
925 addr[0] |= NVREG_MCASTADDRA_FORCE;
926 pff |= NVREG_PFF_ALWAYS;
927 stop_rx();
928 writel(addr[0], base + NvRegMulticastAddrA);
929 writel(addr[1], base + NvRegMulticastAddrB);
930 writel(mask[0], base + NvRegMulticastMaskA);
931 writel(mask[1], base + NvRegMulticastMaskB);
932 writel(pff, base + NvRegPacketFilterFlags);
933 start_rx(nic);
934 }
935
936 /**************************************************************************
937 RESET - Reset the NIC to prepare for use
938 ***************************************************************************/
939 static int forcedeth_reset(struct nic *nic)
940 {
941 u8 *base = (u8 *) BASE;
942 int ret, oom, i;
943 ret = 0;
944 dprintf(("forcedeth: open\n"));
945
946 /* 1) erase previous misconfiguration */
947 /* 4.1-1: stop adapter: ignored, 4.3 seems to be overkill */
948 writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
949 writel(0, base + NvRegMulticastAddrB);
950 writel(0, base + NvRegMulticastMaskA);
951 writel(0, base + NvRegMulticastMaskB);
952 writel(0, base + NvRegPacketFilterFlags);
953
954 writel(0, base + NvRegTransmitterControl);
955 writel(0, base + NvRegReceiverControl);
956
957 writel(0, base + NvRegAdapterControl);
958
959 /* 2) initialize descriptor rings */
960 oom = init_ring(nic);
961
962 writel(0, base + NvRegLinkSpeed);
963 writel(0, base + NvRegUnknownTransmitterReg);
964 txrx_reset(nic);
965 writel(0, base + NvRegUnknownSetupReg6);
966
967 np->in_shutdown = 0;
968
969 /* 3) set mac address */
970 {
971 u32 mac[2];
972
973 mac[0] =
974 (nic->node_addr[0] << 0) + (nic->node_addr[1] << 8) +
975 (nic->node_addr[2] << 16) + (nic->node_addr[3] << 24);
976 mac[1] =
977 (nic->node_addr[4] << 0) + (nic->node_addr[5] << 8);
978
979 writel(mac[0], base + NvRegMacAddrA);
980 writel(mac[1], base + NvRegMacAddrB);
981 }
982
983 /* 4) give hw rings */
984 writel((u32) virt_to_le32desc(&rx_ring[0]),
985 base + NvRegRxRingPhysAddr);
986 writel((u32) virt_to_le32desc(&tx_ring[0]),
987 base + NvRegTxRingPhysAddr);
988
989 writel(((RX_RING - 1) << NVREG_RINGSZ_RXSHIFT) +
990 ((TX_RING - 1) << NVREG_RINGSZ_TXSHIFT),
991 base + NvRegRingSizes);
992
993 /* 5) continue setup */
994 np->linkspeed = NVREG_LINKSPEED_FORCE | NVREG_LINKSPEED_10;
995 np->duplex = 0;
996 writel(np->linkspeed, base + NvRegLinkSpeed);
997 writel(NVREG_UNKSETUP3_VAL1, base + NvRegUnknownSetupReg3);
998 writel(np->desc_ver, base + NvRegTxRxControl);
999 pci_push(base);
1000 writel(NVREG_TXRXCTL_BIT1 | np->desc_ver, base + NvRegTxRxControl);
1001 reg_delay(NvRegUnknownSetupReg5, NVREG_UNKSETUP5_BIT31,
1002 NVREG_UNKSETUP5_BIT31, NV_SETUP5_DELAY,
1003 NV_SETUP5_DELAYMAX,
1004 "open: SetupReg5, Bit 31 remained off\n");
1005
1006 writel(0, base + NvRegUnknownSetupReg4);
1007 // writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
1008 writel(NVREG_MIISTAT_MASK2, base + NvRegMIIStatus);
1009 #if 0
1010 printf("%d-Mbs Link, %s-Duplex\n",
1011 np->linkspeed & NVREG_LINKSPEED_10 ? 10 : 100,
1012 np->duplex ? "Full" : "Half");
1013 #endif
1014
1015 /* 6) continue setup */
1016 writel(NVREG_MISC1_FORCE | NVREG_MISC1_HD, base + NvRegMisc1);
1017 writel(readl(base + NvRegTransmitterStatus),
1018 base + NvRegTransmitterStatus);
1019 writel(NVREG_PFF_ALWAYS, base + NvRegPacketFilterFlags);
1020 writel(NVREG_OFFLOAD_NORMAL, base + NvRegOffloadConfig);
1021
1022 writel(readl(base + NvRegReceiverStatus),
1023 base + NvRegReceiverStatus);
1024
1025 /* Get a random number */
1026 i = random();
1027 writel(NVREG_RNDSEED_FORCE | (i & NVREG_RNDSEED_MASK),
1028 base + NvRegRandomSeed);
1029 writel(NVREG_UNKSETUP1_VAL, base + NvRegUnknownSetupReg1);
1030 writel(NVREG_UNKSETUP2_VAL, base + NvRegUnknownSetupReg2);
1031 writel(NVREG_POLL_DEFAULT, base + NvRegPollingInterval);
1032 writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
1033 writel((np->
1034 phyaddr << NVREG_ADAPTCTL_PHYSHIFT) |
1035 NVREG_ADAPTCTL_PHYVALID | NVREG_ADAPTCTL_RUNNING,
1036 base + NvRegAdapterControl);
1037 writel(NVREG_MIISPEED_BIT8 | NVREG_MIIDELAY, base + NvRegMIISpeed);
1038 writel(NVREG_UNKSETUP4_VAL, base + NvRegUnknownSetupReg4);
1039 writel(NVREG_WAKEUPFLAGS_VAL, base + NvRegWakeUpFlags);
1040
1041 i = readl(base + NvRegPowerState);
1042 if ((i & NVREG_POWERSTATE_POWEREDUP) == 0)
1043 writel(NVREG_POWERSTATE_POWEREDUP | i,
1044 base + NvRegPowerState);
1045
1046 pci_push(base);
1047 udelay(10);
1048 writel(readl(base + NvRegPowerState) | NVREG_POWERSTATE_VALID,
1049 base + NvRegPowerState);
1050
1051 writel(0, base + NvRegIrqMask);
1052 pci_push(base);
1053 writel(NVREG_MIISTAT_MASK2, base + NvRegMIIStatus);
1054 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
1055 pci_push(base);
1056 /*
1057 writel(np->irqmask, base + NvRegIrqMask);
1058 */
1059 writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
1060 writel(0, base + NvRegMulticastAddrB);
1061 writel(0, base + NvRegMulticastMaskA);
1062 writel(0, base + NvRegMulticastMaskB);
1063 writel(NVREG_PFF_ALWAYS | NVREG_PFF_MYADDR,
1064 base + NvRegPacketFilterFlags);
1065
1066 set_multicast(nic);
1067 /* One manual link speed update: Interrupts are enabled, future link
1068 * speed changes cause interrupts and are handled by nv_link_irq().
1069 */
1070 {
1071 u32 miistat;
1072 miistat = readl(base + NvRegMIIStatus);
1073 writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus);
1074 dprintf(("startup: got 0x%hX.\n", miistat));
1075 }
1076 ret = update_linkspeed(nic);
1077
1078 //start_rx(nic);
1079 start_tx(nic);
1080
1081 if (ret) {
1082 //Start Connection netif_carrier_on(dev);
1083 } else {
1084 printf("no link during initialization.\n");
1085 }
1086
1087 return ret;
1088 }
1089
1090 /*
1091 * extern void hex_dump(const char *data, const unsigned int len);
1092 */
1093 /**************************************************************************
1094 POLL - Wait for a frame
1095 ***************************************************************************/
1096 static int forcedeth_poll(struct nic *nic, int retrieve)
1097 {
1098 /* return true if there's an ethernet packet ready to read */
1099 /* nic->packet should contain data on return */
1100 /* nic->packetlen should contain length of data */
1101
1102 int len;
1103 int i;
1104 u32 Flags;
1105
1106 i = np->cur_rx % RX_RING;
1107
1108 Flags = le32_to_cpu(rx_ring[i].FlagLen);
1109 len = nv_descr_getlength(&rx_ring[i], np->desc_ver);
1110
1111 if (Flags & NV_RX_AVAIL)
1112 return 0; /* still owned by hardware, */
1113
1114 if (np->desc_ver == DESC_VER_1) {
1115 if (!(Flags & NV_RX_DESCRIPTORVALID))
1116 return 0;
1117 } else {
1118 if (!(Flags & NV_RX2_DESCRIPTORVALID))
1119 return 0;
1120 }
1121
1122 if (!retrieve)
1123 return 1;
1124
1125 /* got a valid packet - forward it to the network core */
1126 nic->packetlen = len;
1127 memcpy(nic->packet, rxb + (i * RX_NIC_BUFSIZE), nic->packetlen);
1128 /*
1129 * hex_dump(rxb + (i * RX_NIC_BUFSIZE), len);
1130 */
1131 wmb();
1132 np->cur_rx++;
1133 alloc_rx(nic);
1134 return 1;
1135 }
1136
1137
1138 /**************************************************************************
1139 TRANSMIT - Transmit a frame
1140 ***************************************************************************/
1141 static void forcedeth_transmit(struct nic *nic, const char *d, /* Destination */
1142 unsigned int t, /* Type */
1143 unsigned int s, /* size */
1144 const char *p)
1145 { /* Packet */
1146 /* send the packet to destination */
1147 u8 *ptxb;
1148 u16 nstype;
1149 u8 *base = (u8 *) BASE;
1150 int nr = np->next_tx % TX_RING;
1151
1152 /* point to the current txb incase multiple tx_rings are used */
1153 ptxb = txb + (nr * RX_NIC_BUFSIZE);
1154 //np->tx_skbuff[nr] = ptxb;
1155
1156 /* copy the packet to ring buffer */
1157 memcpy(ptxb, d, ETH_ALEN); /* dst */
1158 memcpy(ptxb + ETH_ALEN, nic->node_addr, ETH_ALEN); /* src */
1159 nstype = htons((u16) t); /* type */
1160 memcpy(ptxb + 2 * ETH_ALEN, (u8 *) & nstype, 2); /* type */
1161 memcpy(ptxb + ETH_HLEN, p, s);
1162
1163 s += ETH_HLEN;
1164 while (s < ETH_ZLEN) /* pad to min length */
1165 ptxb[s++] = '\0';
1166
1167 tx_ring[nr].PacketBuffer = (u32) virt_to_le32desc(ptxb);
1168
1169 wmb();
1170 tx_ring[nr].FlagLen = cpu_to_le32((s - 1) | np->tx_flags);
1171
1172 writel(NVREG_TXRXCTL_KICK | np->desc_ver, base + NvRegTxRxControl);
1173 pci_push(base);
1174 np->next_tx++;
1175 }
1176
1177 /**************************************************************************
1178 DISABLE - Turn off ethernet interface
1179 ***************************************************************************/
1180 static void forcedeth_disable ( struct nic *nic __unused ) {
1181 /* put the card in its initial state */
1182 /* This function serves 3 purposes.
1183 * This disables DMA and interrupts so we don't receive
1184 * unexpected packets or interrupts from the card after
1185 * etherboot has finished.
1186 * This frees resources so etherboot may use
1187 * this driver on another interface
1188 * This allows etherboot to reinitialize the interface
1189 * if something is something goes wrong.
1190 */
1191 u8 *base = (u8 *) BASE;
1192 np->in_shutdown = 1;
1193 stop_tx();
1194 stop_rx();
1195
1196 /* disable interrupts on the nic or we will lock up */
1197 writel(0, base + NvRegIrqMask);
1198 pci_push(base);
1199 dprintf(("Irqmask is zero again\n"));
1200
1201 /* specia op:o write back the misordered MAC address - otherwise
1202 * the next probe_nic would see a wrong address.
1203 */
1204 writel(np->orig_mac[0], base + NvRegMacAddrA);
1205 writel(np->orig_mac[1], base + NvRegMacAddrB);
1206 }
1207
1208 /**************************************************************************
1209 IRQ - Enable, Disable, or Force interrupts
1210 ***************************************************************************/
1211 static void forcedeth_irq(struct nic *nic __unused,
1212 irq_action_t action __unused)
1213 {
1214 switch (action) {
1215 case DISABLE:
1216 break;
1217 case ENABLE:
1218 break;
1219 case FORCE:
1220 break;
1221 }
1222 }
1223
1224 static struct nic_operations forcedeth_operations = {
1225 .connect = dummy_connect,
1226 .poll = forcedeth_poll,
1227 .transmit = forcedeth_transmit,
1228 .irq = forcedeth_irq,
1229
1230 };
1231
1232 /**************************************************************************
1233 PROBE - Look for an adapter, this routine's visible to the outside
1234 ***************************************************************************/
1235 #define IORESOURCE_MEM 0x00000200
1236 #define board_found 1
1237 #define valid_link 0
1238 static int forcedeth_probe ( struct nic *nic, struct pci_device *pci ) {
1239
1240 unsigned long addr;
1241 int sz;
1242 u8 *base;
1243 int i;
1244
1245 if (pci->ioaddr == 0)
1246 return 0;
1247
1248 printf("forcedeth.c: Found %s, vendor=0x%hX, device=0x%hX\n",
1249 pci->driver_name, pci->vendor, pci->device);
1250
1251 pci_fill_nic ( nic, pci );
1252
1253 /* point to private storage */
1254 np = &npx;
1255
1256 adjust_pci_device(pci);
1257
1258 addr = pci_bar_start(pci, PCI_BASE_ADDRESS_0);
1259 sz = pci_bar_size(pci, PCI_BASE_ADDRESS_0);
1260
1261 /* BASE is used throughout to address the card */
1262 BASE = (unsigned long) ioremap(addr, sz);
1263 if (!BASE)
1264 return 0;
1265
1266 /* handle different descriptor versions */
1267 if (pci->device == PCI_DEVICE_ID_NVIDIA_NVENET_1 ||
1268 pci->device == PCI_DEVICE_ID_NVIDIA_NVENET_2 ||
1269 pci->device == PCI_DEVICE_ID_NVIDIA_NVENET_3)
1270 np->desc_ver = DESC_VER_1;
1271 else
1272 np->desc_ver = DESC_VER_2;
1273
1274 //rx_ring[0] = rx_ring;
1275 //tx_ring[0] = tx_ring;
1276
1277 /* read the mac address */
1278 base = (u8 *) BASE;
1279 np->orig_mac[0] = readl(base + NvRegMacAddrA);
1280 np->orig_mac[1] = readl(base + NvRegMacAddrB);
1281
1282 nic->node_addr[0] = (np->orig_mac[1] >> 8) & 0xff;
1283 nic->node_addr[1] = (np->orig_mac[1] >> 0) & 0xff;
1284 nic->node_addr[2] = (np->orig_mac[0] >> 24) & 0xff;
1285 nic->node_addr[3] = (np->orig_mac[0] >> 16) & 0xff;
1286 nic->node_addr[4] = (np->orig_mac[0] >> 8) & 0xff;
1287 nic->node_addr[5] = (np->orig_mac[0] >> 0) & 0xff;
1288 #ifdef LINUX
1289 if (!is_valid_ether_addr(dev->dev_addr)) {
1290 /*
1291 * Bad mac address. At least one bios sets the mac address
1292 * to 01:23:45:67:89:ab
1293 */
1294 printk(KERN_ERR
1295 "%s: Invalid Mac address detected: %02x:%02x:%02x:%02x:%02x:%02x\n",
1296 pci_name(pci_dev), dev->dev_addr[0],
1297 dev->dev_addr[1], dev->dev_addr[2],
1298 dev->dev_addr[3], dev->dev_addr[4],
1299 dev->dev_addr[5]);
1300 printk(KERN_ERR
1301 "Please complain to your hardware vendor. Switching to a random MAC.\n");
1302 dev->dev_addr[0] = 0x00;
1303 dev->dev_addr[1] = 0x00;
1304 dev->dev_addr[2] = 0x6c;
1305 get_random_bytes(&dev->dev_addr[3], 3);
1306 }
1307 #endif
1308
1309 DBG ( "%s: MAC Address %s\n", pci->driver_name, eth_ntoa ( nic->node_addr ) );
1310
1311 /* disable WOL */
1312 writel(0, base + NvRegWakeUpFlags);
1313 np->wolenabled = 0;
1314
1315 if (np->desc_ver == DESC_VER_1) {
1316 np->tx_flags = NV_TX_LASTPACKET | NV_TX_VALID;
1317 } else {
1318 np->tx_flags = NV_TX2_LASTPACKET | NV_TX2_VALID;
1319 }
1320
1321 switch (pci->device) {
1322 case 0x01C3: // nforce
1323 // DEV_IRQMASK_1|DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
1324 np->irqmask = NVREG_IRQMASK_WANTED_2 | NVREG_IRQ_TIMER;
1325 // np->need_linktimer = 1;
1326 // np->link_timeout = jiffies + LINK_TIMEOUT;
1327 break;
1328 case 0x0066:
1329 /* Fall Through */
1330 case 0x00D6:
1331 // DEV_NEED_LASTPACKET1|DEV_IRQMASK_2|DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER
1332 np->irqmask = NVREG_IRQMASK_WANTED_2;
1333 np->irqmask |= NVREG_IRQ_TIMER;
1334 // np->need_linktimer = 1;
1335 // np->link_timeout = jiffies + LINK_TIMEOUT;
1336 if (np->desc_ver == DESC_VER_1)
1337 np->tx_flags |= NV_TX_LASTPACKET1;
1338 else
1339 np->tx_flags |= NV_TX2_LASTPACKET1;
1340 break;
1341 case 0x0086:
1342 /* Fall Through */
1343 case 0x008c:
1344 /* Fall Through */
1345 case 0x00e6:
1346 /* Fall Through */
1347 case 0x00df:
1348 /* Fall Through */
1349 case 0x0056:
1350 /* Fall Through */
1351 case 0x0057:
1352 /* Fall Through */
1353 case 0x0037:
1354 /* Fall Through */
1355 case 0x0038:
1356 //DEV_NEED_LASTPACKET1|DEV_IRQMASK_2|DEV_NEED_TIMERIRQ
1357 np->irqmask = NVREG_IRQMASK_WANTED_2;
1358 np->irqmask |= NVREG_IRQ_TIMER;
1359 // np->need_linktimer = 1;
1360 // np->link_timeout = jiffies + LINK_TIMEOUT;
1361 if (np->desc_ver == DESC_VER_1)
1362 np->tx_flags |= NV_TX_LASTPACKET1;
1363 else
1364 np->tx_flags |= NV_TX2_LASTPACKET1;
1365 break;
1366 default:
1367 printf
1368 ("Your card was undefined in this driver. Review driver_data in Linux driver and send a patch\n");
1369 }
1370
1371 /* find a suitable phy */
1372 for (i = 1; i < 32; i++) {
1373 int id1, id2;
1374 id1 = mii_rw(nic, i, MII_PHYSID1, MII_READ);
1375 if (id1 < 0 || id1 == 0xffff)
1376 continue;
1377 id2 = mii_rw(nic, i, MII_PHYSID2, MII_READ);
1378 if (id2 < 0 || id2 == 0xffff)
1379 continue;
1380 id1 = (id1 & PHYID1_OUI_MASK) << PHYID1_OUI_SHFT;
1381 id2 = (id2 & PHYID2_OUI_MASK) >> PHYID2_OUI_SHFT;
1382 dprintf
1383 (("%s: open: Found PHY %hX:%hX at address %d.\n",
1384 pci->driver_name, id1, id2, i));
1385 np->phyaddr = i;
1386 np->phy_oui = id1 | id2;
1387 break;
1388 }
1389 if (i == 32) {
1390 /* PHY in isolate mode? No phy attached and user wants to
1391 * test loopback? Very odd, but can be correct.
1392 */
1393 printf
1394 ("%s: open: Could not find a valid PHY.\n", pci->driver_name);
1395 }
1396
1397 if (i != 32) {
1398 /* reset it */
1399 phy_init(nic);
1400 }
1401
1402 dprintf(("%s: forcedeth.c: subsystem: %hX:%hX bound to %s\n",
1403 pci->driver_name, pci->vendor, pci->dev_id, pci->driver_name));
1404 if(!forcedeth_reset(nic)) return 0; // no valid link
1405
1406 /* point to NIC specific routines */
1407 nic->nic_op = &forcedeth_operations;
1408 return 1;
1409 }
1410
1411 static struct pci_device_id forcedeth_nics[] = {
1412 PCI_ROM(0x10de, 0x01C3, "nforce", "nForce NVENET_1 Ethernet Controller"),
1413 PCI_ROM(0x10de, 0x0066, "nforce2", "nForce NVENET_2 Ethernet Controller"),
1414 PCI_ROM(0x10de, 0x00D6, "nforce3", "nForce NVENET_3 Ethernet Controller"),
1415 PCI_ROM(0x10de, 0x0086, "nforce4", "nForce NVENET_4 Ethernet Controller"),
1416 PCI_ROM(0x10de, 0x008c, "nforce5", "nForce NVENET_5 Ethernet Controller"),
1417 PCI_ROM(0x10de, 0x00e6, "nforce6", "nForce NVENET_6 Ethernet Controller"),
1418 PCI_ROM(0x10de, 0x00df, "nforce7", "nForce NVENET_7 Ethernet Controller"),
1419 PCI_ROM(0x10de, 0x0056, "nforce8", "nForce NVENET_8 Ethernet Controller"),
1420 PCI_ROM(0x10de, 0x0057, "nforce9", "nForce NVENET_9 Ethernet Controller"),
1421 PCI_ROM(0x10de, 0x0037, "nforce10", "nForce NVENET_10 Ethernet Controller"),
1422 PCI_ROM(0x10de, 0x0038, "nforce11", "nForce NVENET_11 Ethernet Controller"),
1423 };
1424
1425 PCI_DRIVER ( forcedeth_driver, forcedeth_nics, PCI_NO_CLASS );
1426
1427 DRIVER ( "forcedeth", nic_driver, pci_driver, forcedeth_driver,
1428 forcedeth_probe, forcedeth_disable );
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