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Remove obsolete files (INSTALL, RELNOTES)
[gpxe.git] / src / drivers / net / r8169.c
blob52cb0d0e4cc01e413385f37da65d43a1a145f950
1 /**************************************************************************
2 * r8169.c: Etherboot device driver for the RealTek RTL-8169 Gigabit
3 * Written 2003 by Timothy Legge <tlegge@rogers.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
18 *
19 * Portions of this code based on:
20 * r8169.c: A RealTek RTL-8169 Gigabit Ethernet driver
21 * for Linux kernel 2.4.x.
22 *
23 * Written 2002 ShuChen <shuchen@realtek.com.tw>
24 * See Linux Driver for full information
25 *
26 * Linux Driver Versions:
27 * 1.27a, 10.02.2002
28 * RTL8169_VERSION "2.2" <2004/08/09>
29 *
30 * Thanks to:
31 * Jean Chen of RealTek Semiconductor Corp. for
32 * providing the evaluation NIC used to develop
33 * this driver. RealTek's support for Etherboot
34 * is appreciated.
35 *
36 * REVISION HISTORY:
37 * ================
38 *
39 * v1.0 11-26-2003 timlegge Initial port of Linux driver
40 * v1.5 01-17-2004 timlegge Initial driver output cleanup
41 * v1.6 03-27-2004 timlegge Additional Cleanup
42 * v1.7 11-22-2005 timlegge Update to RealTek Driver Version 2.2
43 *
44 * Indent Options: indent -kr -i8
45 ***************************************************************************/
46
47 #include "etherboot.h"
48 #include "nic.h"
49 #include <gpxe/pci.h>
50 #include <gpxe/ethernet.h>
51 #include <gpxe/malloc.h>
52 #include "timer.h"
53
54 #define drv_version "v1.6"
55 #define drv_date "03-27-2004"
56
57 #define HZ 1000
58
59 static u32 ioaddr;
60
61 /* Condensed operations for readability. */
62 #define virt_to_le32desc(addr) cpu_to_le32(virt_to_bus(addr))
63 #define le32desc_to_virt(addr) bus_to_virt(le32_to_cpu(addr))
64
65 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
66
67 #undef RTL8169_DEBUG
68 #undef RTL8169_JUMBO_FRAME_SUPPORT
69 #undef RTL8169_HW_FLOW_CONTROL_SUPPORT
70
71
72 #undef RTL8169_IOCTL_SUPPORT
73 #undef RTL8169_DYNAMIC_CONTROL
74 #define RTL8169_USE_IO
75
76
77 /* media options
78 _10_Half = 0x01,
79 _10_Full = 0x02,
80 _100_Half = 0x04,
81 _100_Full = 0x08,
82 _1000_Full = 0x10,
83 */
84 static int media = -1;
85
86 #if 0
87 /* Maximum events (Rx packets, etc.) to handle at each interrupt. */
88 static int max_interrupt_work = 20;
89 #endif
90
91 #if 0
92 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
93 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
94 static int multicast_filter_limit = 32;
95 #endif
96
97 /* MAC address length*/
98 #define MAC_ADDR_LEN 6
99
100 /* max supported gigabit ethernet frame size -- must be at least (dev->mtu+14+4).*/
101 #define MAX_ETH_FRAME_SIZE 1536
102
103 #define TX_FIFO_THRESH 256 /* In bytes */
104
105 #define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
106 #define RX_DMA_BURST 7 /* Maximum PCI burst, '6' is 1024 */
107 #define TX_DMA_BURST 7 /* Maximum PCI burst, '6' is 1024 */
108 #define ETTh 0x3F /* 0x3F means NO threshold */
109
110 #define EarlyTxThld 0x3F /* 0x3F means NO early transmit */
111 #define RxPacketMaxSize 0x0800 /* Maximum size supported is 16K-1 */
112 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
113
114 #define NUM_TX_DESC 1 /* Number of Tx descriptor registers */
115 #define NUM_RX_DESC 4 /* Number of Rx descriptor registers */
116 #define RX_BUF_SIZE 1536 /* Rx Buffer size */
117
118 #define RTL_MIN_IO_SIZE 0x80
119 #define TX_TIMEOUT (6*HZ)
120
121 #define RTL8169_TIMER_EXPIRE_TIME 100 //100
122
123 #define ETH_HDR_LEN 14
124 #define DEFAULT_MTU 1500
125 #define DEFAULT_RX_BUF_LEN 1536
126
127
128 #ifdef RTL8169_JUMBO_FRAME_SUPPORT
129 #define MAX_JUMBO_FRAME_MTU ( 10000 )
130 #define MAX_RX_SKBDATA_SIZE ( MAX_JUMBO_FRAME_MTU + ETH_HDR_LEN )
131 #else
132 #define MAX_RX_SKBDATA_SIZE 1600
133 #endif //end #ifdef RTL8169_JUMBO_FRAME_SUPPORT
134
135 #ifdef RTL8169_USE_IO
136 #define RTL_W8(reg, val8) outb ((val8), ioaddr + (reg))
137 #define RTL_W16(reg, val16) outw ((val16), ioaddr + (reg))
138 #define RTL_W32(reg, val32) outl ((val32), ioaddr + (reg))
139 #define RTL_R8(reg) inb (ioaddr + (reg))
140 #define RTL_R16(reg) inw (ioaddr + (reg))
141 #define RTL_R32(reg) ((unsigned long) inl (ioaddr + (reg)))
142 #else
143 /* write/read MMIO register */
144 #define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
145 #define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
146 #define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
147 #define RTL_R8(reg) readb (ioaddr + (reg))
148 #define RTL_R16(reg) readw (ioaddr + (reg))
149 #define RTL_R32(reg) ((unsigned long) readl (ioaddr + (reg)))
150 #endif
151
152 #define MCFG_METHOD_1 0x01
153 #define MCFG_METHOD_2 0x02
154 #define MCFG_METHOD_3 0x03
155 #define MCFG_METHOD_4 0x04
156
157 #define PCFG_METHOD_1 0x01 //PHY Reg 0x03 bit0-3 == 0x0000
158 #define PCFG_METHOD_2 0x02 //PHY Reg 0x03 bit0-3 == 0x0001
159 #define PCFG_METHOD_3 0x03 //PHY Reg 0x03 bit0-3 == 0x0002
160
161 static struct {
162 const char *name;
163 u8 mcfg; /* depend on RTL8169 docs */
164 u32 RxConfigMask; /* should clear the bits supported by this chip */
165 } rtl_chip_info[] = {
166 {
167 "RTL-8169", MCFG_METHOD_1, 0xff7e1880,}, {
168 "RTL8169s/8110s", MCFG_METHOD_2, 0xff7e1880}, {
169 "RTL8169s/8110s", MCFG_METHOD_3, 0xff7e1880},};
170
171 enum RTL8169_registers {
172 MAC0 = 0x0, /* Ethernet hardware address. */
173 MAR0 = 0x8, /* Multicast filter. */
174 TxDescStartAddr = 0x20,
175 TxHDescStartAddr = 0x28,
176 FLASH = 0x30,
177 ERSR = 0x36,
178 ChipCmd = 0x37,
179 TxPoll = 0x38,
180 IntrMask = 0x3C,
181 IntrStatus = 0x3E,
182 TxConfig = 0x40,
183 RxConfig = 0x44,
184 RxMissed = 0x4C,
185 Cfg9346 = 0x50,
186 Config0 = 0x51,
187 Config1 = 0x52,
188 Config2 = 0x53,
189 Config3 = 0x54,
190 Config4 = 0x55,
191 Config5 = 0x56,
192 MultiIntr = 0x5C,
193 PHYAR = 0x60,
194 TBICSR = 0x64,
195 TBI_ANAR = 0x68,
196 TBI_LPAR = 0x6A,
197 PHYstatus = 0x6C,
198 RxMaxSize = 0xDA,
199 CPlusCmd = 0xE0,
200 RxDescStartAddr = 0xE4,
201 ETThReg = 0xEC,
202 FuncEvent = 0xF0,
203 FuncEventMask = 0xF4,
204 FuncPresetState = 0xF8,
205 FuncForceEvent = 0xFC,
206 };
207
208 enum RTL8169_register_content {
209 /*InterruptStatusBits */
210 SYSErr = 0x8000,
211 PCSTimeout = 0x4000,
212 SWInt = 0x0100,
213 TxDescUnavail = 0x80,
214 RxFIFOOver = 0x40,
215 LinkChg = 0x20,
216 RxOverflow = 0x10,
217 TxErr = 0x08,
218 TxOK = 0x04,
219 RxErr = 0x02,
220 RxOK = 0x01,
221
222 /*RxStatusDesc */
223 RxRES = 0x00200000,
224 RxCRC = 0x00080000,
225 RxRUNT = 0x00100000,
226 RxRWT = 0x00400000,
227
228 /*ChipCmdBits */
229 CmdReset = 0x10,
230 CmdRxEnb = 0x08,
231 CmdTxEnb = 0x04,
232 RxBufEmpty = 0x01,
233
234 /*Cfg9346Bits */
235 Cfg9346_Lock = 0x00,
236 Cfg9346_Unlock = 0xC0,
237
238 /*rx_mode_bits */
239 AcceptErr = 0x20,
240 AcceptRunt = 0x10,
241 AcceptBroadcast = 0x08,
242 AcceptMulticast = 0x04,
243 AcceptMyPhys = 0x02,
244 AcceptAllPhys = 0x01,
245
246 /*RxConfigBits */
247 RxCfgFIFOShift = 13,
248 RxCfgDMAShift = 8,
249
250 /*TxConfigBits */
251 TxInterFrameGapShift = 24,
252 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
253
254 /*rtl8169_PHYstatus */
255 TBI_Enable = 0x80,
256 TxFlowCtrl = 0x40,
257 RxFlowCtrl = 0x20,
258 _1000bpsF = 0x10,
259 _100bps = 0x08,
260 _10bps = 0x04,
261 LinkStatus = 0x02,
262 FullDup = 0x01,
263
264 /*GIGABIT_PHY_registers */
265 PHY_CTRL_REG = 0,
266 PHY_STAT_REG = 1,
267 PHY_AUTO_NEGO_REG = 4,
268 PHY_1000_CTRL_REG = 9,
269
270 /*GIGABIT_PHY_REG_BIT */
271 PHY_Restart_Auto_Nego = 0x0200,
272 PHY_Enable_Auto_Nego = 0x1000,
273
274 /* PHY_STAT_REG = 1; */
275 PHY_Auto_Neco_Comp = 0x0020,
276
277 /* PHY_AUTO_NEGO_REG = 4; */
278 PHY_Cap_10_Half = 0x0020,
279 PHY_Cap_10_Full = 0x0040,
280 PHY_Cap_100_Half = 0x0080,
281 PHY_Cap_100_Full = 0x0100,
282
283 /* PHY_1000_CTRL_REG = 9; */
284 PHY_Cap_1000_Full = 0x0200,
285 PHY_Cap_1000_Half = 0x0100,
286
287 PHY_Cap_PAUSE = 0x0400,
288 PHY_Cap_ASYM_PAUSE = 0x0800,
289
290 PHY_Cap_Null = 0x0,
291
292 /*_MediaType*/
293 _10_Half = 0x01,
294 _10_Full = 0x02,
295 _100_Half = 0x04,
296 _100_Full = 0x08,
297 _1000_Full = 0x10,
298
299 /*_TBICSRBit*/
300 TBILinkOK = 0x02000000,
301 };
302
303 enum _DescStatusBit {
304 OWNbit = 0x80000000,
305 EORbit = 0x40000000,
306 FSbit = 0x20000000,
307 LSbit = 0x10000000,
308 };
309
310 struct TxDesc {
311 u32 status;
312 u32 vlan_tag;
313 u32 buf_addr;
314 u32 buf_Haddr;
315 };
316
317 struct RxDesc {
318 u32 status;
319 u32 vlan_tag;
320 u32 buf_addr;
321 u32 buf_Haddr;
322 };
323
324 /* The descriptors for this card are required to be aligned on 256
325 * byte boundaries. As the align attribute does not do more than 16
326 * bytes of alignment it requires some extra steps. Add 256 to the
327 * size of the array and the init_ring adjusts the alignment.
328 *
329 * UPDATE: This is no longer true; we can request arbitrary alignment.
330 */
331
332 /* Define the TX and RX Descriptors and Buffers */
333 #define __align_256 __attribute__ (( aligned ( 256 ) ))
334 struct {
335 struct TxDesc tx_ring[NUM_TX_DESC] __align_256;
336 unsigned char txb[NUM_TX_DESC * RX_BUF_SIZE];
337 struct RxDesc rx_ring[NUM_RX_DESC] __align_256;
338 unsigned char rxb[NUM_RX_DESC * RX_BUF_SIZE];
339 } *r8169_bufs;
340 #define tx_ring r8169_bufs->tx_ring
341 #define rx_ring r8169_bufs->rx_ring
342 #define txb r8169_bufs->txb
343 #define rxb r8169_bufs->rxb
344
345 static struct rtl8169_private {
346 void *mmio_addr; /* memory map physical address */
347 int chipset;
348 int pcfg;
349 int mcfg;
350 unsigned long cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
351 unsigned long cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
352 struct TxDesc *TxDescArray; /* Index of 256-alignment Tx Descriptor buffer */
353 struct RxDesc *RxDescArray; /* Index of 256-alignment Rx Descriptor buffer */
354 unsigned char *RxBufferRing[NUM_RX_DESC]; /* Index of Rx Buffer array */
355 unsigned char *Tx_skbuff[NUM_TX_DESC];
356 } tpx;
357
358 static struct rtl8169_private *tpc;
359
360 static const u16 rtl8169_intr_mask =
361 LinkChg | RxOverflow | RxFIFOOver | TxErr | TxOK | RxErr | RxOK;
362 static const unsigned int rtl8169_rx_config =
363 (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift) |
364 0x0000000E;
365
366 static void rtl8169_hw_PHY_config(struct nic *nic __unused);
367 //static void rtl8169_hw_PHY_reset(struct net_device *dev);
368
369 #define RTL8169_WRITE_GMII_REG_BIT( ioaddr, reg, bitnum, bitval )\
370 { \
371 int val; \
372 if( bitval == 1 ){ val = ( RTL8169_READ_GMII_REG( ioaddr, reg ) | (bitval<<bitnum) ) & 0xffff ; } \
373 else{ val = ( RTL8169_READ_GMII_REG( ioaddr, reg ) & (~(0x0001<<bitnum)) ) & 0xffff ; } \
374 RTL8169_WRITE_GMII_REG( ioaddr, reg, val ); \
375 }
376
377 //=================================================================
378 // PHYAR
379 // bit Symbol
380 // 31 Flag
381 // 30-21 reserved
382 // 20-16 5-bit GMII/MII register address
383 // 15-0 16-bit GMII/MII register data
384 //=================================================================
385 static void RTL8169_WRITE_GMII_REG(unsigned long ioaddr, int RegAddr, int value)
386 {
387 int i;
388
389 RTL_W32(PHYAR, 0x80000000 | (RegAddr & 0xFF) << 16 | value);
390 udelay(1000);
391
392 for (i = 2000; i > 0; i--) {
393 // Check if the RTL8169 has completed writing to the specified MII register
394 if (!(RTL_R32(PHYAR) & 0x80000000)) {
395 break;
396 } else {
397 udelay(100);
398 } // end of if( ! (RTL_R32(PHYAR)&0x80000000) )
399 } // end of for() loop
400 }
401
402 //=================================================================
403 static int RTL8169_READ_GMII_REG(unsigned long ioaddr, int RegAddr)
404 {
405 int i, value = -1;
406
407 RTL_W32(PHYAR, 0x0 | (RegAddr & 0xFF) << 16);
408 udelay(1000);
409
410 for (i = 2000; i > 0; i--) {
411 // Check if the RTL8169 has completed retrieving data from the specified MII register
412 if (RTL_R32(PHYAR) & 0x80000000) {
413 value = (int) (RTL_R32(PHYAR) & 0xFFFF);
414 break;
415 } else {
416 udelay(100);
417 } // end of if( RTL_R32(PHYAR) & 0x80000000 )
418 } // end of for() loop
419 return value;
420 }
421
422
423 #if 0
424 static void mdio_write(int RegAddr, int value)
425 {
426 int i;
427
428 RTL_W32(PHYAR, 0x80000000 | (RegAddr & 0xFF) << 16 | value);
429 udelay(1000);
430
431 for (i = 2000; i > 0; i--) {
432 /* Check if the RTL8169 has completed writing to the specified MII register */
433 if (!(RTL_R32(PHYAR) & 0x80000000)) {
434 break;
435 } else {
436 udelay(100);
437 }
438 }
439 }
440
441 static int mdio_read(int RegAddr)
442 {
443 int i, value = -1;
444
445 RTL_W32(PHYAR, 0x0 | (RegAddr & 0xFF) << 16);
446 udelay(1000);
447
448 for (i = 2000; i > 0; i--) {
449 /* Check if the RTL8169 has completed retrieving data from the specified MII register */
450 if (RTL_R32(PHYAR) & 0x80000000) {
451 value = (int) (RTL_R32(PHYAR) & 0xFFFF);
452 break;
453 } else {
454 udelay(100);
455 }
456 }
457 return value;
458 }
459 #endif
460
461 #define IORESOURCE_MEM 0x00000200
462
463 static int rtl8169_init_board(struct pci_device *pdev)
464 {
465 int i;
466 // unsigned long mmio_end, mmio_flags
467 unsigned long mmio_start, mmio_len;
468
469 adjust_pci_device(pdev);
470
471 mmio_start = pci_bar_start(pdev, PCI_BASE_ADDRESS_1);
472 // mmio_end = pci_resource_end (pdev, 1);
473 // mmio_flags = pci_resource_flags (pdev, PCI_BASE_ADDRESS_1);
474 mmio_len = pci_bar_size(pdev, PCI_BASE_ADDRESS_1);
475
476 // make sure PCI base addr 1 is MMIO
477 // if (!(mmio_flags & IORESOURCE_MEM)) {
478 // printf ("region #1 not an MMIO resource, aborting\n");
479 // return 0;
480 // }
481
482 // check for weird/broken PCI region reporting
483 if (mmio_len < RTL_MIN_IO_SIZE) {
484 printf("Invalid PCI region size(s), aborting\n");
485 return 0;
486 }
487 #ifdef RTL8169_USE_IO
488 ioaddr = pci_bar_start(pdev, PCI_BASE_ADDRESS_0);
489 #else
490 // ioremap MMIO region
491 ioaddr = (unsigned long) ioremap(mmio_start, mmio_len);
492 if (ioaddr == 0) {
493 printk("cannot remap MMIO, aborting\n");
494 return 0;
495 }
496 #endif
497
498 tpc->mmio_addr = &ioaddr;
499 /* Soft reset the chip. */
500 RTL_W8(ChipCmd, CmdReset);
501
502 /* Check that the chip has finished the reset. */
503 for (i = 1000; i > 0; i--)
504 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
505 break;
506 else
507 udelay(10);
508 // identify config method
509 {
510 unsigned long val32 = (RTL_R32(TxConfig) & 0x7c800000);
511 if (val32 == (0x1 << 28)) {
512 tpc->mcfg = MCFG_METHOD_4;
513 } else if (val32 == (0x1 << 26)) {
514 tpc->mcfg = MCFG_METHOD_3;
515 } else if (val32 == (0x1 << 23)) {
516 tpc->mcfg = MCFG_METHOD_2;
517 } else if (val32 == 0x00000000) {
518 tpc->mcfg = MCFG_METHOD_1;
519 } else {
520 tpc->mcfg = MCFG_METHOD_1;
521 }
522 }
523 {
524 unsigned char val8 =
525 (unsigned char) (RTL8169_READ_GMII_REG(ioaddr, 3) &
526 0x000f);
527 if (val8 == 0x00) {
528 tpc->pcfg = PCFG_METHOD_1;
529 } else if (val8 == 0x01) {
530 tpc->pcfg = PCFG_METHOD_2;
531 } else if (val8 == 0x02) {
532 tpc->pcfg = PCFG_METHOD_3;
533 } else {
534 tpc->pcfg = PCFG_METHOD_3;
535 }
536 }
537
538 /* identify chip attached to board */
539
540 for (i = ARRAY_SIZE(rtl_chip_info) - 1; i >= 0; i--)
541 if (tpc->mcfg == rtl_chip_info[i].mcfg) {
542 tpc->chipset = i;
543 goto match;
544 }
545 /* if unknown chip, assume array element #0, original RTL-8169 in this case */
546 DBG ( "PCI device: unknown chip version, assuming RTL-8169\n" );
547 DBG ( "PCI device: TxConfig = %#lX\n", ( unsigned long ) RTL_R32 ( TxConfig ) );
548
549 tpc->chipset = 0;
550 return 1;
551
552 match:
553 return 0;
554
555 }
556
557 /**************************************************************************
558 IRQ - Wait for a frame
559 ***************************************************************************/
560 static void r8169_irq(struct nic *nic __unused, irq_action_t action)
561 {
562 int intr_status = 0;
563 int interested = RxOverflow | RxFIFOOver | RxErr | RxOK;
564
565 switch (action) {
566 case DISABLE:
567 case ENABLE:
568 intr_status = RTL_R16(IntrStatus);
569 /* h/w no longer present (hotplug?) or major error,
570 bail */
571 if (intr_status == 0xFFFF)
572 break;
573
574 intr_status = intr_status & ~interested;
575 if (action == ENABLE)
576 intr_status = intr_status | interested;
577 RTL_W16(IntrMask, intr_status);
578 break;
579 case FORCE:
580 RTL_W8(TxPoll, (RTL_R8(TxPoll) | 0x01));
581 break;
582 }
583 }
584
585 /**************************************************************************
586 POLL - Wait for a frame
587 ***************************************************************************/
588 static int r8169_poll(struct nic *nic, int retreive)
589 {
590 /* return true if there's an ethernet packet ready to read */
591 /* nic->packet should contain data on return */
592 /* nic->packetlen should contain length of data */
593 int cur_rx;
594 unsigned int intr_status = 0;
595 cur_rx = tpc->cur_rx;
596 if ((tpc->RxDescArray[cur_rx].status & OWNbit) == 0) {
597 /* There is a packet ready */
598 if (!retreive)
599 return 1;
600 intr_status = RTL_R16(IntrStatus);
601 /* h/w no longer present (hotplug?) or major error,
602 bail */
603 if (intr_status == 0xFFFF)
604 return 0;
605 RTL_W16(IntrStatus, intr_status &
606 ~(RxFIFOOver | RxOverflow | RxOK));
607
608 if (!(tpc->RxDescArray[cur_rx].status & RxRES)) {
609 nic->packetlen = (int) (tpc->RxDescArray[cur_rx].
610 status & 0x00001FFF) - 4;
611 memcpy(nic->packet, tpc->RxBufferRing[cur_rx],
612 nic->packetlen);
613 if (cur_rx == NUM_RX_DESC - 1)
614 tpc->RxDescArray[cur_rx].status =
615 (OWNbit | EORbit) + RX_BUF_SIZE;
616 else
617 tpc->RxDescArray[cur_rx].status =
618 OWNbit + RX_BUF_SIZE;
619 tpc->RxDescArray[cur_rx].buf_addr =
620 virt_to_bus(tpc->RxBufferRing[cur_rx]);
621 } else
622 printf("Error Rx");
623 /* FIXME: shouldn't I reset the status on an error */
624 cur_rx = (cur_rx + 1) % NUM_RX_DESC;
625 tpc->cur_rx = cur_rx;
626 RTL_W16(IntrStatus, intr_status &
627 (RxFIFOOver | RxOverflow | RxOK));
628
629 return 1;
630
631 }
632 tpc->cur_rx = cur_rx;
633 /* FIXME: There is no reason to do this as cur_rx did not change */
634
635 return (0); /* initially as this is called to flush the input */
636
637 }
638
639 /**************************************************************************
640 TRANSMIT - Transmit a frame
641 ***************************************************************************/
642 static void r8169_transmit(struct nic *nic, const char *d, /* Destination */
643 unsigned int t, /* Type */
644 unsigned int s, /* size */
645 const char *p)
646 { /* Packet */
647 /* send the packet to destination */
648
649 u16 nstype;
650 u32 to;
651 u8 *ptxb;
652 int entry = tpc->cur_tx % NUM_TX_DESC;
653
654 /* point to the current txb incase multiple tx_rings are used */
655 ptxb = tpc->Tx_skbuff[entry * MAX_ETH_FRAME_SIZE];
656 memcpy(ptxb, d, ETH_ALEN);
657 memcpy(ptxb + ETH_ALEN, nic->node_addr, ETH_ALEN);
658 nstype = htons((u16) t);
659 memcpy(ptxb + 2 * ETH_ALEN, (u8 *) & nstype, 2);
660 memcpy(ptxb + ETH_HLEN, p, s);
661 s += ETH_HLEN;
662 s &= 0x0FFF;
663 while (s < ETH_ZLEN)
664 ptxb[s++] = '\0';
665
666 tpc->TxDescArray[entry].buf_addr = virt_to_bus(ptxb);
667 if (entry != (NUM_TX_DESC - 1))
668 tpc->TxDescArray[entry].status =
669 (OWNbit | FSbit | LSbit) | ((s > ETH_ZLEN) ? s :
670 ETH_ZLEN);
671 else
672 tpc->TxDescArray[entry].status =
673 (OWNbit | EORbit | FSbit | LSbit) | ((s > ETH_ZLEN) ? s
674 : ETH_ZLEN);
675 RTL_W8(TxPoll, 0x40); /* set polling bit */
676
677 tpc->cur_tx++;
678 to = currticks() + TX_TIMEOUT;
679 while ((tpc->TxDescArray[entry].status & OWNbit) && (currticks() < to)); /* wait */
680
681 if (currticks() >= to) {
682 printf("TX Time Out");
683 }
684 }
685
686 static void rtl8169_set_rx_mode(struct nic *nic __unused)
687 {
688 u32 mc_filter[2]; /* Multicast hash filter */
689 int rx_mode;
690 u32 tmp = 0;
691
692 /* IFF_ALLMULTI */
693 /* Too many to filter perfectly -- accept all multicasts. */
694 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
695 mc_filter[1] = mc_filter[0] = 0xffffffff;
696
697 tmp =
698 rtl8169_rx_config | rx_mode | (RTL_R32(RxConfig) &
699 rtl_chip_info[tpc->chipset].
700 RxConfigMask);
701
702 RTL_W32(RxConfig, tmp);
703 RTL_W32(MAR0 + 0, mc_filter[0]);
704 RTL_W32(MAR0 + 4, mc_filter[1]);
705 }
706 static void rtl8169_hw_start(struct nic *nic)
707 {
708 u32 i;
709
710 /* Soft reset the chip. */
711 RTL_W8(ChipCmd, CmdReset);
712
713 /* Check that the chip has finished the reset. */
714 for (i = 1000; i > 0; i--) {
715 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
716 break;
717 else
718 udelay(10);
719 }
720
721 RTL_W8(Cfg9346, Cfg9346_Unlock);
722 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
723 RTL_W8(ETThReg, ETTh);
724
725 /* For gigabit rtl8169 */
726 RTL_W16(RxMaxSize, RxPacketMaxSize);
727
728 /* Set Rx Config register */
729 i = rtl8169_rx_config | (RTL_R32(RxConfig) &
730 rtl_chip_info[tpc->chipset].RxConfigMask);
731 RTL_W32(RxConfig, i);
732
733 /* Set DMA burst size and Interframe Gap Time */
734 RTL_W32(TxConfig,
735 (TX_DMA_BURST << TxDMAShift) | (InterFrameGap <<
736 TxInterFrameGapShift));
737
738
739 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd));
740
741 if (tpc->mcfg == MCFG_METHOD_2 || tpc->mcfg == MCFG_METHOD_3) {
742 RTL_W16(CPlusCmd,
743 (RTL_R16(CPlusCmd) | (1 << 14) | (1 << 3)));
744 DBG
745 ("Set MAC Reg C+CR Offset 0xE0: bit-3 and bit-14\n");
746 } else {
747 RTL_W16(CPlusCmd, (RTL_R16(CPlusCmd) | (1 << 3)));
748 DBG("Set MAC Reg C+CR Offset 0xE0: bit-3.\n");
749 }
750
751 {
752 //RTL_W16(0xE2, 0x1517);
753 //RTL_W16(0xE2, 0x152a);
754 //RTL_W16(0xE2, 0x282a);
755 RTL_W16(0xE2, 0x0000);
756 }
757
758
759
760 tpc->cur_rx = 0;
761
762 RTL_W32(TxDescStartAddr, virt_to_le32desc(tpc->TxDescArray));
763 RTL_W32(RxDescStartAddr, virt_to_le32desc(tpc->RxDescArray));
764 RTL_W8(Cfg9346, Cfg9346_Lock);
765 udelay(10);
766
767 RTL_W32(RxMissed, 0);
768
769 rtl8169_set_rx_mode(nic);
770
771 /* no early-rx interrupts */
772 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
773
774 RTL_W16(IntrMask, rtl8169_intr_mask);
775
776 }
777
778 static void rtl8169_init_ring(struct nic *nic __unused)
779 {
780 int i;
781
782 tpc->cur_rx = 0;
783 tpc->cur_tx = 0;
784 memset(tpc->TxDescArray, 0x0, NUM_TX_DESC * sizeof(struct TxDesc));
785 memset(tpc->RxDescArray, 0x0, NUM_RX_DESC * sizeof(struct RxDesc));
786
787 for (i = 0; i < NUM_TX_DESC; i++) {
788 tpc->Tx_skbuff[i] = &txb[i];
789 }
790
791 for (i = 0; i < NUM_RX_DESC; i++) {
792 if (i == (NUM_RX_DESC - 1))
793 tpc->RxDescArray[i].status =
794 (OWNbit | EORbit) | RX_BUF_SIZE;
795 else
796 tpc->RxDescArray[i].status = OWNbit | RX_BUF_SIZE;
797
798 tpc->RxBufferRing[i] = &rxb[i * RX_BUF_SIZE];
799 tpc->RxDescArray[i].buf_addr =
800 virt_to_bus(tpc->RxBufferRing[i]);
801 }
802 }
803
804 /**************************************************************************
805 RESET - Finish setting up the ethernet interface
806 ***************************************************************************/
807 static void r8169_reset(struct nic *nic)
808 {
809 int i;
810
811 tpc->TxDescArray = tx_ring;
812 tpc->RxDescArray = rx_ring;
813
814 rtl8169_init_ring(nic);
815 rtl8169_hw_start(nic);
816 /* Construct a perfect filter frame with the mac address as first match
817 * and broadcast for all others */
818 for (i = 0; i < 192; i++)
819 txb[i] = 0xFF;
820
821 txb[0] = nic->node_addr[0];
822 txb[1] = nic->node_addr[1];
823 txb[2] = nic->node_addr[2];
824 txb[3] = nic->node_addr[3];
825 txb[4] = nic->node_addr[4];
826 txb[5] = nic->node_addr[5];
827 }
828
829 /**************************************************************************
830 DISABLE - Turn off ethernet interface
831 ***************************************************************************/
832 static void r8169_disable ( struct nic *nic __unused ) {
833 int i;
834 /* Stop the chip's Tx and Rx DMA processes. */
835 RTL_W8(ChipCmd, 0x00);
836
837 /* Disable interrupts by clearing the interrupt mask. */
838 RTL_W16(IntrMask, 0x0000);
839
840 RTL_W32(RxMissed, 0);
841
842 tpc->TxDescArray = NULL;
843 tpc->RxDescArray = NULL;
844 for (i = 0; i < NUM_RX_DESC; i++) {
845 tpc->RxBufferRing[i] = NULL;
846 }
847 }
848
849 static struct nic_operations r8169_operations = {
850 .connect = dummy_connect,
851 .poll = r8169_poll,
852 .transmit = r8169_transmit,
853 .irq = r8169_irq,
854
855 };
856
857 static struct pci_device_id r8169_nics[] = {
858 PCI_ROM(0x10ec, 0x8169, "r8169", "RealTek RTL8169 Gigabit Ethernet"),
859 PCI_ROM(0x16ec, 0x0116, "usr-r8169", "US Robotics RTL8169 Gigabit Ethernet"),
860 PCI_ROM(0x1186, 0x4300, "dlink-r8169", "D-Link RTL8169 Gigabit Ethernet"),
861 PCI_ROM(0x1737, 0x1032, "linksys-r8169", "Linksys RTL8169 Gigabit Ethernet"),
862 };
863
864 PCI_DRIVER ( r8169_driver, r8169_nics, PCI_NO_CLASS );
865
866 /**************************************************************************
867 PROBE - Look for an adapter, this routine's visible to the outside
868 ***************************************************************************/
869
870 #define board_found 1
871 #define valid_link 0
872 static int r8169_probe ( struct nic *nic, struct pci_device *pci ) {
873
874 static int board_idx = -1;
875 static int printed_version = 0;
876 int i, rc;
877 int option = -1, Cap10_100 = 0, Cap1000 = 0;
878
879 printf ( "r8169.c: Found %s, Vendor=%hX Device=%hX\n",
880 pci->driver_name, pci->vendor, pci->device );
881
882 board_idx++;
883
884 printed_version = 1;
885
886 /* Quick and very dirty hack to get r8169 driver working
887 * again, pre-rewrite
888 */
889 if ( ! r8169_bufs )
890 r8169_bufs = malloc_dma ( sizeof ( *r8169_bufs ), 256 );
891 if ( ! r8169_bufs )
892 return 0;
893 memset ( r8169_bufs, 0, sizeof ( *r8169_bufs ) );
894
895 /* point to private storage */
896 tpc = &tpx;
897
898 rc = rtl8169_init_board(pci); /* Return code is meaningless */
899
900 /* Get MAC address. FIXME: read EEPROM */
901 for (i = 0; i < MAC_ADDR_LEN; i++)
902 nic->node_addr[i] = RTL_R8(MAC0 + i);
903
904 DBG ( "%s: Identified chip type is '%s'.\n", pci->driver_name,
905 rtl_chip_info[tpc->chipset].name );
906
907 /* Print out some hardware info */
908 DBG ( "%s: %s at IOAddr %#hX, ", pci->driver_name, eth_ntoa ( nic->node_addr ),
909 (unsigned int) ioaddr );
910
911 /* Config PHY */
912 rtl8169_hw_PHY_config(nic);
913
914 DBG("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
915 RTL_W8(0x82, 0x01);
916
917 if (tpc->mcfg < MCFG_METHOD_3) {
918 DBG("Set PCI Latency=0x40\n");
919 pci_write_config_byte(pci, PCI_LATENCY_TIMER, 0x40);
920 }
921
922 if (tpc->mcfg == MCFG_METHOD_2) {
923 DBG("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
924 RTL_W8(0x82, 0x01);
925 DBG("Set PHY Reg 0x0bh = 0x00h\n");
926 RTL8169_WRITE_GMII_REG(ioaddr, 0x0b, 0x0000); //w 0x0b 15 0 0
927 }
928
929 /* if TBI is not endbled */
930 if (!(RTL_R8(PHYstatus) & TBI_Enable)) {
931 int val = RTL8169_READ_GMII_REG(ioaddr, PHY_AUTO_NEGO_REG);
932
933 #ifdef RTL8169_HW_FLOW_CONTROL_SUPPORT
934 val |= PHY_Cap_PAUSE | PHY_Cap_ASYM_PAUSE;
935 #endif //end #define RTL8169_HW_FLOW_CONTROL_SUPPORT
936
937 option = media;
938 /* Force RTL8169 in 10/100/1000 Full/Half mode. */
939 if (option > 0) {
940 printf(" Force-mode Enabled.\n");
941 Cap10_100 = 0, Cap1000 = 0;
942 switch (option) {
943 case _10_Half:
944 Cap10_100 = PHY_Cap_10_Half;
945 Cap1000 = PHY_Cap_Null;
946 break;
947 case _10_Full:
948 Cap10_100 = PHY_Cap_10_Full;
949 Cap1000 = PHY_Cap_Null;
950 break;
951 case _100_Half:
952 Cap10_100 = PHY_Cap_100_Half;
953 Cap1000 = PHY_Cap_Null;
954 break;
955 case _100_Full:
956 Cap10_100 = PHY_Cap_100_Full;
957 Cap1000 = PHY_Cap_Null;
958 break;
959 case _1000_Full:
960 Cap10_100 = PHY_Cap_Null;
961 Cap1000 = PHY_Cap_1000_Full;
962 break;
963 default:
964 break;
965 }
966 RTL8169_WRITE_GMII_REG(ioaddr, PHY_AUTO_NEGO_REG, Cap10_100 | (val & 0xC1F)); //leave PHY_AUTO_NEGO_REG bit4:0 unchanged
967 RTL8169_WRITE_GMII_REG(ioaddr, PHY_1000_CTRL_REG,
968 Cap1000);
969 } else {
970 DBG ( "%s: Auto-negotiation Enabled.\n", pci->driver_name );
971
972 // enable 10/100 Full/Half Mode, leave PHY_AUTO_NEGO_REG bit4:0 unchanged
973 RTL8169_WRITE_GMII_REG(ioaddr, PHY_AUTO_NEGO_REG,
974 PHY_Cap_10_Half |
975 PHY_Cap_10_Full |
976 PHY_Cap_100_Half |
977 PHY_Cap_100_Full | (val &
978 0xC1F));
979
980 // enable 1000 Full Mode
981 // RTL8169_WRITE_GMII_REG( ioaddr, PHY_1000_CTRL_REG, PHY_Cap_1000_Full );
982 RTL8169_WRITE_GMII_REG(ioaddr, PHY_1000_CTRL_REG, PHY_Cap_1000_Full | PHY_Cap_1000_Half); //rtl8168
983
984 } // end of if( option > 0 )
985
986 // Enable auto-negotiation and restart auto-nigotiation
987 RTL8169_WRITE_GMII_REG(ioaddr, PHY_CTRL_REG,
988 PHY_Enable_Auto_Nego |
989 PHY_Restart_Auto_Nego);
990 udelay(100);
991
992 // wait for auto-negotiation process
993 for (i = 10000; i > 0; i--) {
994 //check if auto-negotiation complete
995 if (RTL8169_READ_GMII_REG(ioaddr, PHY_STAT_REG) &
996 PHY_Auto_Neco_Comp) {
997 udelay(100);
998 option = RTL_R8(PHYstatus);
999 if (option & _1000bpsF) {
1000 printf
1001 ("1000Mbps Full-duplex operation.\n");
1002 } else {
1003 printf
1004 ("%sMbps %s-duplex operation.\n",
1005 (option & _100bps) ? "100" :
1006 "10",
1007 (option & FullDup) ? "Full" :
1008 "Half");
1009 }
1010 break;
1011 } else {
1012 udelay(100);
1013 } // end of if( RTL8169_READ_GMII_REG(ioaddr, 1) & 0x20 )
1014 } // end for-loop to wait for auto-negotiation process
1015
1016
1017 } else {
1018 udelay(100);
1019 printf
1020 ("%s: 1000Mbps Full-duplex operation, TBI Link %s!\n",
1021 pci->driver_name,
1022 (RTL_R32(TBICSR) & TBILinkOK) ? "OK" : "Failed");
1023
1024 }
1025
1026 r8169_reset(nic);
1027
1028 /* point to NIC specific routines */
1029 nic->nic_op = &r8169_operations;
1030
1031 nic->irqno = pci->irq;
1032 nic->ioaddr = ioaddr;
1033
1034 return 1;
1035 }
1036
1037 //======================================================================================================
1038 /*
1039 static void rtl8169_hw_PHY_reset(struct nic *nic __unused)
1040 {
1041 int val, phy_reset_expiretime = 50;
1042 struct rtl8169_private *priv = dev->priv;
1043 unsigned long ioaddr = priv->ioaddr;
1044
1045 DBG("%s: Reset RTL8169s PHY\n", dev->name);
1046
1047 val = ( RTL8169_READ_GMII_REG( ioaddr, 0 ) | 0x8000 ) & 0xffff;
1048 RTL8169_WRITE_GMII_REG( ioaddr, 0, val );
1049
1050 do //waiting for phy reset
1051 {
1052 if( RTL8169_READ_GMII_REG( ioaddr, 0 ) & 0x8000 ){
1053 phy_reset_expiretime --;
1054 udelay(100);
1055 }
1056 else{
1057 break;
1058 }
1059 }while( phy_reset_expiretime >= 0 );
1060
1061 assert( phy_reset_expiretime > 0 );
1062 }
1063
1064 */
1065
1066 //======================================================================================================
1067 static void rtl8169_hw_PHY_config(struct nic *nic __unused)
1068 {
1069
1070 DBG("priv->mcfg=%d, priv->pcfg=%d\n", tpc->mcfg, tpc->pcfg);
1071
1072 if (tpc->mcfg == MCFG_METHOD_4) {
1073 /*
1074 RTL8169_WRITE_GMII_REG( (unsigned long)ioaddr, 0x1F, 0x0001 );
1075 RTL8169_WRITE_GMII_REG( (unsigned long)ioaddr, 0x1b, 0x841e );
1076 RTL8169_WRITE_GMII_REG( (unsigned long)ioaddr, 0x0e, 0x7bfb );
1077 RTL8169_WRITE_GMII_REG( (unsigned long)ioaddr, 0x09, 0x273a );
1078 */
1079
1080 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x1F,
1081 0x0002);
1082 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x01,
1083 0x90D0);
1084 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x1F,
1085 0x0000);
1086 } else if ((tpc->mcfg == MCFG_METHOD_2)
1087 || (tpc->mcfg == MCFG_METHOD_3)) {
1088 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x1F,
1089 0x0001);
1090 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x15,
1091 0x1000);
1092 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x18,
1093 0x65C7);
1094 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x04,
1095 0x0000);
1096 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x03,
1097 0x00A1);
1098 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x02,
1099 0x0008);
1100 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x01,
1101 0x1020);
1102 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x00,
1103 0x1000);
1104 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x04,
1105 0x0800);
1106 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x04,
1107 0x0000);
1108 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x04,
1109 0x7000);
1110 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x03,
1111 0xFF41);
1112 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x02,
1113 0xDE60);
1114 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x01,
1115 0x0140);
1116 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x00,
1117 0x0077);
1118 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x04,
1119 0x7800);
1120 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x04,
1121 0x7000);
1122 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x04,
1123 0xA000);
1124 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x03,
1125 0xDF01);
1126 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x02,
1127 0xDF20);
1128 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x01,
1129 0xFF95);
1130 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x00,
1131 0xFA00);
1132 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x04,
1133 0xA800);
1134 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x04,
1135 0xA000);
1136 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x04,
1137 0xB000);
1138 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x03,
1139 0xFF41);
1140 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x02,
1141 0xDE20);
1142 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x01,
1143 0x0140);
1144 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x00,
1145 0x00BB);
1146 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x04,
1147 0xB800);
1148 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x04,
1149 0xB000);
1150 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x04,
1151 0xF000);
1152 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x03,
1153 0xDF01);
1154 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x02,
1155 0xDF20);
1156 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x01,
1157 0xFF95);
1158 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x00,
1159 0xBF00);
1160 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x04,
1161 0xF800);
1162 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x04,
1163 0xF000);
1164 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x04,
1165 0x0000);
1166 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x1F,
1167 0x0000);
1168 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x0B,
1169 0x0000);
1170 } else {
1171 DBG("tpc->mcfg=%d. Discard hw PHY config.\n",
1172 tpc->mcfg);
1173 }
1174 }
1175
1176 DRIVER ( "r8169/PCI", nic_driver, pci_driver, r8169_driver,
1177 r8169_probe, r8169_disable );
1178
1179 /*
1180 * Local variables:
1181 * c-basic-offset: 8
1182 * c-indent-level: 8
1183 * tab-width: 8
1184 * End:
1185 */
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