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Warnings purge for via-velocity.[ch]
[gpxe.git] / src / drivers / net / via-velocity.h
blobe0b8809f1479a04196339d71a5b1aac382f1f4af
1 /*
2 * Copyright (c) 1996, 2003 VIA Networking Technologies, Inc.
3 * All rights reserved.
4 *
5 * This software may be redistributed and/or modified under
6 * the terms of the GNU General Public License as published by the Free
7 * Software Foundation; either version 2 of the License, or
8 * any later version.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
12 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * for more details.
14 *
15 * File: via-velocity.h
16 *
17 * Purpose: Header file to define driver's private structures.
18 *
19 * Author: Chuang Liang-Shing, AJ Jiang
20 *
21 * Date: Jan 24, 2003
22 *
23 * Changes for Etherboot Port:
24 * Copyright (c) 2006 by Timothy Legge <tlegge@rogers.com>
25 */
26
27 #include "timer.h"
28
29 #ifndef VELOCITY_H
30 #define VELOCITY_H
31
32 #define VELOCITY_TX_CSUM_SUPPORT
33
34 #define VELOCITY_NAME "via-velocity"
35 #define VELOCITY_FULL_DRV_NAM "VIA Networking Velocity Family Gigabit Ethernet Adapter Driver"
36 #define VELOCITY_VERSION "1.13"
37
38 #define PKT_BUF_SZ 1564
39
40 #define MAX_UNITS 8
41 #define OPTION_DEFAULT { [0 ... MAX_UNITS-1] = -1}
42
43 #define REV_ID_VT6110 (0)
44
45 #define BYTE_REG_BITS_ON(x,p) do { writeb(readb((p))|(x),(p));} while (0)
46 #define WORD_REG_BITS_ON(x,p) do { writew(readw((p))|(x),(p));} while (0)
47 #define DWORD_REG_BITS_ON(x,p) do { writel(readl((p))|(x),(p));} while (0)
48
49 #define BYTE_REG_BITS_IS_ON(x,p) (readb((p)) & (x))
50 #define WORD_REG_BITS_IS_ON(x,p) (readw((p)) & (x))
51 #define DWORD_REG_BITS_IS_ON(x,p) (readl((p)) & (x))
52
53 #define BYTE_REG_BITS_OFF(x,p) do { writeb(readb((p)) & (~(x)),(p));} while (0)
54 #define WORD_REG_BITS_OFF(x,p) do { writew(readw((p)) & (~(x)),(p));} while (0)
55 #define DWORD_REG_BITS_OFF(x,p) do { writel(readl((p)) & (~(x)),(p));} while (0)
56
57 #define BYTE_REG_BITS_SET(x,m,p) do { writeb( (readb((p)) & (~(m))) |(x),(p));} while (0)
58 #define WORD_REG_BITS_SET(x,m,p) do { writew( (readw((p)) & (~(m))) |(x),(p));} while (0)
59 #define DWORD_REG_BITS_SET(x,m,p) do { writel( (readl((p)) & (~(m)))|(x),(p));} while (0)
60
61 #define VAR_USED(p) do {(p)=(p);} while (0)
62
63 /*
64 * Purpose: Structures for MAX RX/TX descriptors.
65 */
66
67
68 #define B_OWNED_BY_CHIP 1
69 #define B_OWNED_BY_HOST 0
70
71 /*
72 * Bits in the RSR0 register
73 */
74
75 #define RSR_DETAG 0x0080
76 #define RSR_SNTAG 0x0040
77 #define RSR_RXER 0x0020
78 #define RSR_RL 0x0010
79 #define RSR_CE 0x0008
80 #define RSR_FAE 0x0004
81 #define RSR_CRC 0x0002
82 #define RSR_VIDM 0x0001
83
84 /*
85 * Bits in the RSR1 register
86 */
87
88 #define RSR_RXOK 0x8000 // rx OK
89 #define RSR_PFT 0x4000 // Perfect filtering address match
90 #define RSR_MAR 0x2000 // MAC accept multicast address packet
91 #define RSR_BAR 0x1000 // MAC accept broadcast address packet
92 #define RSR_PHY 0x0800 // MAC accept physical address packet
93 #define RSR_VTAG 0x0400 // 802.1p/1q tagging packet indicator
94 #define RSR_STP 0x0200 // start of packet
95 #define RSR_EDP 0x0100 // end of packet
96
97 /*
98 * Bits in the RSR1 register
99 */
100
101 #define RSR1_RXOK 0x80 // rx OK
102 #define RSR1_PFT 0x40 // Perfect filtering address match
103 #define RSR1_MAR 0x20 // MAC accept multicast address packet
104 #define RSR1_BAR 0x10 // MAC accept broadcast address packet
105 #define RSR1_PHY 0x08 // MAC accept physical address packet
106 #define RSR1_VTAG 0x04 // 802.1p/1q tagging packet indicator
107 #define RSR1_STP 0x02 // start of packet
108 #define RSR1_EDP 0x01 // end of packet
109
110 /*
111 * Bits in the CSM register
112 */
113
114 #define CSM_IPOK 0x40 //IP Checkusm validatiaon ok
115 #define CSM_TUPOK 0x20 //TCP/UDP Checkusm validatiaon ok
116 #define CSM_FRAG 0x10 //Fragment IP datagram
117 #define CSM_IPKT 0x04 //Received an IP packet
118 #define CSM_TCPKT 0x02 //Received a TCP packet
119 #define CSM_UDPKT 0x01 //Received a UDP packet
120
121 /*
122 * Bits in the TSR0 register
123 */
124
125 #define TSR0_ABT 0x0080 // Tx abort because of excessive collision
126 #define TSR0_OWT 0x0040 // Jumbo frame Tx abort
127 #define TSR0_OWC 0x0020 // Out of window collision
128 #define TSR0_COLS 0x0010 // experience collision in this transmit event
129 #define TSR0_NCR3 0x0008 // collision retry counter[3]
130 #define TSR0_NCR2 0x0004 // collision retry counter[2]
131 #define TSR0_NCR1 0x0002 // collision retry counter[1]
132 #define TSR0_NCR0 0x0001 // collision retry counter[0]
133 #define TSR0_TERR 0x8000 //
134 #define TSR0_FDX 0x4000 // current transaction is serviced by full duplex mode
135 #define TSR0_GMII 0x2000 // current transaction is serviced by GMII mode
136 #define TSR0_LNKFL 0x1000 // packet serviced during link down
137 #define TSR0_SHDN 0x0400 // shutdown case
138 #define TSR0_CRS 0x0200 // carrier sense lost
139 #define TSR0_CDH 0x0100 // AQE test fail (CD heartbeat)
140
141 /*
142 * Bits in the TSR1 register
143 */
144
145 #define TSR1_TERR 0x80 //
146 #define TSR1_FDX 0x40 // current transaction is serviced by full duplex mode
147 #define TSR1_GMII 0x20 // current transaction is serviced by GMII mode
148 #define TSR1_LNKFL 0x10 // packet serviced during link down
149 #define TSR1_SHDN 0x04 // shutdown case
150 #define TSR1_CRS 0x02 // carrier sense lost
151 #define TSR1_CDH 0x01 // AQE test fail (CD heartbeat)
152
153 //
154 // Bits in the TCR0 register
155 //
156 #define TCR0_TIC 0x80 // assert interrupt immediately while descriptor has been send complete
157 #define TCR0_PIC 0x40 // priority interrupt request, INA# is issued over adaptive interrupt scheme
158 #define TCR0_VETAG 0x20 // enable VLAN tag
159 #define TCR0_IPCK 0x10 // request IP checksum calculation.
160 #define TCR0_UDPCK 0x08 // request UDP checksum calculation.
161 #define TCR0_TCPCK 0x04 // request TCP checksum calculation.
162 #define TCR0_JMBO 0x02 // indicate a jumbo packet in GMAC side
163 #define TCR0_CRC 0x01 // disable CRC generation
164
165 #define TCPLS_NORMAL 3
166 #define TCPLS_START 2
167 #define TCPLS_END 1
168 #define TCPLS_MED 0
169
170
171 // max transmit or receive buffer size
172 #define CB_RX_BUF_SIZE 2048UL // max buffer size
173 // NOTE: must be multiple of 4
174
175 #define CB_MAX_RD_NUM 512 // MAX # of RD
176 #define CB_MAX_TD_NUM 256 // MAX # of TD
177
178 #define CB_INIT_RD_NUM_3119 128 // init # of RD, for setup VT3119
179 #define CB_INIT_TD_NUM_3119 64 // init # of TD, for setup VT3119
180
181 #define CB_INIT_RD_NUM 128 // init # of RD, for setup default
182 #define CB_INIT_TD_NUM 64 // init # of TD, for setup default
183
184 // for 3119
185 #define CB_TD_RING_NUM 4 // # of TD rings.
186 #define CB_MAX_SEG_PER_PKT 7 // max data seg per packet (Tx)
187
188
189 /*
190 * If collisions excess 15 times , tx will abort, and
191 * if tx fifo underflow, tx will fail
192 * we should try to resend it
193 */
194
195 #define CB_MAX_TX_ABORT_RETRY 3
196
197 /*
198 * Receive descriptor
199 */
200
201 struct rdesc0 {
202 u16 RSR; /* Receive status */
203 u16 len:14; /* Received packet length */
204 u16 reserved:1;
205 u16 owner:1; /* Who owns this buffer ? */
206 };
207
208 struct rdesc1 {
209 u16 PQTAG;
210 u8 CSM;
211 u8 IPKT;
212 };
213
214 struct rx_desc {
215 struct rdesc0 rdesc0;
216 struct rdesc1 rdesc1;
217 u32 pa_low; /* Low 32 bit PCI address */
218 u16 pa_high; /* Next 16 bit PCI address (48 total) */
219 u16 len:15; /* Frame size */
220 u16 inten:1; /* Enable interrupt */
221 } __attribute__ ((__packed__));
222
223 /*
224 * Transmit descriptor
225 */
226
227 struct tdesc0 {
228 u16 TSR; /* Transmit status register */
229 u16 pktsize:14; /* Size of frame */
230 u16 reserved:1;
231 u16 owner:1; /* Who owns the buffer */
232 };
233
234 struct pqinf { /* Priority queue info */
235 u16 VID:12;
236 u16 CFI:1;
237 u16 priority:3;
238 } __attribute__ ((__packed__));
239
240 struct tdesc1 {
241 struct pqinf pqinf;
242 u8 TCR;
243 u8 TCPLS:2;
244 u8 reserved:2;
245 u8 CMDZ:4;
246 } __attribute__ ((__packed__));
247
248 struct td_buf {
249 u32 pa_low;
250 u16 pa_high;
251 u16 bufsize:14;
252 u16 reserved:1;
253 u16 queue:1;
254 } __attribute__ ((__packed__));
255
256 struct tx_desc {
257 struct tdesc0 tdesc0;
258 struct tdesc1 tdesc1;
259 struct td_buf td_buf[7];
260 };
261
262 #ifdef LINUX
263 struct velocity_rd_info {
264 struct sk_buff *skb;
265 dma_addr_t skb_dma;
266 };
267
268
269 /**
270 * alloc_rd_info - allocate an rd info block
271 *
272 * Alocate and initialize a receive info structure used for keeping
273 * track of kernel side information related to each receive
274 * descriptor we are using
275 */
276
277 static inline struct velocity_rd_info *alloc_rd_info(void)
278 {
279 struct velocity_rd_info *ptr;
280 if ((ptr =
281 kmalloc(sizeof(struct velocity_rd_info), GFP_ATOMIC)) == NULL)
282 return NULL;
283 else {
284 memset(ptr, 0, sizeof(struct velocity_rd_info));
285 return ptr;
286 }
287 }
288
289 /*
290 * Used to track transmit side buffers.
291 */
292
293 struct velocity_td_info {
294 struct sk_buff *skb;
295 u8 *buf;
296 int nskb_dma;
297 dma_addr_t skb_dma[7];
298 dma_addr_t buf_dma;
299 };
300
301 #endif
302 enum {
303 OWNED_BY_HOST = 0,
304 OWNED_BY_NIC = 1
305 } velocity_owner;
306
307
308 /*
309 * MAC registers and macros.
310 */
311
312
313 #define MCAM_SIZE 64
314 #define VCAM_SIZE 64
315 #define TX_QUEUE_NO 4
316
317 #define MAX_HW_MIB_COUNTER 32
318 #define VELOCITY_MIN_MTU (1514-14)
319 #define VELOCITY_MAX_MTU (9000)
320
321 /*
322 * Registers in the MAC
323 */
324
325 #define MAC_REG_PAR 0x00 // physical address
326 #define MAC_REG_RCR 0x06
327 #define MAC_REG_TCR 0x07
328 #define MAC_REG_CR0_SET 0x08
329 #define MAC_REG_CR1_SET 0x09
330 #define MAC_REG_CR2_SET 0x0A
331 #define MAC_REG_CR3_SET 0x0B
332 #define MAC_REG_CR0_CLR 0x0C
333 #define MAC_REG_CR1_CLR 0x0D
334 #define MAC_REG_CR2_CLR 0x0E
335 #define MAC_REG_CR3_CLR 0x0F
336 #define MAC_REG_MAR 0x10
337 #define MAC_REG_CAM 0x10
338 #define MAC_REG_DEC_BASE_HI 0x18
339 #define MAC_REG_DBF_BASE_HI 0x1C
340 #define MAC_REG_ISR_CTL 0x20
341 #define MAC_REG_ISR_HOTMR 0x20
342 #define MAC_REG_ISR_TSUPTHR 0x20
343 #define MAC_REG_ISR_RSUPTHR 0x20
344 #define MAC_REG_ISR_CTL1 0x21
345 #define MAC_REG_TXE_SR 0x22
346 #define MAC_REG_RXE_SR 0x23
347 #define MAC_REG_ISR 0x24
348 #define MAC_REG_ISR0 0x24
349 #define MAC_REG_ISR1 0x25
350 #define MAC_REG_ISR2 0x26
351 #define MAC_REG_ISR3 0x27
352 #define MAC_REG_IMR 0x28
353 #define MAC_REG_IMR0 0x28
354 #define MAC_REG_IMR1 0x29
355 #define MAC_REG_IMR2 0x2A
356 #define MAC_REG_IMR3 0x2B
357 #define MAC_REG_TDCSR_SET 0x30
358 #define MAC_REG_RDCSR_SET 0x32
359 #define MAC_REG_TDCSR_CLR 0x34
360 #define MAC_REG_RDCSR_CLR 0x36
361 #define MAC_REG_RDBASE_LO 0x38
362 #define MAC_REG_RDINDX 0x3C
363 #define MAC_REG_TDBASE_LO 0x40
364 #define MAC_REG_RDCSIZE 0x50
365 #define MAC_REG_TDCSIZE 0x52
366 #define MAC_REG_TDINDX 0x54
367 #define MAC_REG_TDIDX0 0x54
368 #define MAC_REG_TDIDX1 0x56
369 #define MAC_REG_TDIDX2 0x58
370 #define MAC_REG_TDIDX3 0x5A
371 #define MAC_REG_PAUSE_TIMER 0x5C
372 #define MAC_REG_RBRDU 0x5E
373 #define MAC_REG_FIFO_TEST0 0x60
374 #define MAC_REG_FIFO_TEST1 0x64
375 #define MAC_REG_CAMADDR 0x68
376 #define MAC_REG_CAMCR 0x69
377 #define MAC_REG_GFTEST 0x6A
378 #define MAC_REG_FTSTCMD 0x6B
379 #define MAC_REG_MIICFG 0x6C
380 #define MAC_REG_MIISR 0x6D
381 #define MAC_REG_PHYSR0 0x6E
382 #define MAC_REG_PHYSR1 0x6F
383 #define MAC_REG_MIICR 0x70
384 #define MAC_REG_MIIADR 0x71
385 #define MAC_REG_MIIDATA 0x72
386 #define MAC_REG_SOFT_TIMER0 0x74
387 #define MAC_REG_SOFT_TIMER1 0x76
388 #define MAC_REG_CFGA 0x78
389 #define MAC_REG_CFGB 0x79
390 #define MAC_REG_CFGC 0x7A
391 #define MAC_REG_CFGD 0x7B
392 #define MAC_REG_DCFG0 0x7C
393 #define MAC_REG_DCFG1 0x7D
394 #define MAC_REG_MCFG0 0x7E
395 #define MAC_REG_MCFG1 0x7F
396
397 #define MAC_REG_TBIST 0x80
398 #define MAC_REG_RBIST 0x81
399 #define MAC_REG_PMCC 0x82
400 #define MAC_REG_STICKHW 0x83
401 #define MAC_REG_MIBCR 0x84
402 #define MAC_REG_EERSV 0x85
403 #define MAC_REG_REVID 0x86
404 #define MAC_REG_MIBREAD 0x88
405 #define MAC_REG_BPMA 0x8C
406 #define MAC_REG_EEWR_DATA 0x8C
407 #define MAC_REG_BPMD_WR 0x8F
408 #define MAC_REG_BPCMD 0x90
409 #define MAC_REG_BPMD_RD 0x91
410 #define MAC_REG_EECHKSUM 0x92
411 #define MAC_REG_EECSR 0x93
412 #define MAC_REG_EERD_DATA 0x94
413 #define MAC_REG_EADDR 0x96
414 #define MAC_REG_EMBCMD 0x97
415 #define MAC_REG_JMPSR0 0x98
416 #define MAC_REG_JMPSR1 0x99
417 #define MAC_REG_JMPSR2 0x9A
418 #define MAC_REG_JMPSR3 0x9B
419 #define MAC_REG_CHIPGSR 0x9C
420 #define MAC_REG_TESTCFG 0x9D
421 #define MAC_REG_DEBUG 0x9E
422 #define MAC_REG_CHIPGCR 0x9F
423 #define MAC_REG_WOLCR0_SET 0xA0
424 #define MAC_REG_WOLCR1_SET 0xA1
425 #define MAC_REG_PWCFG_SET 0xA2
426 #define MAC_REG_WOLCFG_SET 0xA3
427 #define MAC_REG_WOLCR0_CLR 0xA4
428 #define MAC_REG_WOLCR1_CLR 0xA5
429 #define MAC_REG_PWCFG_CLR 0xA6
430 #define MAC_REG_WOLCFG_CLR 0xA7
431 #define MAC_REG_WOLSR0_SET 0xA8
432 #define MAC_REG_WOLSR1_SET 0xA9
433 #define MAC_REG_WOLSR0_CLR 0xAC
434 #define MAC_REG_WOLSR1_CLR 0xAD
435 #define MAC_REG_PATRN_CRC0 0xB0
436 #define MAC_REG_PATRN_CRC1 0xB2
437 #define MAC_REG_PATRN_CRC2 0xB4
438 #define MAC_REG_PATRN_CRC3 0xB6
439 #define MAC_REG_PATRN_CRC4 0xB8
440 #define MAC_REG_PATRN_CRC5 0xBA
441 #define MAC_REG_PATRN_CRC6 0xBC
442 #define MAC_REG_PATRN_CRC7 0xBE
443 #define MAC_REG_BYTEMSK0_0 0xC0
444 #define MAC_REG_BYTEMSK0_1 0xC4
445 #define MAC_REG_BYTEMSK0_2 0xC8
446 #define MAC_REG_BYTEMSK0_3 0xCC
447 #define MAC_REG_BYTEMSK1_0 0xD0
448 #define MAC_REG_BYTEMSK1_1 0xD4
449 #define MAC_REG_BYTEMSK1_2 0xD8
450 #define MAC_REG_BYTEMSK1_3 0xDC
451 #define MAC_REG_BYTEMSK2_0 0xE0
452 #define MAC_REG_BYTEMSK2_1 0xE4
453 #define MAC_REG_BYTEMSK2_2 0xE8
454 #define MAC_REG_BYTEMSK2_3 0xEC
455 #define MAC_REG_BYTEMSK3_0 0xF0
456 #define MAC_REG_BYTEMSK3_1 0xF4
457 #define MAC_REG_BYTEMSK3_2 0xF8
458 #define MAC_REG_BYTEMSK3_3 0xFC
459
460 /*
461 * Bits in the RCR register
462 */
463
464 #define RCR_AS 0x80
465 #define RCR_AP 0x40
466 #define RCR_AL 0x20
467 #define RCR_PROM 0x10
468 #define RCR_AB 0x08
469 #define RCR_AM 0x04
470 #define RCR_AR 0x02
471 #define RCR_SEP 0x01
472
473 /*
474 * Bits in the TCR register
475 */
476
477 #define TCR_TB2BDIS 0x80
478 #define TCR_COLTMC1 0x08
479 #define TCR_COLTMC0 0x04
480 #define TCR_LB1 0x02 /* loopback[1] */
481 #define TCR_LB0 0x01 /* loopback[0] */
482
483 /*
484 * Bits in the CR0 register
485 */
486
487 #define CR0_TXON 0x00000008UL
488 #define CR0_RXON 0x00000004UL
489 #define CR0_STOP 0x00000002UL /* stop MAC, default = 1 */
490 #define CR0_STRT 0x00000001UL /* start MAC */
491 #define CR0_SFRST 0x00008000UL /* software reset */
492 #define CR0_TM1EN 0x00004000UL
493 #define CR0_TM0EN 0x00002000UL
494 #define CR0_DPOLL 0x00000800UL /* disable rx/tx auto polling */
495 #define CR0_DISAU 0x00000100UL
496 #define CR0_XONEN 0x00800000UL
497 #define CR0_FDXTFCEN 0x00400000UL /* full-duplex TX flow control enable */
498 #define CR0_FDXRFCEN 0x00200000UL /* full-duplex RX flow control enable */
499 #define CR0_HDXFCEN 0x00100000UL /* half-duplex flow control enable */
500 #define CR0_XHITH1 0x00080000UL /* TX XON high threshold 1 */
501 #define CR0_XHITH0 0x00040000UL /* TX XON high threshold 0 */
502 #define CR0_XLTH1 0x00020000UL /* TX pause frame low threshold 1 */
503 #define CR0_XLTH0 0x00010000UL /* TX pause frame low threshold 0 */
504 #define CR0_GSPRST 0x80000000UL
505 #define CR0_FORSRST 0x40000000UL
506 #define CR0_FPHYRST 0x20000000UL
507 #define CR0_DIAG 0x10000000UL
508 #define CR0_INTPCTL 0x04000000UL
509 #define CR0_GINTMSK1 0x02000000UL
510 #define CR0_GINTMSK0 0x01000000UL
511
512 /*
513 * Bits in the CR1 register
514 */
515
516 #define CR1_SFRST 0x80 /* software reset */
517 #define CR1_TM1EN 0x40
518 #define CR1_TM0EN 0x20
519 #define CR1_DPOLL 0x08 /* disable rx/tx auto polling */
520 #define CR1_DISAU 0x01
521
522 /*
523 * Bits in the CR2 register
524 */
525
526 #define CR2_XONEN 0x80
527 #define CR2_FDXTFCEN 0x40 /* full-duplex TX flow control enable */
528 #define CR2_FDXRFCEN 0x20 /* full-duplex RX flow control enable */
529 #define CR2_HDXFCEN 0x10 /* half-duplex flow control enable */
530 #define CR2_XHITH1 0x08 /* TX XON high threshold 1 */
531 #define CR2_XHITH0 0x04 /* TX XON high threshold 0 */
532 #define CR2_XLTH1 0x02 /* TX pause frame low threshold 1 */
533 #define CR2_XLTH0 0x01 /* TX pause frame low threshold 0 */
534
535 /*
536 * Bits in the CR3 register
537 */
538
539 #define CR3_GSPRST 0x80
540 #define CR3_FORSRST 0x40
541 #define CR3_FPHYRST 0x20
542 #define CR3_DIAG 0x10
543 #define CR3_INTPCTL 0x04
544 #define CR3_GINTMSK1 0x02
545 #define CR3_GINTMSK0 0x01
546
547 #define ISRCTL_UDPINT 0x8000
548 #define ISRCTL_TSUPDIS 0x4000
549 #define ISRCTL_RSUPDIS 0x2000
550 #define ISRCTL_PMSK1 0x1000
551 #define ISRCTL_PMSK0 0x0800
552 #define ISRCTL_INTPD 0x0400
553 #define ISRCTL_HCRLD 0x0200
554 #define ISRCTL_SCRLD 0x0100
555
556 /*
557 * Bits in the ISR_CTL1 register
558 */
559
560 #define ISRCTL1_UDPINT 0x80
561 #define ISRCTL1_TSUPDIS 0x40
562 #define ISRCTL1_RSUPDIS 0x20
563 #define ISRCTL1_PMSK1 0x10
564 #define ISRCTL1_PMSK0 0x08
565 #define ISRCTL1_INTPD 0x04
566 #define ISRCTL1_HCRLD 0x02
567 #define ISRCTL1_SCRLD 0x01
568
569 /*
570 * Bits in the TXE_SR register
571 */
572
573 #define TXESR_TFDBS 0x08
574 #define TXESR_TDWBS 0x04
575 #define TXESR_TDRBS 0x02
576 #define TXESR_TDSTR 0x01
577
578 /*
579 * Bits in the RXE_SR register
580 */
581
582 #define RXESR_RFDBS 0x08
583 #define RXESR_RDWBS 0x04
584 #define RXESR_RDRBS 0x02
585 #define RXESR_RDSTR 0x01
586
587 /*
588 * Bits in the ISR register
589 */
590
591 #define ISR_ISR3 0x80000000UL
592 #define ISR_ISR2 0x40000000UL
593 #define ISR_ISR1 0x20000000UL
594 #define ISR_ISR0 0x10000000UL
595 #define ISR_TXSTLI 0x02000000UL
596 #define ISR_RXSTLI 0x01000000UL
597 #define ISR_HFLD 0x00800000UL
598 #define ISR_UDPI 0x00400000UL
599 #define ISR_MIBFI 0x00200000UL
600 #define ISR_SHDNI 0x00100000UL
601 #define ISR_PHYI 0x00080000UL
602 #define ISR_PWEI 0x00040000UL
603 #define ISR_TMR1I 0x00020000UL
604 #define ISR_TMR0I 0x00010000UL
605 #define ISR_SRCI 0x00008000UL
606 #define ISR_LSTPEI 0x00004000UL
607 #define ISR_LSTEI 0x00002000UL
608 #define ISR_OVFI 0x00001000UL
609 #define ISR_FLONI 0x00000800UL
610 #define ISR_RACEI 0x00000400UL
611 #define ISR_TXWB1I 0x00000200UL
612 #define ISR_TXWB0I 0x00000100UL
613 #define ISR_PTX3I 0x00000080UL
614 #define ISR_PTX2I 0x00000040UL
615 #define ISR_PTX1I 0x00000020UL
616 #define ISR_PTX0I 0x00000010UL
617 #define ISR_PTXI 0x00000008UL
618 #define ISR_PRXI 0x00000004UL
619 #define ISR_PPTXI 0x00000002UL
620 #define ISR_PPRXI 0x00000001UL
621
622 /*
623 * Bits in the IMR register
624 */
625
626 #define IMR_TXSTLM 0x02000000UL
627 #define IMR_UDPIM 0x00400000UL
628 #define IMR_MIBFIM 0x00200000UL
629 #define IMR_SHDNIM 0x00100000UL
630 #define IMR_PHYIM 0x00080000UL
631 #define IMR_PWEIM 0x00040000UL
632 #define IMR_TMR1IM 0x00020000UL
633 #define IMR_TMR0IM 0x00010000UL
634
635 #define IMR_SRCIM 0x00008000UL
636 #define IMR_LSTPEIM 0x00004000UL
637 #define IMR_LSTEIM 0x00002000UL
638 #define IMR_OVFIM 0x00001000UL
639 #define IMR_FLONIM 0x00000800UL
640 #define IMR_RACEIM 0x00000400UL
641 #define IMR_TXWB1IM 0x00000200UL
642 #define IMR_TXWB0IM 0x00000100UL
643
644 #define IMR_PTX3IM 0x00000080UL
645 #define IMR_PTX2IM 0x00000040UL
646 #define IMR_PTX1IM 0x00000020UL
647 #define IMR_PTX0IM 0x00000010UL
648 #define IMR_PTXIM 0x00000008UL
649 #define IMR_PRXIM 0x00000004UL
650 #define IMR_PPTXIM 0x00000002UL
651 #define IMR_PPRXIM 0x00000001UL
652
653 /* 0x0013FB0FUL = initial value of IMR */
654
655 #define INT_MASK_DEF ( IMR_PPTXIM|IMR_PPRXIM| IMR_PTXIM|IMR_PRXIM | \
656 IMR_PWEIM|IMR_TXWB0IM|IMR_TXWB1IM|IMR_FLONIM| \
657 IMR_OVFIM|IMR_LSTEIM|IMR_LSTPEIM|IMR_SRCIM|IMR_MIBFIM|\
658 IMR_SHDNIM |IMR_TMR1IM|IMR_TMR0IM|IMR_TXSTLM )
659
660 /*
661 * Bits in the TDCSR0/1, RDCSR0 register
662 */
663
664 #define TRDCSR_DEAD 0x0008
665 #define TRDCSR_WAK 0x0004
666 #define TRDCSR_ACT 0x0002
667 #define TRDCSR_RUN 0x0001
668
669 /*
670 * Bits in the CAMADDR register
671 */
672
673 #define CAMADDR_CAMEN 0x80
674 #define CAMADDR_VCAMSL 0x40
675
676 /*
677 * Bits in the CAMCR register
678 */
679
680 #define CAMCR_PS1 0x80
681 #define CAMCR_PS0 0x40
682 #define CAMCR_AITRPKT 0x20
683 #define CAMCR_AITR16 0x10
684 #define CAMCR_CAMRD 0x08
685 #define CAMCR_CAMWR 0x04
686 #define CAMCR_PS_CAM_MASK 0x40
687 #define CAMCR_PS_CAM_DATA 0x80
688 #define CAMCR_PS_MAR 0x00
689
690 /*
691 * Bits in the MIICFG register
692 */
693
694 #define MIICFG_MPO1 0x80
695 #define MIICFG_MPO0 0x40
696 #define MIICFG_MFDC 0x20
697
698 /*
699 * Bits in the MIISR register
700 */
701
702 #define MIISR_MIDLE 0x80
703
704 /*
705 * Bits in the PHYSR0 register
706 */
707
708 #define PHYSR0_PHYRST 0x80
709 #define PHYSR0_LINKGD 0x40
710 #define PHYSR0_FDPX 0x10
711 #define PHYSR0_SPDG 0x08
712 #define PHYSR0_SPD10 0x04
713 #define PHYSR0_RXFLC 0x02
714 #define PHYSR0_TXFLC 0x01
715
716 /*
717 * Bits in the PHYSR1 register
718 */
719
720 #define PHYSR1_PHYTBI 0x01
721
722 /*
723 * Bits in the MIICR register
724 */
725
726 #define MIICR_MAUTO 0x80
727 #define MIICR_RCMD 0x40
728 #define MIICR_WCMD 0x20
729 #define MIICR_MDPM 0x10
730 #define MIICR_MOUT 0x08
731 #define MIICR_MDO 0x04
732 #define MIICR_MDI 0x02
733 #define MIICR_MDC 0x01
734
735 /*
736 * Bits in the MIIADR register
737 */
738
739 #define MIIADR_SWMPL 0x80
740
741 /*
742 * Bits in the CFGA register
743 */
744
745 #define CFGA_PMHCTG 0x08
746 #define CFGA_GPIO1PD 0x04
747 #define CFGA_ABSHDN 0x02
748 #define CFGA_PACPI 0x01
749
750 /*
751 * Bits in the CFGB register
752 */
753
754 #define CFGB_GTCKOPT 0x80
755 #define CFGB_MIIOPT 0x40
756 #define CFGB_CRSEOPT 0x20
757 #define CFGB_OFSET 0x10
758 #define CFGB_CRANDOM 0x08
759 #define CFGB_CAP 0x04
760 #define CFGB_MBA 0x02
761 #define CFGB_BAKOPT 0x01
762
763 /*
764 * Bits in the CFGC register
765 */
766
767 #define CFGC_EELOAD 0x80
768 #define CFGC_BROPT 0x40
769 #define CFGC_DLYEN 0x20
770 #define CFGC_DTSEL 0x10
771 #define CFGC_BTSEL 0x08
772 #define CFGC_BPS2 0x04 /* bootrom select[2] */
773 #define CFGC_BPS1 0x02 /* bootrom select[1] */
774 #define CFGC_BPS0 0x01 /* bootrom select[0] */
775
776 /*
777 * Bits in the CFGD register
778 */
779
780 #define CFGD_IODIS 0x80
781 #define CFGD_MSLVDACEN 0x40
782 #define CFGD_CFGDACEN 0x20
783 #define CFGD_PCI64EN 0x10
784 #define CFGD_HTMRL4 0x08
785
786 /*
787 * Bits in the DCFG1 register
788 */
789
790 #define DCFG_XMWI 0x8000
791 #define DCFG_XMRM 0x4000
792 #define DCFG_XMRL 0x2000
793 #define DCFG_PERDIS 0x1000
794 #define DCFG_MRWAIT 0x0400
795 #define DCFG_MWWAIT 0x0200
796 #define DCFG_LATMEN 0x0100
797
798 /*
799 * Bits in the MCFG0 register
800 */
801
802 #define MCFG_RXARB 0x0080
803 #define MCFG_RFT1 0x0020
804 #define MCFG_RFT0 0x0010
805 #define MCFG_LOWTHOPT 0x0008
806 #define MCFG_PQEN 0x0004
807 #define MCFG_RTGOPT 0x0002
808 #define MCFG_VIDFR 0x0001
809
810 /*
811 * Bits in the MCFG1 register
812 */
813
814 #define MCFG_TXARB 0x8000
815 #define MCFG_TXQBK1 0x0800
816 #define MCFG_TXQBK0 0x0400
817 #define MCFG_TXQNOBK 0x0200
818 #define MCFG_SNAPOPT 0x0100
819
820 /*
821 * Bits in the PMCC register
822 */
823
824 #define PMCC_DSI 0x80
825 #define PMCC_D2_DIS 0x40
826 #define PMCC_D1_DIS 0x20
827 #define PMCC_D3C_EN 0x10
828 #define PMCC_D3H_EN 0x08
829 #define PMCC_D2_EN 0x04
830 #define PMCC_D1_EN 0x02
831 #define PMCC_D0_EN 0x01
832
833 /*
834 * Bits in STICKHW
835 */
836
837 #define STICKHW_SWPTAG 0x10
838 #define STICKHW_WOLSR 0x08
839 #define STICKHW_WOLEN 0x04
840 #define STICKHW_DS1 0x02 /* R/W by software/cfg cycle */
841 #define STICKHW_DS0 0x01 /* suspend well DS write port */
842
843 /*
844 * Bits in the MIBCR register
845 */
846
847 #define MIBCR_MIBISTOK 0x80
848 #define MIBCR_MIBISTGO 0x40
849 #define MIBCR_MIBINC 0x20
850 #define MIBCR_MIBHI 0x10
851 #define MIBCR_MIBFRZ 0x08
852 #define MIBCR_MIBFLSH 0x04
853 #define MIBCR_MPTRINI 0x02
854 #define MIBCR_MIBCLR 0x01
855
856 /*
857 * Bits in the EERSV register
858 */
859
860 #define EERSV_BOOT_RPL ((u8) 0x01) /* Boot method selection for VT6110 */
861
862 #define EERSV_BOOT_MASK ((u8) 0x06)
863 #define EERSV_BOOT_INT19 ((u8) 0x00)
864 #define EERSV_BOOT_INT18 ((u8) 0x02)
865 #define EERSV_BOOT_LOCAL ((u8) 0x04)
866 #define EERSV_BOOT_BEV ((u8) 0x06)
867
868
869 /*
870 * Bits in BPCMD
871 */
872
873 #define BPCMD_BPDNE 0x80
874 #define BPCMD_EBPWR 0x02
875 #define BPCMD_EBPRD 0x01
876
877 /*
878 * Bits in the EECSR register
879 */
880
881 #define EECSR_EMBP 0x40 /* eeprom embeded programming */
882 #define EECSR_RELOAD 0x20 /* eeprom content reload */
883 #define EECSR_DPM 0x10 /* eeprom direct programming */
884 #define EECSR_ECS 0x08 /* eeprom CS pin */
885 #define EECSR_ECK 0x04 /* eeprom CK pin */
886 #define EECSR_EDI 0x02 /* eeprom DI pin */
887 #define EECSR_EDO 0x01 /* eeprom DO pin */
888
889 /*
890 * Bits in the EMBCMD register
891 */
892
893 #define EMBCMD_EDONE 0x80
894 #define EMBCMD_EWDIS 0x08
895 #define EMBCMD_EWEN 0x04
896 #define EMBCMD_EWR 0x02
897 #define EMBCMD_ERD 0x01
898
899 /*
900 * Bits in TESTCFG register
901 */
902
903 #define TESTCFG_HBDIS 0x80
904
905 /*
906 * Bits in CHIPGCR register
907 */
908
909 #define CHIPGCR_FCGMII 0x80
910 #define CHIPGCR_FCFDX 0x40
911 #define CHIPGCR_FCRESV 0x20
912 #define CHIPGCR_FCMODE 0x10
913 #define CHIPGCR_LPSOPT 0x08
914 #define CHIPGCR_TM1US 0x04
915 #define CHIPGCR_TM0US 0x02
916 #define CHIPGCR_PHYINTEN 0x01
917
918 /*
919 * Bits in WOLCR0
920 */
921
922 #define WOLCR_MSWOLEN7 0x0080 /* enable pattern match filtering */
923 #define WOLCR_MSWOLEN6 0x0040
924 #define WOLCR_MSWOLEN5 0x0020
925 #define WOLCR_MSWOLEN4 0x0010
926 #define WOLCR_MSWOLEN3 0x0008
927 #define WOLCR_MSWOLEN2 0x0004
928 #define WOLCR_MSWOLEN1 0x0002
929 #define WOLCR_MSWOLEN0 0x0001
930 #define WOLCR_ARP_EN 0x0001
931
932 /*
933 * Bits in WOLCR1
934 */
935
936 #define WOLCR_LINKOFF_EN 0x0800 /* link off detected enable */
937 #define WOLCR_LINKON_EN 0x0400 /* link on detected enable */
938 #define WOLCR_MAGIC_EN 0x0200 /* magic packet filter enable */
939 #define WOLCR_UNICAST_EN 0x0100 /* unicast filter enable */
940
941
942 /*
943 * Bits in PWCFG
944 */
945
946 #define PWCFG_PHYPWOPT 0x80 /* internal MII I/F timing */
947 #define PWCFG_PCISTICK 0x40 /* PCI sticky R/W enable */
948 #define PWCFG_WOLTYPE 0x20 /* pulse(1) or button (0) */
949 #define PWCFG_LEGCY_WOL 0x10
950 #define PWCFG_PMCSR_PME_SR 0x08
951 #define PWCFG_PMCSR_PME_EN 0x04 /* control by PCISTICK */
952 #define PWCFG_LEGACY_WOLSR 0x02 /* Legacy WOL_SR shadow */
953 #define PWCFG_LEGACY_WOLEN 0x01 /* Legacy WOL_EN shadow */
954
955 /*
956 * Bits in WOLCFG
957 */
958
959 #define WOLCFG_PMEOVR 0x80 /* for legacy use, force PMEEN always */
960 #define WOLCFG_SAM 0x20 /* accept multicast case reset, default=0 */
961 #define WOLCFG_SAB 0x10 /* accept broadcast case reset, default=0 */
962 #define WOLCFG_SMIIACC 0x08 /* ?? */
963 #define WOLCFG_SGENWH 0x02
964 #define WOLCFG_PHYINTEN 0x01 /* 0:PHYINT trigger enable, 1:use internal MII
965 to report status change */
966 /*
967 * Bits in WOLSR1
968 */
969
970 #define WOLSR_LINKOFF_INT 0x0800
971 #define WOLSR_LINKON_INT 0x0400
972 #define WOLSR_MAGIC_INT 0x0200
973 #define WOLSR_UNICAST_INT 0x0100
974
975 /*
976 * Ethernet address filter type
977 */
978
979 #define PKT_TYPE_NONE 0x0000 /* Turn off receiver */
980 #define PKT_TYPE_DIRECTED 0x0001 /* obselete, directed address is always accepted */
981 #define PKT_TYPE_MULTICAST 0x0002
982 #define PKT_TYPE_ALL_MULTICAST 0x0004
983 #define PKT_TYPE_BROADCAST 0x0008
984 #define PKT_TYPE_PROMISCUOUS 0x0020
985 #define PKT_TYPE_LONG 0x2000 /* NOTE.... the definition of LONG is >2048 bytes in our chip */
986 #define PKT_TYPE_RUNT 0x4000
987 #define PKT_TYPE_ERROR 0x8000 /* Accept error packets, e.g. CRC error */
988
989 /*
990 * Loopback mode
991 */
992
993 #define MAC_LB_NONE 0x00
994 #define MAC_LB_INTERNAL 0x01
995 #define MAC_LB_EXTERNAL 0x02
996
997 /*
998 * Enabled mask value of irq
999 */
1000
1001 #if defined(_SIM)
1002 #define IMR_MASK_VALUE 0x0033FF0FUL /* initial value of IMR
1003 set IMR0 to 0x0F according to spec */
1004
1005 #else
1006 #define IMR_MASK_VALUE 0x0013FB0FUL /* initial value of IMR
1007 ignore MIBFI,RACEI to
1008 reduce intr. frequency
1009 NOTE.... do not enable NoBuf int mask at driver driver
1010 when (1) NoBuf -> RxThreshold = SF
1011 (2) OK -> RxThreshold = original value
1012 */
1013 #endif
1014
1015 /*
1016 * Revision id
1017 */
1018
1019 #define REV_ID_VT3119_A0 0x00
1020 #define REV_ID_VT3119_A1 0x01
1021 #define REV_ID_VT3216_A0 0x10
1022
1023 /*
1024 * Max time out delay time
1025 */
1026
1027 #define W_MAX_TIMEOUT 0x0FFFU
1028
1029
1030 /*
1031 * MAC registers as a structure. Cannot be directly accessed this
1032 * way but generates offsets for readl/writel() calls
1033 */
1034
1035 struct mac_regs {
1036 volatile u8 PAR[6]; /* 0x00 */
1037 volatile u8 RCR;
1038 volatile u8 TCR;
1039
1040 volatile u32 CR0Set; /* 0x08 */
1041 volatile u32 CR0Clr; /* 0x0C */
1042
1043 volatile u8 MARCAM[8]; /* 0x10 */
1044
1045 volatile u32 DecBaseHi; /* 0x18 */
1046 volatile u16 DbfBaseHi; /* 0x1C */
1047 volatile u16 reserved_1E;
1048
1049 volatile u16 ISRCTL; /* 0x20 */
1050 volatile u8 TXESR;
1051 volatile u8 RXESR;
1052
1053 volatile u32 ISR; /* 0x24 */
1054 volatile u32 IMR;
1055
1056 volatile u32 TDStatusPort; /* 0x2C */
1057
1058 volatile u16 TDCSRSet; /* 0x30 */
1059 volatile u8 RDCSRSet;
1060 volatile u8 reserved_33;
1061 volatile u16 TDCSRClr;
1062 volatile u8 RDCSRClr;
1063 volatile u8 reserved_37;
1064
1065 volatile u32 RDBaseLo; /* 0x38 */
1066 volatile u16 RDIdx; /* 0x3C */
1067 volatile u16 reserved_3E;
1068
1069 volatile u32 TDBaseLo[4]; /* 0x40 */
1070
1071 volatile u16 RDCSize; /* 0x50 */
1072 volatile u16 TDCSize; /* 0x52 */
1073 volatile u16 TDIdx[4]; /* 0x54 */
1074 volatile u16 tx_pause_timer; /* 0x5C */
1075 volatile u16 RBRDU; /* 0x5E */
1076
1077 volatile u32 FIFOTest0; /* 0x60 */
1078 volatile u32 FIFOTest1; /* 0x64 */
1079
1080 volatile u8 CAMADDR; /* 0x68 */
1081 volatile u8 CAMCR; /* 0x69 */
1082 volatile u8 GFTEST; /* 0x6A */
1083 volatile u8 FTSTCMD; /* 0x6B */
1084
1085 volatile u8 MIICFG; /* 0x6C */
1086 volatile u8 MIISR;
1087 volatile u8 PHYSR0;
1088 volatile u8 PHYSR1;
1089 volatile u8 MIICR;
1090 volatile u8 MIIADR;
1091 volatile u16 MIIDATA;
1092
1093 volatile u16 SoftTimer0; /* 0x74 */
1094 volatile u16 SoftTimer1;
1095
1096 volatile u8 CFGA; /* 0x78 */
1097 volatile u8 CFGB;
1098 volatile u8 CFGC;
1099 volatile u8 CFGD;
1100
1101 volatile u16 DCFG; /* 0x7C */
1102 volatile u16 MCFG;
1103
1104 volatile u8 TBIST; /* 0x80 */
1105 volatile u8 RBIST;
1106 volatile u8 PMCPORT;
1107 volatile u8 STICKHW;
1108
1109 volatile u8 MIBCR; /* 0x84 */
1110 volatile u8 reserved_85;
1111 volatile u8 rev_id;
1112 volatile u8 PORSTS;
1113
1114 volatile u32 MIBData; /* 0x88 */
1115
1116 volatile u16 EEWrData;
1117
1118 volatile u8 reserved_8E;
1119 volatile u8 BPMDWr;
1120 volatile u8 BPCMD;
1121 volatile u8 BPMDRd;
1122
1123 volatile u8 EECHKSUM; /* 0x92 */
1124 volatile u8 EECSR;
1125
1126 volatile u16 EERdData; /* 0x94 */
1127 volatile u8 EADDR;
1128 volatile u8 EMBCMD;
1129
1130
1131 volatile u8 JMPSR0; /* 0x98 */
1132 volatile u8 JMPSR1;
1133 volatile u8 JMPSR2;
1134 volatile u8 JMPSR3;
1135 volatile u8 CHIPGSR; /* 0x9C */
1136 volatile u8 TESTCFG;
1137 volatile u8 DEBUG;
1138 volatile u8 CHIPGCR;
1139
1140 volatile u16 WOLCRSet; /* 0xA0 */
1141 volatile u8 PWCFGSet;
1142 volatile u8 WOLCFGSet;
1143
1144 volatile u16 WOLCRClr; /* 0xA4 */
1145 volatile u8 PWCFGCLR;
1146 volatile u8 WOLCFGClr;
1147
1148 volatile u16 WOLSRSet; /* 0xA8 */
1149 volatile u16 reserved_AA;
1150
1151 volatile u16 WOLSRClr; /* 0xAC */
1152 volatile u16 reserved_AE;
1153
1154 volatile u16 PatternCRC[8]; /* 0xB0 */
1155 volatile u32 ByteMask[4][4]; /* 0xC0 */
1156 } __attribute__ ((__packed__));
1157
1158
1159 enum hw_mib {
1160 HW_MIB_ifRxAllPkts = 0,
1161 HW_MIB_ifRxOkPkts,
1162 HW_MIB_ifTxOkPkts,
1163 HW_MIB_ifRxErrorPkts,
1164 HW_MIB_ifRxRuntOkPkt,
1165 HW_MIB_ifRxRuntErrPkt,
1166 HW_MIB_ifRx64Pkts,
1167 HW_MIB_ifTx64Pkts,
1168 HW_MIB_ifRx65To127Pkts,
1169 HW_MIB_ifTx65To127Pkts,
1170 HW_MIB_ifRx128To255Pkts,
1171 HW_MIB_ifTx128To255Pkts,
1172 HW_MIB_ifRx256To511Pkts,
1173 HW_MIB_ifTx256To511Pkts,
1174 HW_MIB_ifRx512To1023Pkts,
1175 HW_MIB_ifTx512To1023Pkts,
1176 HW_MIB_ifRx1024To1518Pkts,
1177 HW_MIB_ifTx1024To1518Pkts,
1178 HW_MIB_ifTxEtherCollisions,
1179 HW_MIB_ifRxPktCRCE,
1180 HW_MIB_ifRxJumboPkts,
1181 HW_MIB_ifTxJumboPkts,
1182 HW_MIB_ifRxMacControlFrames,
1183 HW_MIB_ifTxMacControlFrames,
1184 HW_MIB_ifRxPktFAE,
1185 HW_MIB_ifRxLongOkPkt,
1186 HW_MIB_ifRxLongPktErrPkt,
1187 HW_MIB_ifTXSQEErrors,
1188 HW_MIB_ifRxNobuf,
1189 HW_MIB_ifRxSymbolErrors,
1190 HW_MIB_ifInRangeLengthErrors,
1191 HW_MIB_ifLateCollisions,
1192 HW_MIB_SIZE
1193 };
1194
1195 enum chip_type {
1196 CHIP_TYPE_VT6110 = 1,
1197 };
1198
1199 struct velocity_info_tbl {
1200 enum chip_type chip_id;
1201 char *name;
1202 int io_size;
1203 int txqueue;
1204 u32 flags;
1205 };
1206
1207 struct velocity_info_tbl *info;
1208
1209 #define mac_hw_mibs_init(regs) {\
1210 BYTE_REG_BITS_ON(MIBCR_MIBFRZ,&((regs)->MIBCR));\
1211 BYTE_REG_BITS_ON(MIBCR_MIBCLR,&((regs)->MIBCR));\
1212 do {}\
1213 while (BYTE_REG_BITS_IS_ON(MIBCR_MIBCLR,&((regs)->MIBCR)));\
1214 BYTE_REG_BITS_OFF(MIBCR_MIBFRZ,&((regs)->MIBCR));\
1215 }
1216
1217 #define mac_read_isr(regs) readl(&((regs)->ISR))
1218 #define mac_write_isr(regs, x) writel((x),&((regs)->ISR))
1219 #define mac_clear_isr(regs) writel(0xffffffffL,&((regs)->ISR))
1220
1221 #define mac_write_int_mask(mask, regs) writel((mask),&((regs)->IMR));
1222 #define mac_disable_int(regs) writel(CR0_GINTMSK1,&((regs)->CR0Clr))
1223 #define mac_enable_int(regs) writel(CR0_GINTMSK1,&((regs)->CR0Set))
1224
1225 #define mac_hw_mibs_read(regs, MIBs) {\
1226 int i;\
1227 BYTE_REG_BITS_ON(MIBCR_MPTRINI,&((regs)->MIBCR));\
1228 for (i=0;i<HW_MIB_SIZE;i++) {\
1229 (MIBs)[i]=readl(&((regs)->MIBData));\
1230 }\
1231 }
1232
1233 #define mac_set_dma_length(regs, n) {\
1234 BYTE_REG_BITS_SET((n),0x07,&((regs)->DCFG));\
1235 }
1236
1237 #define mac_set_rx_thresh(regs, n) {\
1238 BYTE_REG_BITS_SET((n),(MCFG_RFT0|MCFG_RFT1),&((regs)->MCFG));\
1239 }
1240
1241 #define mac_rx_queue_run(regs) {\
1242 writeb(TRDCSR_RUN, &((regs)->RDCSRSet));\
1243 }
1244
1245 #define mac_rx_queue_wake(regs) {\
1246 writeb(TRDCSR_WAK, &((regs)->RDCSRSet));\
1247 }
1248
1249 #define mac_tx_queue_run(regs, n) {\
1250 writew(TRDCSR_RUN<<((n)*4),&((regs)->TDCSRSet));\
1251 }
1252
1253 #define mac_tx_queue_wake(regs, n) {\
1254 writew(TRDCSR_WAK<<(n*4),&((regs)->TDCSRSet));\
1255 }
1256
1257 #define mac_eeprom_reload(regs) {\
1258 int i=0;\
1259 BYTE_REG_BITS_ON(EECSR_RELOAD,&((regs)->EECSR));\
1260 do {\
1261 udelay(10);\
1262 if (i++>0x1000) {\
1263 break;\
1264 }\
1265 }while (BYTE_REG_BITS_IS_ON(EECSR_RELOAD,&((regs)->EECSR)));\
1266 }
1267
1268 enum velocity_cam_type {
1269 VELOCITY_VLAN_ID_CAM = 0,
1270 VELOCITY_MULTICAST_CAM
1271 };
1272
1273 /**
1274 * mac_get_cam_mask - Read a CAM mask
1275 * @regs: register block for this velocity
1276 * @mask: buffer to store mask
1277 * @cam_type: CAM to fetch
1278 *
1279 * Fetch the mask bits of the selected CAM and store them into the
1280 * provided mask buffer.
1281 */
1282
1283 static inline void mac_get_cam_mask(struct mac_regs *regs, u8 * mask,
1284 enum velocity_cam_type cam_type)
1285 {
1286 int i;
1287 /* Select CAM mask */
1288 BYTE_REG_BITS_SET(CAMCR_PS_CAM_MASK, CAMCR_PS1 | CAMCR_PS0,
1289 &regs->CAMCR);
1290
1291 if (cam_type == VELOCITY_VLAN_ID_CAM)
1292 writeb(CAMADDR_VCAMSL, &regs->CAMADDR);
1293 else
1294 writeb(0, &regs->CAMADDR);
1295
1296 /* read mask */
1297 for (i = 0; i < 8; i++)
1298 *mask++ = readb(&(regs->MARCAM[i]));
1299
1300 /* disable CAMEN */
1301 writeb(0, &regs->CAMADDR);
1302
1303 /* Select mar */
1304 BYTE_REG_BITS_SET(CAMCR_PS_MAR, CAMCR_PS1 | CAMCR_PS0,
1305 &regs->CAMCR);
1306
1307 }
1308
1309 /**
1310 * mac_set_cam_mask - Set a CAM mask
1311 * @regs: register block for this velocity
1312 * @mask: CAM mask to load
1313 * @cam_type: CAM to store
1314 *
1315 * Store a new mask into a CAM
1316 */
1317
1318 static inline void mac_set_cam_mask(struct mac_regs *regs, u8 * mask,
1319 enum velocity_cam_type cam_type)
1320 {
1321 int i;
1322 /* Select CAM mask */
1323 BYTE_REG_BITS_SET(CAMCR_PS_CAM_MASK, CAMCR_PS1 | CAMCR_PS0,
1324 &regs->CAMCR);
1325
1326 if (cam_type == VELOCITY_VLAN_ID_CAM)
1327 writeb(CAMADDR_CAMEN | CAMADDR_VCAMSL, &regs->CAMADDR);
1328 else
1329 writeb(CAMADDR_CAMEN, &regs->CAMADDR);
1330
1331 for (i = 0; i < 8; i++) {
1332 writeb(*mask++, &(regs->MARCAM[i]));
1333 }
1334 /* disable CAMEN */
1335 writeb(0, &regs->CAMADDR);
1336
1337 /* Select mar */
1338 BYTE_REG_BITS_SET(CAMCR_PS_MAR, CAMCR_PS1 | CAMCR_PS0,
1339 &regs->CAMCR);
1340 }
1341
1342 /**
1343 * mac_set_cam - set CAM data
1344 * @regs: register block of this velocity
1345 * @idx: Cam index
1346 * @addr: 2 or 6 bytes of CAM data
1347 * @cam_type: CAM to load
1348 *
1349 * Load an address or vlan tag into a CAM
1350 */
1351
1352 static inline void mac_set_cam(struct mac_regs *regs, int idx, u8 * addr,
1353 enum velocity_cam_type cam_type)
1354 {
1355 int i;
1356
1357 /* Select CAM mask */
1358 BYTE_REG_BITS_SET(CAMCR_PS_CAM_DATA, CAMCR_PS1 | CAMCR_PS0,
1359 &regs->CAMCR);
1360
1361 idx &= (64 - 1);
1362
1363 if (cam_type == VELOCITY_VLAN_ID_CAM)
1364 writeb(CAMADDR_CAMEN | CAMADDR_VCAMSL | idx,
1365 &regs->CAMADDR);
1366 else
1367 writeb(CAMADDR_CAMEN | idx, &regs->CAMADDR);
1368
1369 if (cam_type == VELOCITY_VLAN_ID_CAM)
1370 writew(*((u16 *) addr), &regs->MARCAM[0]);
1371 else {
1372 for (i = 0; i < 6; i++) {
1373 writeb(*addr++, &(regs->MARCAM[i]));
1374 }
1375 }
1376 BYTE_REG_BITS_ON(CAMCR_CAMWR, &regs->CAMCR);
1377
1378 udelay(10);
1379
1380 writeb(0, &regs->CAMADDR);
1381
1382 /* Select mar */
1383 BYTE_REG_BITS_SET(CAMCR_PS_MAR, CAMCR_PS1 | CAMCR_PS0,
1384 &regs->CAMCR);
1385 }
1386
1387 /**
1388 * mac_get_cam - fetch CAM data
1389 * @regs: register block of this velocity
1390 * @idx: Cam index
1391 * @addr: buffer to hold up to 6 bytes of CAM data
1392 * @cam_type: CAM to load
1393 *
1394 * Load an address or vlan tag from a CAM into the buffer provided by
1395 * the caller. VLAN tags are 2 bytes the address cam entries are 6.
1396 */
1397
1398 static inline void mac_get_cam(struct mac_regs *regs, int idx, u8 * addr,
1399 enum velocity_cam_type cam_type)
1400 {
1401 int i;
1402
1403 /* Select CAM mask */
1404 BYTE_REG_BITS_SET(CAMCR_PS_CAM_DATA, CAMCR_PS1 | CAMCR_PS0,
1405 &regs->CAMCR);
1406
1407 idx &= (64 - 1);
1408
1409 if (cam_type == VELOCITY_VLAN_ID_CAM)
1410 writeb(CAMADDR_CAMEN | CAMADDR_VCAMSL | idx,
1411 &regs->CAMADDR);
1412 else
1413 writeb(CAMADDR_CAMEN | idx, &regs->CAMADDR);
1414
1415 BYTE_REG_BITS_ON(CAMCR_CAMRD, &regs->CAMCR);
1416
1417 udelay(10);
1418
1419 if (cam_type == VELOCITY_VLAN_ID_CAM)
1420 *((u16 *) addr) = readw(&(regs->MARCAM[0]));
1421 else
1422 for (i = 0; i < 6; i++, addr++)
1423 *((u8 *) addr) = readb(&(regs->MARCAM[i]));
1424
1425 writeb(0, &regs->CAMADDR);
1426
1427 /* Select mar */
1428 BYTE_REG_BITS_SET(CAMCR_PS_MAR, CAMCR_PS1 | CAMCR_PS0,
1429 &regs->CAMCR);
1430 }
1431
1432 /**
1433 * mac_wol_reset - reset WOL after exiting low power
1434 * @regs: register block of this velocity
1435 *
1436 * Called after we drop out of wake on lan mode in order to
1437 * reset the Wake on lan features. This function doesn't restore
1438 * the rest of the logic from the result of sleep/wakeup
1439 */
1440
1441 inline static void mac_wol_reset(struct mac_regs *regs)
1442 {
1443
1444 /* Turn off SWPTAG right after leaving power mode */
1445 BYTE_REG_BITS_OFF(STICKHW_SWPTAG, &regs->STICKHW);
1446 /* clear sticky bits */
1447 BYTE_REG_BITS_OFF((STICKHW_DS1 | STICKHW_DS0), &regs->STICKHW);
1448
1449 BYTE_REG_BITS_OFF(CHIPGCR_FCGMII, &regs->CHIPGCR);
1450 BYTE_REG_BITS_OFF(CHIPGCR_FCMODE, &regs->CHIPGCR);
1451 /* disable force PME-enable */
1452 writeb(WOLCFG_PMEOVR, &regs->WOLCFGClr);
1453 /* disable power-event config bit */
1454 writew(0xFFFF, &regs->WOLCRClr);
1455 /* clear power status */
1456 writew(0xFFFF, &regs->WOLSRClr);
1457 }
1458
1459
1460 /*
1461 * Header for WOL definitions. Used to compute hashes
1462 */
1463
1464 typedef u8 MCAM_ADDR[ETH_ALEN];
1465
1466 struct arp_packet {
1467 u8 dest_mac[ETH_ALEN];
1468 u8 src_mac[ETH_ALEN];
1469 u16 type;
1470 u16 ar_hrd;
1471 u16 ar_pro;
1472 u8 ar_hln;
1473 u8 ar_pln;
1474 u16 ar_op;
1475 u8 ar_sha[ETH_ALEN];
1476 u8 ar_sip[4];
1477 u8 ar_tha[ETH_ALEN];
1478 u8 ar_tip[4];
1479 } __attribute__ ((__packed__));
1480
1481 struct _magic_packet {
1482 u8 dest_mac[6];
1483 u8 src_mac[6];
1484 u16 type;
1485 u8 MAC[16][6];
1486 u8 password[6];
1487 } __attribute__ ((__packed__));
1488
1489 /*
1490 * Store for chip context when saving and restoring status. Not
1491 * all fields are saved/restored currently.
1492 */
1493
1494 struct velocity_context {
1495 u8 mac_reg[256];
1496 MCAM_ADDR cam_addr[MCAM_SIZE];
1497 u16 vcam[VCAM_SIZE];
1498 u32 cammask[2];
1499 u32 patcrc[2];
1500 u32 pattern[8];
1501 };
1502
1503
1504 /*
1505 * MII registers.
1506 */
1507
1508
1509 /*
1510 * Registers in the MII (offset unit is WORD)
1511 */
1512
1513 #define MII_REG_BMCR 0x00 // physical address
1514 #define MII_REG_BMSR 0x01 //
1515 #define MII_REG_PHYID1 0x02 // OUI
1516 #define MII_REG_PHYID2 0x03 // OUI + Module ID + REV ID
1517 #define MII_REG_ANAR 0x04 //
1518 #define MII_REG_ANLPAR 0x05 //
1519 #define MII_REG_G1000CR 0x09 //
1520 #define MII_REG_G1000SR 0x0A //
1521 #define MII_REG_MODCFG 0x10 //
1522 #define MII_REG_TCSR 0x16 //
1523 #define MII_REG_PLED 0x1B //
1524 // NS, MYSON only
1525 #define MII_REG_PCR 0x17 //
1526 // ESI only
1527 #define MII_REG_PCSR 0x17 //
1528 #define MII_REG_AUXCR 0x1C //
1529
1530 // Marvell 88E1000/88E1000S
1531 #define MII_REG_PSCR 0x10 // PHY specific control register
1532
1533 //
1534 // Bits in the BMCR register
1535 //
1536 #define BMCR_RESET 0x8000 //
1537 #define BMCR_LBK 0x4000 //
1538 #define BMCR_SPEED100 0x2000 //
1539 #define BMCR_AUTO 0x1000 //
1540 #define BMCR_PD 0x0800 //
1541 #define BMCR_ISO 0x0400 //
1542 #define BMCR_REAUTO 0x0200 //
1543 #define BMCR_FDX 0x0100 //
1544 #define BMCR_SPEED1G 0x0040 //
1545 //
1546 // Bits in the BMSR register
1547 //
1548 #define BMSR_AUTOCM 0x0020 //
1549 #define BMSR_LNK 0x0004 //
1550
1551 //
1552 // Bits in the ANAR register
1553 //
1554 #define ANAR_ASMDIR 0x0800 // Asymmetric PAUSE support
1555 #define ANAR_PAUSE 0x0400 // Symmetric PAUSE Support
1556 #define ANAR_T4 0x0200 //
1557 #define ANAR_TXFD 0x0100 //
1558 #define ANAR_TX 0x0080 //
1559 #define ANAR_10FD 0x0040 //
1560 #define ANAR_10 0x0020 //
1561 //
1562 // Bits in the ANLPAR register
1563 //
1564 #define ANLPAR_ASMDIR 0x0800 // Asymmetric PAUSE support
1565 #define ANLPAR_PAUSE 0x0400 // Symmetric PAUSE Support
1566 #define ANLPAR_T4 0x0200 //
1567 #define ANLPAR_TXFD 0x0100 //
1568 #define ANLPAR_TX 0x0080 //
1569 #define ANLPAR_10FD 0x0040 //
1570 #define ANLPAR_10 0x0020 //
1571
1572 //
1573 // Bits in the G1000CR register
1574 //
1575 #define G1000CR_1000FD 0x0200 // PHY is 1000-T Full-duplex capable
1576 #define G1000CR_1000 0x0100 // PHY is 1000-T Half-duplex capable
1577
1578 //
1579 // Bits in the G1000SR register
1580 //
1581 #define G1000SR_1000FD 0x0800 // LP PHY is 1000-T Full-duplex capable
1582 #define G1000SR_1000 0x0400 // LP PHY is 1000-T Half-duplex capable
1583
1584 #define TCSR_ECHODIS 0x2000 //
1585 #define AUXCR_MDPPS 0x0004 //
1586
1587 // Bits in the PLED register
1588 #define PLED_LALBE 0x0004 //
1589
1590 // Marvell 88E1000/88E1000S Bits in the PHY specific control register (10h)
1591 #define PSCR_ACRSTX 0x0800 // Assert CRS on Transmit
1592
1593 #define PHYID_CICADA_CS8201 0x000FC410UL
1594 #define PHYID_VT3216_32BIT 0x000FC610UL
1595 #define PHYID_VT3216_64BIT 0x000FC600UL
1596 #define PHYID_MARVELL_1000 0x01410C50UL
1597 #define PHYID_MARVELL_1000S 0x01410C40UL
1598
1599 #define PHYID_REV_ID_MASK 0x0000000FUL
1600
1601 #define PHYID_GET_PHY_REV_ID(i) ((i) & PHYID_REV_ID_MASK)
1602 #define PHYID_GET_PHY_ID(i) ((i) & ~PHYID_REV_ID_MASK)
1603
1604 #define MII_REG_BITS_ON(x,i,p) do {\
1605 u16 w;\
1606 velocity_mii_read((p),(i),&(w));\
1607 (w)|=(x);\
1608 velocity_mii_write((p),(i),(w));\
1609 } while (0)
1610
1611 #define MII_REG_BITS_OFF(x,i,p) do {\
1612 u16 w;\
1613 velocity_mii_read((p),(i),&(w));\
1614 (w)&=(~(x));\
1615 velocity_mii_write((p),(i),(w));\
1616 } while (0)
1617
1618 #define MII_REG_BITS_IS_ON(x,i,p) ({\
1619 u16 w;\
1620 velocity_mii_read((p),(i),&(w));\
1621 ((int) ((w) & (x)));})
1622
1623 #define MII_GET_PHY_ID(p) ({\
1624 u32 id; \
1625 u16 id2; \
1626 u16 id1; \
1627 velocity_mii_read((p),MII_REG_PHYID2, &id2);\
1628 velocity_mii_read((p),MII_REG_PHYID1, &id1);\
1629 id = ( ( (u32)id2 ) << 16 ) | id1; \
1630 (id);})
1631
1632 #ifdef LINUX
1633 /*
1634 * Inline debug routine
1635 */
1636
1637
1638 enum velocity_msg_level {
1639 MSG_LEVEL_ERR = 0, //Errors that will cause abnormal operation.
1640 MSG_LEVEL_NOTICE = 1, //Some errors need users to be notified.
1641 MSG_LEVEL_INFO = 2, //Normal message.
1642 MSG_LEVEL_VERBOSE = 3, //Will report all trival errors.
1643 MSG_LEVEL_DEBUG = 4 //Only for debug purpose.
1644 };
1645
1646 #ifdef VELOCITY_DEBUG
1647 #define ASSERT(x) { \
1648 if (!(x)) { \
1649 printk(KERN_ERR "assertion %s failed: file %s line %d\n", #x,\
1650 __FUNCTION__, __LINE__);\
1651 BUG(); \
1652 }\
1653 }
1654 #define VELOCITY_DBG(p,args...) printk(p, ##args)
1655 #else
1656 #define ASSERT(x)
1657 #define VELOCITY_DBG(x)
1658 #endif
1659
1660 #define VELOCITY_PRT(l, p, args...) do {if (l<=msglevel) printf( p ,##args);} while (0)
1661
1662 #define VELOCITY_PRT_CAMMASK(p,t) {\
1663 int i;\
1664 if ((t)==VELOCITY_MULTICAST_CAM) {\
1665 for (i=0;i<(MCAM_SIZE/8);i++)\
1666 printk("%02X",(p)->mCAMmask[i]);\
1667 }\
1668 else {\
1669 for (i=0;i<(VCAM_SIZE/8);i++)\
1670 printk("%02X",(p)->vCAMmask[i]);\
1671 }\
1672 printk("\n");\
1673 }
1674
1675 #endif
1676
1677 #define VELOCITY_WOL_MAGIC 0x00000000UL
1678 #define VELOCITY_WOL_PHY 0x00000001UL
1679 #define VELOCITY_WOL_ARP 0x00000002UL
1680 #define VELOCITY_WOL_UCAST 0x00000004UL
1681 #define VELOCITY_WOL_BCAST 0x00000010UL
1682 #define VELOCITY_WOL_MCAST 0x00000020UL
1683 #define VELOCITY_WOL_MAGIC_SEC 0x00000040UL
1684
1685 /*
1686 * Flags for options
1687 */
1688
1689 #define VELOCITY_FLAGS_TAGGING 0x00000001UL
1690 #define VELOCITY_FLAGS_TX_CSUM 0x00000002UL
1691 #define VELOCITY_FLAGS_RX_CSUM 0x00000004UL
1692 #define VELOCITY_FLAGS_IP_ALIGN 0x00000008UL
1693 #define VELOCITY_FLAGS_VAL_PKT_LEN 0x00000010UL
1694
1695 #define VELOCITY_FLAGS_FLOW_CTRL 0x01000000UL
1696
1697 /*
1698 * Flags for driver status
1699 */
1700
1701 #define VELOCITY_FLAGS_OPENED 0x00010000UL
1702 #define VELOCITY_FLAGS_VMNS_CONNECTED 0x00020000UL
1703 #define VELOCITY_FLAGS_VMNS_COMMITTED 0x00040000UL
1704 #define VELOCITY_FLAGS_WOL_ENABLED 0x00080000UL
1705
1706 /*
1707 * Flags for MII status
1708 */
1709
1710 #define VELOCITY_LINK_FAIL 0x00000001UL
1711 #define VELOCITY_SPEED_10 0x00000002UL
1712 #define VELOCITY_SPEED_100 0x00000004UL
1713 #define VELOCITY_SPEED_1000 0x00000008UL
1714 #define VELOCITY_DUPLEX_FULL 0x00000010UL
1715 #define VELOCITY_AUTONEG_ENABLE 0x00000020UL
1716 #define VELOCITY_FORCED_BY_EEPROM 0x00000040UL
1717
1718 /*
1719 * For velocity_set_media_duplex
1720 */
1721
1722 #define VELOCITY_LINK_CHANGE 0x00000001UL
1723
1724 enum speed_opt {
1725 SPD_DPX_AUTO = 0,
1726 SPD_DPX_100_HALF = 1,
1727 SPD_DPX_100_FULL = 2,
1728 SPD_DPX_10_HALF = 3,
1729 SPD_DPX_10_FULL = 4
1730 };
1731
1732 enum velocity_init_type {
1733 VELOCITY_INIT_COLD = 0,
1734 VELOCITY_INIT_RESET,
1735 VELOCITY_INIT_WOL
1736 };
1737
1738 enum velocity_flow_cntl_type {
1739 FLOW_CNTL_DEFAULT = 1,
1740 FLOW_CNTL_TX,
1741 FLOW_CNTL_RX,
1742 FLOW_CNTL_TX_RX,
1743 FLOW_CNTL_DISABLE,
1744 };
1745
1746 struct velocity_opt {
1747 int numrx; /* Number of RX descriptors */
1748 int numtx; /* Number of TX descriptors */
1749 enum speed_opt spd_dpx; /* Media link mode */
1750 int vid; /* vlan id */
1751 int DMA_length; /* DMA length */
1752 int rx_thresh; /* RX_THRESH */
1753 int flow_cntl;
1754 int wol_opts; /* Wake on lan options */
1755 int td_int_count;
1756 int int_works;
1757 int rx_bandwidth_hi;
1758 int rx_bandwidth_lo;
1759 int rx_bandwidth_en;
1760 u32 flags;
1761 };
1762
1763 #define RX_DESC_MIN 4
1764 #define RX_DESC_MAX 255
1765 #define RX_DESC_DEF RX_DESC_MIN
1766
1767 #define TX_DESC_MIN 1
1768 #define TX_DESC_MAX 256
1769 #define TX_DESC_DEF TX_DESC_MIN
1770
1771 struct velocity_info {
1772 // struct list_head list;
1773
1774 struct pci_device *pdev;
1775 // struct net_device *dev;
1776 // struct net_device_stats stats;
1777
1778 #ifdef CONFIG_PM
1779 u32 pci_state[16];
1780 #endif
1781
1782 // dma_addr_t rd_pool_dma;
1783 // dma_addr_t td_pool_dma[TX_QUEUE_NO];
1784
1785 // dma_addr_t tx_bufs_dma;
1786 u8 *tx_bufs;
1787
1788 u8 ip_addr[4];
1789 enum chip_type chip_id;
1790
1791 struct mac_regs *mac_regs;
1792 unsigned long memaddr;
1793 unsigned long ioaddr;
1794 u32 io_size;
1795
1796 u8 rev_id;
1797
1798 #define AVAIL_TD(p,q) ((p)->options.numtx-((p)->td_used[(q)]))
1799
1800 int num_txq;
1801
1802 volatile int td_used[TX_QUEUE_NO];
1803 int td_curr;
1804 int td_tail[TX_QUEUE_NO];
1805 unsigned char *TxDescArrays; /* Index of Tx Descriptor buffer */
1806 unsigned char *RxDescArrays; /* Index of Rx Descriptor buffer */
1807 unsigned char *tx_buffs;
1808 unsigned char *rx_buffs;
1809
1810 unsigned char *txb;
1811 unsigned char *rxb;
1812 struct tx_desc *td_rings;
1813 struct velocity_td_info *td_infos[TX_QUEUE_NO];
1814
1815 int rd_curr;
1816 int rd_dirty;
1817 u32 rd_filled;
1818 struct rx_desc *rd_ring;
1819 struct velocity_rd_info *rd_info; /* It's an array */
1820
1821 #define GET_RD_BY_IDX(vptr, idx) (vptr->rd_ring[idx])
1822 u32 mib_counter[MAX_HW_MIB_COUNTER];
1823 struct velocity_opt options;
1824
1825 u32 int_mask;
1826
1827 u32 flags;
1828
1829 int rx_buf_sz;
1830 u32 mii_status;
1831 u32 phy_id;
1832 int multicast_limit;
1833
1834 u8 vCAMmask[(VCAM_SIZE / 8)];
1835 u8 mCAMmask[(MCAM_SIZE / 8)];
1836
1837 // spinlock_t lock;
1838
1839 int wol_opts;
1840 u8 wol_passwd[6];
1841
1842 struct velocity_context context;
1843
1844 u32 ticks;
1845 u32 rx_bytes;
1846
1847 } vptx;
1848
1849 static struct velocity_info *vptr;
1850
1851 #ifdef LINUX
1852 /**
1853 * velocity_get_ip - find an IP address for the device
1854 * @vptr: Velocity to query
1855 *
1856 * Dig out an IP address for this interface so that we can
1857 * configure wakeup with WOL for ARP. If there are multiple IP
1858 * addresses on this chain then we use the first - multi-IP WOL is not
1859 * supported.
1860 *
1861 * CHECK ME: locking
1862 */
1863
1864 inline static int velocity_get_ip(struct velocity_info *vptr)
1865 {
1866 struct in_device *in_dev = (struct in_device *) vptr->dev->ip_ptr;
1867 struct in_ifaddr *ifa;
1868
1869 if (in_dev != NULL) {
1870 ifa = (struct in_ifaddr *) in_dev->ifa_list;
1871 if (ifa != NULL) {
1872 memcpy(vptr->ip_addr, &ifa->ifa_address, 4);
1873 return 0;
1874 }
1875 }
1876 return -ENOENT;
1877 }
1878
1879 /**
1880 * velocity_update_hw_mibs - fetch MIB counters from chip
1881 * @vptr: velocity to update
1882 *
1883 * The velocity hardware keeps certain counters in the hardware
1884 * side. We need to read these when the user asks for statistics
1885 * or when they overflow (causing an interrupt). The read of the
1886 * statistic clears it, so we keep running master counters in user
1887 * space.
1888 */
1889
1890 static inline void velocity_update_hw_mibs(struct velocity_info *vptr)
1891 {
1892 u32 tmp;
1893 int i;
1894 BYTE_REG_BITS_ON(MIBCR_MIBFLSH, &(vptr->mac_regs->MIBCR));
1895
1896 while (BYTE_REG_BITS_IS_ON
1897 (MIBCR_MIBFLSH, &(vptr->mac_regs->MIBCR)));
1898
1899 BYTE_REG_BITS_ON(MIBCR_MPTRINI, &(vptr->mac_regs->MIBCR));
1900 for (i = 0; i < HW_MIB_SIZE; i++) {
1901 tmp = readl(&(vptr->mac_regs->MIBData)) & 0x00FFFFFFUL;
1902 vptr->mib_counter[i] += tmp;
1903 }
1904 }
1905 #endif
1906 /**
1907 * init_flow_control_register - set up flow control
1908 * @vptr: velocity to configure
1909 *
1910 * Configure the flow control registers for this velocity device.
1911 */
1912
1913 static inline void init_flow_control_register(struct velocity_info *vptr)
1914 {
1915 struct mac_regs *regs = vptr->mac_regs;
1916
1917 /* Set {XHITH1, XHITH0, XLTH1, XLTH0} in FlowCR1 to {1, 0, 1, 1}
1918 depend on RD=64, and Turn on XNOEN in FlowCR1 */
1919 writel((CR0_XONEN | CR0_XHITH1 | CR0_XLTH1 | CR0_XLTH0),
1920 &regs->CR0Set);
1921 writel((CR0_FDXTFCEN | CR0_FDXRFCEN | CR0_HDXFCEN | CR0_XHITH0),
1922 &regs->CR0Clr);
1923
1924 /* Set TxPauseTimer to 0xFFFF */
1925 writew(0xFFFF, &regs->tx_pause_timer);
1926
1927 /* Initialize RBRDU to Rx buffer count. */
1928 writew(vptr->options.numrx, &regs->RBRDU);
1929 }
1930
1931
1932 #endif
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