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[e1000] Use PCI_BASE_ADDRESS_* symbols instead of integers
[gpxe.git] / src / drivers / net / e1000 / e1000.c
blobc1a4a52d8c938e96f1e2e0e874eec8e09d9ff394
1 /*
2 * gPXE driver for Intel eepro1000 ethernet cards
3 *
4 * Written by Marty Connor
5 *
6 * Copyright Entity Cyber, Inc. 2007
7 *
8 * This software may be used and distributed according to the terms of
9 * the GNU General Public License (GPL), incorporated herein by
10 * reference. Drivers based on or derived from this code fall under
11 * the GPL and must retain the authorship, copyright and license
12 * notice.
13 *
14 */
15
16 /*******************************************************************************
17
18 Intel PRO/1000 Linux driver
19 Copyright(c) 1999 - 2006 Intel Corporation.
20
21 This program is free software; you can redistribute it and/or modify it
22 under the terms and conditions of the GNU General Public License,
23 version 2, as published by the Free Software Foundation.
24
25 This program is distributed in the hope it will be useful, but WITHOUT
26 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
27 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
28 more details.
29
30 You should have received a copy of the GNU General Public License along with
31 this program; if not, write to the Free Software Foundation, Inc.,
32 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
33
34 The full GNU General Public License is included in this distribution in
35 the file called "COPYING".
36
37 Contact Information:
38 Linux NICS <linux.nics@intel.com>
39 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
40 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
41
42 *******************************************************************************/
43
44 #include "e1000.h"
45
46 /**
47 * e1000_get_hw_control - get control of the h/w from f/w
48 *
49 * @v adapter e1000 private structure
50 *
51 * e1000_get_hw_control sets {CTRL_EXT|FWSM}:DRV_LOAD bit.
52 * For ASF and Pass Through versions of f/w this means that
53 * the driver is loaded. For AMT version (only with 82573)
54 * of the f/w this means that the network i/f is open.
55 *
56 **/
57 static void
58 e1000_get_hw_control ( struct e1000_adapter *adapter )
59 {
60 uint32_t ctrl_ext;
61 uint32_t swsm;
62
63 DBG ( "e1000_get_hw_control\n" );
64
65 /* Let firmware know the driver has taken over */
66 switch (adapter->hw.mac_type) {
67 case e1000_82573:
68 swsm = E1000_READ_REG(&adapter->hw, SWSM);
69 E1000_WRITE_REG(&adapter->hw, SWSM,
70 swsm | E1000_SWSM_DRV_LOAD);
71 break;
72 case e1000_82571:
73 case e1000_82572:
74 case e1000_80003es2lan:
75 case e1000_ich8lan:
76 ctrl_ext = E1000_READ_REG(&adapter->hw, CTRL_EXT);
77 E1000_WRITE_REG(&adapter->hw, CTRL_EXT,
78 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
79 break;
80 default:
81 break;
82 }
83 }
84
85 /**
86 * e1000_irq_enable - Enable default interrupt generation settings
87 *
88 * @v adapter e1000 private structure
89 **/
90 static void
91 e1000_irq_enable ( struct e1000_adapter *adapter )
92 {
93 E1000_WRITE_REG ( &adapter->hw, IMS, E1000_IMS_RXDMT0 |
94 E1000_IMS_RXSEQ );
95 E1000_WRITE_FLUSH ( &adapter->hw );
96 }
97
98 /**
99 * e1000_irq_disable - Mask off interrupt generation on the NIC
100 *
101 * @v adapter e1000 private structure
102 **/
103 static void
104 e1000_irq_disable ( struct e1000_adapter *adapter )
105 {
106 E1000_WRITE_REG ( &adapter->hw, IMC, ~0 );
107 E1000_WRITE_FLUSH ( &adapter->hw );
108 }
109
110 /**
111 * e1000_irq_force - trigger interrupt
112 *
113 * @v adapter e1000 private structure
114 **/
115 static void
116 e1000_irq_force ( struct e1000_adapter *adapter )
117 {
118 E1000_WRITE_REG ( &adapter->hw, ICS, E1000_ICS_RXDMT0 );
119 E1000_WRITE_FLUSH ( &adapter->hw );
120 }
121
122 /**
123 * e1000_sw_init - Initialize general software structures (struct e1000_adapter)
124 *
125 * @v adapter e1000 private structure
126 *
127 * e1000_sw_init initializes the Adapter private data structure.
128 * Fields are initialized based on PCI device information and
129 * OS network device settings (MTU size).
130 **/
131 static int
132 e1000_sw_init ( struct e1000_adapter *adapter )
133 {
134 struct e1000_hw *hw = &adapter->hw;
135 struct pci_device *pdev = adapter->pdev;
136
137 /* PCI config space info */
138
139 hw->vendor_id = pdev->vendor;
140 hw->device_id = pdev->device;
141
142 pci_read_config_word ( pdev, PCI_COMMAND, &hw->pci_cmd_word );
143
144 /* Disable Flow Control */
145 hw->fc = E1000_FC_NONE;
146
147 adapter->eeprom_wol = 0;
148 adapter->wol = adapter->eeprom_wol;
149 adapter->en_mng_pt = 0;
150 adapter->rx_int_delay = 0;
151 adapter->rx_abs_int_delay = 0;
152
153 adapter->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE;
154 adapter->rx_ps_bsize0 = E1000_RXBUFFER_128;
155 hw->max_frame_size = MAXIMUM_ETHERNET_VLAN_SIZE +
156 ENET_HEADER_SIZE + ETHERNET_FCS_SIZE;
157 hw->min_frame_size = MINIMUM_ETHERNET_FRAME_SIZE;
158
159 /* identify the MAC */
160
161 if ( e1000_set_mac_type ( hw ) ) {
162 DBG ( "Unknown MAC Type\n" );
163 return -EIO;
164 }
165
166 switch ( hw->mac_type ) {
167 default:
168 break;
169 case e1000_82541:
170 case e1000_82547:
171 case e1000_82541_rev_2:
172 case e1000_82547_rev_2:
173 hw->phy_init_script = 1;
174 break;
175 }
176
177 e1000_set_media_type ( hw );
178
179 hw->autoneg = TRUE;
180 hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT;
181 hw->wait_autoneg_complete = TRUE;
182
183 hw->tbi_compatibility_en = TRUE;
184 hw->adaptive_ifs = TRUE;
185
186 /* Copper options */
187
188 if ( hw->media_type == e1000_media_type_copper ) {
189 hw->mdix = AUTO_ALL_MODES;
190 hw->disable_polarity_correction = FALSE;
191 hw->master_slave = E1000_MASTER_SLAVE;
192 }
193
194 e1000_irq_disable ( adapter );
195
196 return 0;
197 }
198
199 /**
200 * e1000_setup_tx_resources - allocate Tx resources (Descriptors)
201 *
202 * @v adapter e1000 private structure
203 *
204 * @ret rc Returns 0 on success, negative on failure
205 **/
206 static int
207 e1000_setup_tx_resources ( struct e1000_adapter *adapter )
208 {
209 DBG ( "e1000_setup_tx_resources\n" );
210
211 /* Allocate transmit descriptor ring memory.
212 It must not cross a 64K boundary because of hardware errata #23
213 so we use malloc_dma() requesting a 128 byte block that is
214 128 byte aligned. This should guarantee that the memory
215 allocated will not cross a 64K boundary, because 128 is an
216 even multiple of 65536 ( 65536 / 128 == 512 ), so all possible
217 allocations of 128 bytes on a 128 byte boundary will not
218 cross 64K bytes.
219 */
220
221 adapter->tx_base =
222 malloc_dma ( adapter->tx_ring_size, adapter->tx_ring_size );
223
224 if ( ! adapter->tx_base ) {
225 return -ENOMEM;
226 }
227
228 memset ( adapter->tx_base, 0, adapter->tx_ring_size );
229
230 DBG ( "adapter->tx_base = %#08lx\n", virt_to_bus ( adapter->tx_base ) );
231
232 return 0;
233 }
234
235 static void
236 e1000_free_tx_resources ( struct e1000_adapter *adapter )
237 {
238 DBG ( "e1000_free_tx_resources\n" );
239
240 free_dma ( adapter->tx_base, adapter->tx_ring_size );
241 }
242
243 /**
244 * e1000_configure_tx - Configure 8254x Transmit Unit after Reset
245 * @adapter: board private structure
246 *
247 * Configure the Tx unit of the MAC after a reset.
248 **/
249 static void
250 e1000_configure_tx ( struct e1000_adapter *adapter )
251 {
252 struct e1000_hw *hw = &adapter->hw;
253 uint32_t tctl;
254
255 DBG ( "e1000_configure_tx\n" );
256
257 E1000_WRITE_REG ( hw, TDBAH, 0 );
258 E1000_WRITE_REG ( hw, TDBAL, virt_to_bus ( adapter->tx_base ) );
259 E1000_WRITE_REG ( hw, TDLEN, adapter->tx_ring_size );
260
261 DBG ( "TDBAL: %#08x\n", E1000_READ_REG ( hw, TDBAL ) );
262 DBG ( "TDLEN: %d\n", E1000_READ_REG ( hw, TDLEN ) );
263
264 /* Setup the HW Tx Head and Tail descriptor pointers */
265 E1000_WRITE_REG ( hw, TDH, 0 );
266 E1000_WRITE_REG ( hw, TDT, 0 );
267
268 adapter->tx_head = 0;
269 adapter->tx_tail = 0;
270 adapter->tx_fill_ctr = 0;
271
272 /* Setup Transmit Descriptor Settings for eop descriptor */
273 tctl = E1000_TCTL_PSP | E1000_TCTL_EN |
274 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT) |
275 (E1000_HDX_COLLISION_DISTANCE << E1000_COLD_SHIFT);
276
277 e1000_config_collision_dist ( hw );
278
279 E1000_WRITE_REG ( hw, TCTL, tctl );
280 E1000_WRITE_FLUSH ( hw );
281 }
282
283 /**
284 * e1000_setup_rx_resources - allocate Rx resources (Descriptors)
285 *
286 * @v adapter e1000 private structure
287 *
288 * @ret rc Returns 0 on success, negative on failure
289 **/
290 static int
291 e1000_setup_rx_resources ( struct e1000_adapter *adapter )
292 {
293 int i, j;
294 struct e1000_rx_desc *rx_curr_desc;
295
296 DBG ( "e1000_setup_rx_resources\n" );
297
298 /* Allocate receive descriptor ring memory.
299 It must not cross a 64K boundary because of hardware errata
300 */
301
302 adapter->rx_base =
303 malloc_dma ( adapter->rx_ring_size, adapter->rx_ring_size );
304
305 if ( ! adapter->rx_base ) {
306 return -ENOMEM;
307 }
308 memset ( adapter->rx_base, 0, adapter->rx_ring_size );
309
310 for ( i = 0; i < NUM_RX_DESC; i++ ) {
311
312 adapter->rx_iobuf[i] = alloc_iob ( MAXIMUM_ETHERNET_VLAN_SIZE );
313
314 /* If unable to allocate all iobufs, free any that
315 * were successfully allocated, and return an error
316 */
317 if ( ! adapter->rx_iobuf[i] ) {
318 for ( j = 0; j < i; j++ ) {
319 free_iob ( adapter->rx_iobuf[j] );
320 }
321 return -ENOMEM;
322 }
323
324 rx_curr_desc = ( void * ) ( adapter->rx_base ) +
325 ( i * sizeof ( *adapter->rx_base ) );
326
327 rx_curr_desc->buffer_addr = virt_to_bus ( adapter->rx_iobuf[i]->data );
328
329 DBG ( "i = %d rx_curr_desc->buffer_addr = %#16llx\n",
330 i, rx_curr_desc->buffer_addr );
331
332 }
333 return 0;
334 }
335
336 static void
337 e1000_free_rx_resources ( struct e1000_adapter *adapter )
338 {
339 int i;
340
341 DBG ( "e1000_free_rx_resources\n" );
342
343 free_dma ( adapter->rx_base, adapter->rx_ring_size );
344
345 for ( i = 0; i < NUM_RX_DESC; i++ ) {
346 free_iob ( adapter->rx_iobuf[i] );
347 }
348 }
349
350 /**
351 * e1000_configure_rx - Configure 8254x Receive Unit after Reset
352 * @adapter: board private structure
353 *
354 * Configure the Rx unit of the MAC after a reset.
355 **/
356 static void
357 e1000_configure_rx ( struct e1000_adapter *adapter )
358 {
359 struct e1000_hw *hw = &adapter->hw;
360 uint32_t rctl;
361
362 DBG ( "e1000_configure_rx\n" );
363
364 /* disable receives while setting up the descriptors */
365 rctl = E1000_READ_REG ( hw, RCTL );
366 E1000_WRITE_REG ( hw, RCTL, rctl & ~E1000_RCTL_EN );
367
368 adapter->rx_curr = 0;
369
370 /* Setup the HW Rx Head and Tail Descriptor Pointers and
371 * the Base and Length of the Rx Descriptor Ring */
372
373 E1000_WRITE_REG ( hw, RDBAL, virt_to_bus ( adapter->rx_base ) );
374 E1000_WRITE_REG ( hw, RDBAH, 0 );
375 E1000_WRITE_REG ( hw, RDLEN, adapter->rx_ring_size );
376
377 E1000_WRITE_REG ( hw, RDH, 0 );
378 E1000_WRITE_REG ( hw, RDT, NUM_RX_DESC - 1 );
379
380 /* Enable Receives */
381 rctl = ( E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_SZ_2048 |
382 E1000_RCTL_MPE
383 );
384
385 E1000_WRITE_REG ( hw, RCTL, rctl );
386 E1000_WRITE_FLUSH ( hw );
387
388 DBG ( "RDBAL: %#08x\n", E1000_READ_REG ( hw, RDBAL ) );
389 DBG ( "RDLEN: %d\n", E1000_READ_REG ( hw, RDLEN ) );
390 DBG ( "RCTL: %#08x\n", E1000_READ_REG ( hw, RCTL ) );
391 }
392
393 /**
394 * e1000_reset - Put e1000 NIC in known initial state
395 *
396 * @v adapter e1000 private structure
397 **/
398 static void
399 e1000_reset ( struct e1000_adapter *adapter )
400 {
401 uint32_t pba = 0;
402 uint16_t fc_high_water_mark = E1000_FC_HIGH_DIFF;
403
404 DBG ( "e1000_reset\n" );
405
406 switch (adapter->hw.mac_type) {
407 case e1000_82542_rev2_0:
408 case e1000_82542_rev2_1:
409 case e1000_82543:
410 case e1000_82544:
411 case e1000_82540:
412 case e1000_82541:
413 case e1000_82541_rev_2:
414 pba = E1000_PBA_48K;
415 break;
416 case e1000_82545:
417 case e1000_82545_rev_3:
418 case e1000_82546:
419 case e1000_82546_rev_3:
420 pba = E1000_PBA_48K;
421 break;
422 case e1000_82547:
423 case e1000_82547_rev_2:
424 pba = E1000_PBA_30K;
425 break;
426 case e1000_82571:
427 case e1000_82572:
428 case e1000_80003es2lan:
429 pba = E1000_PBA_38K;
430 break;
431 case e1000_82573:
432 pba = E1000_PBA_20K;
433 break;
434 case e1000_ich8lan:
435 pba = E1000_PBA_8K;
436 case e1000_undefined:
437 case e1000_num_macs:
438 break;
439 }
440
441 E1000_WRITE_REG ( &adapter->hw, PBA, pba );
442
443 /* flow control settings */
444 /* Set the FC high water mark to 90% of the FIFO size.
445 * Required to clear last 3 LSB */
446 fc_high_water_mark = ((pba * 9216)/10) & 0xFFF8;
447 /* We can't use 90% on small FIFOs because the remainder
448 * would be less than 1 full frame. In this case, we size
449 * it to allow at least a full frame above the high water
450 * mark. */
451 if (pba < E1000_PBA_16K)
452 fc_high_water_mark = (pba * 1024) - 1600;
453
454 adapter->hw.fc_high_water = fc_high_water_mark;
455 adapter->hw.fc_low_water = fc_high_water_mark - 8;
456 if (adapter->hw.mac_type == e1000_80003es2lan)
457 adapter->hw.fc_pause_time = 0xFFFF;
458 else
459 adapter->hw.fc_pause_time = E1000_FC_PAUSE_TIME;
460 adapter->hw.fc_send_xon = 1;
461 adapter->hw.fc = adapter->hw.original_fc;
462 /* Allow time for pending master requests to run */
463
464 e1000_reset_hw ( &adapter->hw );
465
466 if ( adapter->hw.mac_type >= e1000_82544 )
467 E1000_WRITE_REG ( &adapter->hw, WUC, 0 );
468
469 if ( e1000_init_hw ( &adapter->hw ) )
470 DBG ( "Hardware Error\n" );
471
472 /* if (adapter->hwflags & HWFLAGS_PHY_PWR_BIT) { */
473 if (adapter->hw.mac_type >= e1000_82544 &&
474 adapter->hw.mac_type <= e1000_82547_rev_2 &&
475 adapter->hw.autoneg == 1 &&
476 adapter->hw.autoneg_advertised == ADVERTISE_1000_FULL) {
477 uint32_t ctrl = E1000_READ_REG(&adapter->hw, CTRL);
478 /* clear phy power management bit if we are in gig only mode,
479 * which if enabled will attempt negotiation to 100Mb, which
480 * can cause a loss of link at power off or driver unload */
481 ctrl &= ~E1000_CTRL_SWDPIN3;
482 E1000_WRITE_REG(&adapter->hw, CTRL, ctrl);
483 }
484
485 e1000_phy_get_info ( &adapter->hw, &adapter->phy_info );
486
487 if (!adapter->smart_power_down &&
488 (adapter->hw.mac_type == e1000_82571 ||
489 adapter->hw.mac_type == e1000_82572)) {
490 uint16_t phy_data = 0;
491 /* speed up time to link by disabling smart power down, ignore
492 * the return value of this function because there is nothing
493 * different we would do if it failed */
494 e1000_read_phy_reg(&adapter->hw, IGP02E1000_PHY_POWER_MGMT,
495 &phy_data);
496 phy_data &= ~IGP02E1000_PM_SPD;
497 e1000_write_phy_reg(&adapter->hw, IGP02E1000_PHY_POWER_MGMT,
498 phy_data);
499 }
500 }
501
502 /** Functions that implement the gPXE driver API **/
503
504 /**
505 * e1000_close - Disables a network interface
506 *
507 * @v netdev network interface device structure
508 *
509 **/
510 static void
511 e1000_close ( struct net_device *netdev )
512 {
513 struct e1000_adapter *adapter = netdev_priv ( netdev );
514 struct e1000_hw *hw = &adapter->hw;
515 uint32_t rctl;
516 uint32_t icr;
517
518 DBG ( "e1000_close\n" );
519
520 /* Acknowledge interrupts */
521 icr = E1000_READ_REG ( hw, ICR );
522
523 e1000_irq_disable ( adapter );
524
525 /* disable receives */
526 rctl = E1000_READ_REG ( hw, RCTL );
527 E1000_WRITE_REG ( hw, RCTL, rctl & ~E1000_RCTL_EN );
528 E1000_WRITE_FLUSH ( hw );
529
530 e1000_reset_hw ( hw );
531
532 e1000_free_tx_resources ( adapter );
533 e1000_free_rx_resources ( adapter );
534 }
535
536 /**
537 * e1000_transmit - Transmit a packet
538 *
539 * @v netdev Network device
540 * @v iobuf I/O buffer
541 *
542 * @ret rc Returns 0 on success, negative on failure
543 */
544 static int
545 e1000_transmit ( struct net_device *netdev, struct io_buffer *iobuf )
546 {
547 struct e1000_adapter *adapter = netdev_priv( netdev );
548 struct e1000_hw *hw = &adapter->hw;
549 uint32_t tx_curr = adapter->tx_tail;
550 struct e1000_tx_desc *tx_curr_desc;
551
552 DBG ("e1000_transmit\n");
553
554 if ( adapter->tx_fill_ctr == NUM_TX_DESC ) {
555 DBG ("TX overflow\n");
556 return -ENOBUFS;
557 }
558
559 /* Save pointer to iobuf we have been given to transmit,
560 netdev_tx_complete() will need it later
561 */
562 adapter->tx_iobuf[tx_curr] = iobuf;
563
564 tx_curr_desc = ( void * ) ( adapter->tx_base ) +
565 ( tx_curr * sizeof ( *adapter->tx_base ) );
566
567 DBG ( "tx_curr_desc = %#08lx\n", virt_to_bus ( tx_curr_desc ) );
568 DBG ( "tx_curr_desc + 16 = %#08lx\n", virt_to_bus ( tx_curr_desc ) + 16 );
569 DBG ( "iobuf->data = %#08lx\n", virt_to_bus ( iobuf->data ) );
570
571 /* Add the packet to TX ring
572 */
573 tx_curr_desc->buffer_addr =
574 virt_to_bus ( iobuf->data );
575 tx_curr_desc->lower.data =
576 E1000_TXD_CMD_RPS | E1000_TXD_CMD_EOP |
577 E1000_TXD_CMD_IFCS | iob_len ( iobuf );
578 tx_curr_desc->upper.data = 0;
579
580 DBG ( "TX fill: %d tx_curr: %d addr: %#08lx len: %zd\n", adapter->tx_fill_ctr,
581 tx_curr, virt_to_bus ( iobuf->data ), iob_len ( iobuf ) );
582
583 /* Point to next free descriptor */
584 adapter->tx_tail = ( adapter->tx_tail + 1 ) % NUM_TX_DESC;
585 adapter->tx_fill_ctr++;
586
587 /* Write new tail to NIC, making packet available for transmit
588 */
589 E1000_WRITE_REG ( hw, TDT, adapter->tx_tail );
590
591 return 0;
592 }
593
594 /**
595 * e1000_poll - Poll for received packets
596 *
597 * @v netdev Network device
598 */
599 static void
600 e1000_poll ( struct net_device *netdev )
601 {
602 struct e1000_adapter *adapter = netdev_priv( netdev );
603 struct e1000_hw *hw = &adapter->hw;
604
605 uint32_t icr;
606 uint32_t tx_status;
607 uint32_t rx_status;
608 uint32_t rx_len;
609 uint32_t rx_err;
610 struct io_buffer *rx_iob;
611 struct e1000_tx_desc *tx_curr_desc;
612 struct e1000_rx_desc *rx_curr_desc;
613 uint32_t i;
614 uint64_t tmp_buffer_addr;
615
616 DBGP ( "e1000_poll\n" );
617
618 /* Acknowledge interrupts */
619 icr = E1000_READ_REG ( hw, ICR );
620 if ( ! icr )
621 return;
622
623 DBG ( "e1000_poll: intr_status = %#08x\n", icr );
624
625 /* Check status of transmitted packets
626 */
627 while ( ( i = adapter->tx_head ) != adapter->tx_tail ) {
628
629 tx_curr_desc = ( void * ) ( adapter->tx_base ) +
630 ( i * sizeof ( *adapter->tx_base ) );
631
632 tx_status = tx_curr_desc->upper.data;
633
634 /* if the packet at tx_head is not owned by hardware it is for us */
635 if ( ! ( tx_status & E1000_TXD_STAT_DD ) )
636 break;
637
638 DBG ( "Sent packet. tx_head: %d tx_tail: %d tx_status: %#08x\n",
639 adapter->tx_head, adapter->tx_tail, tx_status );
640
641 if ( tx_status & ( E1000_TXD_STAT_EC | E1000_TXD_STAT_LC |
642 E1000_TXD_STAT_TU ) ) {
643 netdev_tx_complete_err ( netdev, adapter->tx_iobuf[i], -EINVAL );
644 DBG ( "Error transmitting packet, tx_status: %#08x\n",
645 tx_status );
646 } else {
647 netdev_tx_complete ( netdev, adapter->tx_iobuf[i] );
648 DBG ( "Success transmitting packet, tx_status: %#08x\n",
649 tx_status );
650 }
651
652 /* Decrement count of used descriptors, clear this descriptor
653 */
654 adapter->tx_fill_ctr--;
655 memset ( tx_curr_desc, 0, sizeof ( *tx_curr_desc ) );
656
657 adapter->tx_head = ( adapter->tx_head + 1 ) % NUM_TX_DESC;
658 }
659
660 /* Process received packets
661 */
662 while ( 1 ) {
663
664 i = adapter->rx_curr;
665
666 rx_curr_desc = ( void * ) ( adapter->rx_base ) +
667 ( i * sizeof ( *adapter->rx_base ) );
668 rx_status = rx_curr_desc->status;
669
670 DBG2 ( "Before DD Check RX_status: %#08x\n", rx_status );
671
672 if ( ! ( rx_status & E1000_RXD_STAT_DD ) )
673 break;
674
675 DBG ( "RCTL = %#08x\n", E1000_READ_REG ( &adapter->hw, RCTL ) );
676
677 rx_len = rx_curr_desc->length;
678
679 DBG ( "Received packet, rx_curr: %d rx_status: %#08x rx_len: %d\n",
680 i, rx_status, rx_len );
681
682 rx_err = rx_curr_desc->errors;
683
684 if ( rx_err & E1000_RXD_ERR_FRAME_ERR_MASK ) {
685
686 netdev_rx_err ( netdev, NULL, -EINVAL );
687 DBG ( "e1000_poll: Corrupted packet received!"
688 " rx_err: %#08x\n", rx_err );
689 } else {
690
691 /* If unable allocate space for this packet,
692 * try again next poll
693 */
694 rx_iob = alloc_iob ( rx_len );
695 if ( ! rx_iob )
696 break;
697
698 memcpy ( iob_put ( rx_iob, rx_len ),
699 adapter->rx_iobuf[i]->data, rx_len );
700
701 /* Add this packet to the receive queue.
702 */
703 netdev_rx ( netdev, rx_iob );
704 }
705
706 tmp_buffer_addr = rx_curr_desc->buffer_addr;
707 memset ( rx_curr_desc, 0, sizeof ( *rx_curr_desc ) );
708 rx_curr_desc->buffer_addr = tmp_buffer_addr;
709
710 E1000_WRITE_REG ( hw, RDT, adapter->rx_curr );
711
712 adapter->rx_curr = ( adapter->rx_curr + 1 ) % NUM_RX_DESC;
713 }
714 }
715
716 /**
717 * e1000_irq - enable or Disable interrupts
718 *
719 * @v adapter e1000 adapter
720 * @v action requested interrupt action
721 **/
722 static void
723 e1000_irq ( struct net_device *netdev, int enable )
724 {
725 struct e1000_adapter *adapter = netdev_priv(netdev);
726
727 DBG ( "e1000_irq\n" );
728
729 switch ( enable ) {
730 case 0 :
731 e1000_irq_disable ( adapter );
732 break;
733 case 1 :
734 e1000_irq_enable ( adapter );
735 break;
736 case 2 :
737 e1000_irq_force ( adapter );
738 break;
739 }
740 }
741
742 static struct net_device_operations e1000_operations;
743
744 /**
745 * e1000_probe - Initial configuration of e1000 NIC
746 *
747 * @v pci PCI device
748 * @v id PCI IDs
749 *
750 * @ret rc Return status code
751 **/
752 static int
753 e1000_probe ( struct pci_device *pdev,
754 const struct pci_device_id *id __unused )
755 {
756 int i, err;
757 struct net_device *netdev;
758 struct e1000_adapter *adapter;
759 unsigned long mmio_start, mmio_len;
760 unsigned long flash_start, flash_len;
761
762 DBG ( "e1000_probe\n" );
763
764 err = -ENOMEM;
765
766 /* Allocate net device ( also allocates memory for netdev->priv
767 and makes netdev-priv point to it ) */
768 netdev = alloc_etherdev ( sizeof ( struct e1000_adapter ) );
769 if ( ! netdev )
770 goto err_alloc_etherdev;
771
772 /* Associate e1000-specific network operations operations with
773 * generic network device layer */
774 netdev_init ( netdev, &e1000_operations );
775
776 /* Associate this network device with given PCI device */
777 pci_set_drvdata ( pdev, netdev );
778 netdev->dev = &pdev->dev;
779
780 /* Initialize driver private storage */
781 adapter = netdev_priv ( netdev );
782 memset ( adapter, 0, ( sizeof ( *adapter ) ) );
783
784 adapter->hw.io_base = pdev->ioaddr;
785 adapter->ioaddr = pdev->ioaddr;
786 adapter->irqno = pdev->irq;
787 adapter->netdev = netdev;
788 adapter->pdev = pdev;
789 adapter->hw.back = adapter;
790
791 adapter->tx_ring_size = sizeof ( *adapter->tx_base ) * NUM_TX_DESC;
792 adapter->rx_ring_size = sizeof ( *adapter->rx_base ) * NUM_RX_DESC;
793
794 mmio_start = pci_bar_start ( pdev, PCI_BASE_ADDRESS_0 );
795 mmio_len = pci_bar_size ( pdev, PCI_BASE_ADDRESS_0 );
796
797 DBG ( "mmio_start: %#08lx\n", mmio_start );
798 DBG ( "mmio_len: %#08lx\n", mmio_len );
799
800 /* Fix up PCI device */
801 adjust_pci_device ( pdev );
802
803 err = -EIO;
804
805 adapter->hw.hw_addr = ioremap ( mmio_start, mmio_len );
806 DBG ( "adapter->hw.hw_addr: %p\n", adapter->hw.hw_addr );
807
808 if ( ! adapter->hw.hw_addr )
809 goto err_ioremap;
810
811 /* setup the private structure */
812 if ( ( err = e1000_sw_init ( adapter ) ) )
813 goto err_sw_init;
814
815 DBG ( "adapter->hw.mac_type: %#08x\n", adapter->hw.mac_type );
816
817 /* Flash BAR mapping must happen after e1000_sw_init
818 * because it depends on mac_type
819 */
820 if ( ( adapter->hw.mac_type == e1000_ich8lan ) && ( pdev->ioaddr ) ) {
821 flash_start = pci_bar_start ( pdev, PCI_BASE_ADDRESS_1 );
822 flash_len = pci_bar_size ( pdev, PCI_BASE_ADDRESS_1 );
823 adapter->hw.flash_address = ioremap ( flash_start, flash_len );
824 if ( ! adapter->hw.flash_address )
825 goto err_flashmap;
826 }
827
828 /* initialize eeprom parameters */
829 if ( e1000_init_eeprom_params ( &adapter->hw ) ) {
830 DBG ( "EEPROM initialization failed\n" );
831 goto err_eeprom;
832 }
833
834 /* before reading the EEPROM, reset the controller to
835 * put the device in a known good starting state
836 */
837 err = e1000_reset_hw ( &adapter->hw );
838 if ( err < 0 ) {
839 DBG ( "Hardware Initialization Failed\n" );
840 goto err_reset;
841 }
842
843 /* make sure the EEPROM is good */
844 if ( e1000_validate_eeprom_checksum( &adapter->hw ) < 0 ) {
845 DBG ( "The EEPROM Checksum Is Not Valid\n" );
846 goto err_eeprom;
847 }
848
849 /* copy the MAC address out of the EEPROM */
850 if ( e1000_read_mac_addr ( &adapter->hw ) )
851 DBG ( "EEPROM Read Error\n" );
852
853 memcpy ( netdev->ll_addr, adapter->hw.mac_addr, ETH_ALEN );
854
855 /* print bus type/speed/width info */
856 {
857 struct e1000_hw *hw = &adapter->hw;
858 DBG ( "(PCI%s:%s:%s) ",
859 ((hw->bus_type == e1000_bus_type_pcix) ? "-X" :
860 (hw->bus_type == e1000_bus_type_pci_express ? " Express":"")),
861 ((hw->bus_speed == e1000_bus_speed_2500) ? "2.5Gb/s" :
862 (hw->bus_speed == e1000_bus_speed_133) ? "133MHz" :
863 (hw->bus_speed == e1000_bus_speed_120) ? "120MHz" :
864 (hw->bus_speed == e1000_bus_speed_100) ? "100MHz" :
865 (hw->bus_speed == e1000_bus_speed_66) ? "66MHz" : "33MHz"),
866 ((hw->bus_width == e1000_bus_width_64) ? "64-bit" :
867 (hw->bus_width == e1000_bus_width_pciex_4) ? "Width x4" :
868 (hw->bus_width == e1000_bus_width_pciex_1) ? "Width x1" :
869 "32-bit"));
870 }
871 for (i = 0; i < 6; i++)
872 DBG ("%02x%s", netdev->ll_addr[i], i == 5 ? "\n" : ":");
873
874 /* reset the hardware with the new settings */
875 e1000_reset ( adapter );
876
877 e1000_get_hw_control ( adapter );
878
879 /* Mark as link up; we don't yet handle link state */
880 netdev_link_up ( netdev );
881
882 if ( ( err = register_netdev ( netdev ) ) != 0)
883 goto err_register;
884
885 DBG ( "e1000_probe succeeded!\n" );
886
887 /* No errors, return success */
888 return 0;
889
890 /* Error return paths */
891 err_reset:
892 err_register:
893 err_eeprom:
894 if ( ! e1000_check_phy_reset_block ( &adapter->hw ) )
895 e1000_phy_hw_reset ( &adapter->hw );
896 if ( adapter->hw.flash_address )
897 iounmap ( adapter->hw.flash_address );
898 err_flashmap:
899 err_sw_init:
900 iounmap ( adapter->hw.hw_addr );
901 err_ioremap:
902 netdev_put ( netdev );
903 err_alloc_etherdev:
904 return err;
905 }
906
907 /**
908 * e1000_remove - Device Removal Routine
909 *
910 * @v pdev PCI device information struct
911 *
912 **/
913 static void
914 e1000_remove ( struct pci_device *pdev )
915 {
916 struct net_device *netdev = pci_get_drvdata ( pdev );
917 struct e1000_adapter *adapter = netdev_priv ( netdev );
918
919 DBG ( "e1000_remove\n" );
920
921 if ( adapter->hw.flash_address )
922 iounmap ( adapter->hw.flash_address );
923 if ( adapter->hw.hw_addr )
924 iounmap ( adapter->hw.hw_addr );
925
926 unregister_netdev ( netdev );
927 e1000_reset_hw ( &adapter->hw );
928 netdev_nullify ( netdev );
929 netdev_put ( netdev );
930 }
931
932 /**
933 * e1000_open - Called when a network interface is made active
934 *
935 * @v netdev network interface device structure
936 * @ret rc Return status code, 0 on success, negative value on failure
937 *
938 **/
939 static int
940 e1000_open ( struct net_device *netdev )
941 {
942 struct e1000_adapter *adapter = netdev_priv(netdev);
943 int err;
944
945 DBG ( "e1000_open\n" );
946
947 /* allocate transmit descriptors */
948 err = e1000_setup_tx_resources ( adapter );
949 if ( err ) {
950 DBG ( "Error setting up TX resources!\n" );
951 goto err_setup_tx;
952 }
953
954 /* allocate receive descriptors */
955 err = e1000_setup_rx_resources ( adapter );
956 if ( err ) {
957 DBG ( "Error setting up RX resources!\n" );
958 goto err_setup_rx;
959 }
960
961 e1000_configure_tx ( adapter );
962
963 e1000_configure_rx ( adapter );
964
965 DBG ( "RXDCTL: %#08x\n", E1000_READ_REG ( &adapter->hw, RXDCTL ) );
966
967 return 0;
968
969 err_setup_rx:
970 e1000_free_tx_resources ( adapter );
971 err_setup_tx:
972 e1000_reset ( adapter );
973
974 return err;
975 }
976
977 /** e1000 net device operations */
978 static struct net_device_operations e1000_operations = {
979 .open = e1000_open,
980 .close = e1000_close,
981 .transmit = e1000_transmit,
982 .poll = e1000_poll,
983 .irq = e1000_irq,
984 };
985
986 int32_t
987 e1000_read_pcie_cap_reg(struct e1000_hw *hw, uint32_t reg, uint16_t *value)
988 {
989 struct e1000_adapter *adapter = hw->back;
990 uint16_t cap_offset;
991
992 #define PCI_CAP_ID_EXP 0x10 /* PCI Express */
993 cap_offset = pci_find_capability(adapter->pdev, PCI_CAP_ID_EXP);
994 if (!cap_offset)
995 return -E1000_ERR_CONFIG;
996
997 pci_read_config_word(adapter->pdev, cap_offset + reg, value);
998
999 return 0;
1000 }
1001
1002 void
1003 e1000_pci_clear_mwi ( struct e1000_hw *hw )
1004 {
1005 struct e1000_adapter *adapter = hw->back;
1006
1007 pci_write_config_word ( adapter->pdev, PCI_COMMAND,
1008 hw->pci_cmd_word & ~PCI_COMMAND_INVALIDATE );
1009 }
1010
1011 void
1012 e1000_pci_set_mwi ( struct e1000_hw *hw )
1013 {
1014 struct e1000_adapter *adapter = hw->back;
1015
1016 pci_write_config_word ( adapter->pdev, PCI_COMMAND, hw->pci_cmd_word );
1017 }
1018
1019 void
1020 e1000_read_pci_cfg ( struct e1000_hw *hw, uint32_t reg, uint16_t *value )
1021 {
1022 struct e1000_adapter *adapter = hw->back;
1023
1024 pci_read_config_word ( adapter->pdev, reg, value );
1025 }
1026
1027 void
1028 e1000_write_pci_cfg ( struct e1000_hw *hw, uint32_t reg, uint16_t *value )
1029 {
1030 struct e1000_adapter *adapter = hw->back;
1031
1032 pci_write_config_word ( adapter->pdev, reg, *value );
1033 }
1034
1035 void
1036 e1000_io_write ( struct e1000_hw *hw __unused, unsigned long port, uint32_t value )
1037 {
1038 outl ( value, port );
1039 }
1040
1041 static struct pci_device_id e1000_nics[] = {
1042 PCI_ROM(0x8086, 0x1000, "e1000-0x1000", "e1000-0x1000"),
1043 PCI_ROM(0x8086, 0x1001, "e1000-0x1001", "e1000-0x1001"),
1044 PCI_ROM(0x8086, 0x1004, "e1000-0x1004", "e1000-0x1004"),
1045 PCI_ROM(0x8086, 0x1008, "e1000-0x1008", "e1000-0x1008"),
1046 PCI_ROM(0x8086, 0x1009, "e1000-0x1009", "e1000-0x1009"),
1047 PCI_ROM(0x8086, 0x100c, "e1000-0x100c", "e1000-0x100c"),
1048 PCI_ROM(0x8086, 0x100d, "e1000-0x100d", "e1000-0x100d"),
1049 PCI_ROM(0x8086, 0x100e, "e1000-0x100e", "e1000-0x100e"),
1050 PCI_ROM(0x8086, 0x100f, "e1000-0x100f", "e1000-0x100f"),
1051 PCI_ROM(0x8086, 0x1010, "e1000-0x1010", "e1000-0x1010"),
1052 PCI_ROM(0x8086, 0x1011, "e1000-0x1011", "e1000-0x1011"),
1053 PCI_ROM(0x8086, 0x1012, "e1000-0x1012", "e1000-0x1012"),
1054 PCI_ROM(0x8086, 0x1013, "e1000-0x1013", "e1000-0x1013"),
1055 PCI_ROM(0x8086, 0x1014, "e1000-0x1014", "e1000-0x1014"),
1056 PCI_ROM(0x8086, 0x1015, "e1000-0x1015", "e1000-0x1015"),
1057 PCI_ROM(0x8086, 0x1016, "e1000-0x1016", "e1000-0x1016"),
1058 PCI_ROM(0x8086, 0x1017, "e1000-0x1017", "e1000-0x1017"),
1059 PCI_ROM(0x8086, 0x1018, "e1000-0x1018", "e1000-0x1018"),
1060 PCI_ROM(0x8086, 0x1019, "e1000-0x1019", "e1000-0x1019"),
1061 PCI_ROM(0x8086, 0x101a, "e1000-0x101a", "e1000-0x101a"),
1062 PCI_ROM(0x8086, 0x101d, "e1000-0x101d", "e1000-0x101d"),
1063 PCI_ROM(0x8086, 0x101e, "e1000-0x101e", "e1000-0x101e"),
1064 PCI_ROM(0x8086, 0x1026, "e1000-0x1026", "e1000-0x1026"),
1065 PCI_ROM(0x8086, 0x1027, "e1000-0x1027", "e1000-0x1027"),
1066 PCI_ROM(0x8086, 0x1028, "e1000-0x1028", "e1000-0x1028"),
1067 PCI_ROM(0x8086, 0x1049, "e1000-0x1049", "e1000-0x1049"),
1068 PCI_ROM(0x8086, 0x104a, "e1000-0x104a", "e1000-0x104a"),
1069 PCI_ROM(0x8086, 0x104b, "e1000-0x104b", "e1000-0x104b"),
1070 PCI_ROM(0x8086, 0x104c, "e1000-0x104c", "e1000-0x104c"),
1071 PCI_ROM(0x8086, 0x104d, "e1000-0x104d", "e1000-0x104d"),
1072 PCI_ROM(0x8086, 0x105e, "e1000-0x105e", "e1000-0x105e"),
1073 PCI_ROM(0x8086, 0x105f, "e1000-0x105f", "e1000-0x105f"),
1074 PCI_ROM(0x8086, 0x1060, "e1000-0x1060", "e1000-0x1060"),
1075 PCI_ROM(0x8086, 0x1075, "e1000-0x1075", "e1000-0x1075"),
1076 PCI_ROM(0x8086, 0x1076, "e1000-0x1076", "e1000-0x1076"),
1077 PCI_ROM(0x8086, 0x1077, "e1000-0x1077", "e1000-0x1077"),
1078 PCI_ROM(0x8086, 0x1078, "e1000-0x1078", "e1000-0x1078"),
1079 PCI_ROM(0x8086, 0x1079, "e1000-0x1079", "e1000-0x1079"),
1080 PCI_ROM(0x8086, 0x107a, "e1000-0x107a", "e1000-0x107a"),
1081 PCI_ROM(0x8086, 0x107b, "e1000-0x107b", "e1000-0x107b"),
1082 PCI_ROM(0x8086, 0x107c, "e1000-0x107c", "e1000-0x107c"),
1083 PCI_ROM(0x8086, 0x107d, "e1000-0x107d", "e1000-0x107d"),
1084 PCI_ROM(0x8086, 0x107e, "e1000-0x107e", "e1000-0x107e"),
1085 PCI_ROM(0x8086, 0x107f, "e1000-0x107f", "e1000-0x107f"),
1086 PCI_ROM(0x8086, 0x108a, "e1000-0x108a", "e1000-0x108a"),
1087 PCI_ROM(0x8086, 0x108b, "e1000-0x108b", "e1000-0x108b"),
1088 PCI_ROM(0x8086, 0x108c, "e1000-0x108c", "e1000-0x108c"),
1089 PCI_ROM(0x8086, 0x1096, "e1000-0x1096", "e1000-0x1096"),
1090 PCI_ROM(0x8086, 0x1098, "e1000-0x1098", "e1000-0x1098"),
1091 PCI_ROM(0x8086, 0x1099, "e1000-0x1099", "e1000-0x1099"),
1092 PCI_ROM(0x8086, 0x109a, "e1000-0x109a", "e1000-0x109a"),
1093 PCI_ROM(0x8086, 0x10a4, "e1000-0x10a4", "e1000-0x10a4"),
1094 PCI_ROM(0x8086, 0x10a5, "e1000-0x10a5", "e1000-0x10a5"),
1095 PCI_ROM(0x8086, 0x10b5, "e1000-0x10b5", "e1000-0x10b5"),
1096 PCI_ROM(0x8086, 0x10b9, "e1000-0x10b9", "e1000-0x10b9"),
1097 PCI_ROM(0x8086, 0x10ba, "e1000-0x10ba", "e1000-0x10ba"),
1098 PCI_ROM(0x8086, 0x10bb, "e1000-0x10bb", "e1000-0x10bb"),
1099 PCI_ROM(0x8086, 0x10bc, "e1000-0x10bc", "e1000-0x10bc"),
1100 PCI_ROM(0x8086, 0x10c4, "e1000-0x10c4", "e1000-0x10c4"),
1101 PCI_ROM(0x8086, 0x10c5, "e1000-0x10c5", "e1000-0x10c5"),
1102 PCI_ROM(0x8086, 0x10d9, "e1000-0x10d9", "e1000-0x10d9"),
1103 PCI_ROM(0x8086, 0x10da, "e1000-0x10da", "e1000-0x10da"),
1104 };
1105
1106 struct pci_driver e1000_driver __pci_driver = {
1107 .ids = e1000_nics,
1108 .id_count = (sizeof (e1000_nics) / sizeof (e1000_nics[0])),
1109 .probe = e1000_probe,
1110 .remove = e1000_remove,
1111 };
1112
1113 /*
1114 * Local variables:
1115 * c-basic-offset: 8
1116 * c-indent-level: 8
1117 * tab-width: 8
1118 * End:
1119 */
gPXE - free pxe roms