src/drivers/net/smc9000.c

   1 #ifdef ALLMULTI
   2 #error multicast support is not yet implemented
   3 #endif
   4  /*------------------------------------------------------------------------
   5  * smc9000.c
   6  * This is a Etherboot driver for SMC's 9000 series of Ethernet cards.
   7  *
   8  * Copyright (C) 1998 Daniel Engström <daniel.engstrom@riksnett.no>
   9  * Based on the Linux SMC9000 driver, smc9194.c by Eric Stahlman
  10  * Copyright (C) 1996 by Erik Stahlman <eric@vt.edu>
  11  *
  12  * This software may be used and distributed according to the terms
  13  * of the GNU Public License, incorporated herein by reference.
  14  *
  15  * "Features" of the SMC chip:
  16  *   4608 byte packet memory. ( for the 91C92/4.  Others have more )
  17  *   EEPROM for configuration
  18  *   AUI/TP selection
  19  *
  20  * Authors
  21  *      Erik Stahlman                           <erik@vt.edu>
  22  *      Daniel Engström                         <daniel.engstrom@riksnett.no>
  23  *
  24  * History
  25  * 98-09-25              Daniel Engström Etherboot driver crated from Eric's
  26  *                                       Linux driver.
  27  *
  28  *---------------------------------------------------------------------------*/
  29 #define LINUX_OUT_MACROS 1
  30 #define SMC9000_DEBUG    0
  31
  32 #if SMC9000_DEBUG > 1
  33 #define PRINTK2 printf
  34 #else
  35 #define PRINTK2(args...)
  36 #endif
  37
  38 #include <gpxe/ethernet.h>
  39 #include <errno.h>
  40 #include "etherboot.h"
  41 #include "nic.h"
  42 #include <gpxe/isa.h>
  43 #include "timer.h"
  44 #include "smc9000.h"
  45
  46 # define _outb outb
  47 # define _outw outw
  48
  49 static const char       smc9000_version[] = "Version 0.99 98-09-30";
  50 static const char       *interfaces[ 2 ] = { "TP", "AUI" };
  51 static const char       *chip_ids[ 15 ] =  {
  52    NULL, NULL, NULL,
  53    /* 3 */ "SMC91C90/91C92",
  54    /* 4 */ "SMC91C94",
  55    /* 5 */ "SMC91C95",
  56    NULL,
  57    /* 7 */ "SMC91C100",
  58    /* 8 */ "SMC91C100FD",
  59    /* 9 */ "SMC91C11xFD",
  60    NULL, NULL,
  61    NULL, NULL, NULL
  62 };
  63 static const char      smc91c96_id[] = "SMC91C96";
  64
  65 /*------------------------------------------------------------
  66  . Reads a register from the MII Management serial interface
  67  .-------------------------------------------------------------*/
  68 static word smc_read_phy_register(int ioaddr, byte phyaddr, byte phyreg)
  69 {
  70     int oldBank;
  71     unsigned int i;
  72     byte mask;
  73     word mii_reg;
  74     byte bits[64];
  75     int clk_idx = 0;
  76     int input_idx;
  77     word phydata;
  78
  79     // 32 consecutive ones on MDO to establish sync
  80     for (i = 0; i < 32; ++i)
  81         bits[clk_idx++] = MII_MDOE | MII_MDO;
  82
  83     // Start code <01>
  84     bits[clk_idx++] = MII_MDOE;
  85     bits[clk_idx++] = MII_MDOE | MII_MDO;
  86
  87     // Read command <10>
  88     bits[clk_idx++] = MII_MDOE | MII_MDO;
  89     bits[clk_idx++] = MII_MDOE;
  90
  91     // Output the PHY address, msb first
  92     mask = (byte)0x10;
  93     for (i = 0; i < 5; ++i)
  94     {
  95         if (phyaddr & mask)
  96             bits[clk_idx++] = MII_MDOE | MII_MDO;
  97         else
  98             bits[clk_idx++] = MII_MDOE;
  99
 100         // Shift to next lowest bit
 101         mask >>= 1;
 102     }
 103
 104     // Output the phy register number, msb first
 105     mask = (byte)0x10;
 106     for (i = 0; i < 5; ++i)
 107     {
 108         if (phyreg & mask)
 109             bits[clk_idx++] = MII_MDOE | MII_MDO;
 110         else
 111             bits[clk_idx++] = MII_MDOE;
 112
 113         // Shift to next lowest bit
 114         mask >>= 1;
 115     }
 116
 117     // Tristate and turnaround (2 bit times)
 118     bits[clk_idx++] = 0;
 119     //bits[clk_idx++] = 0;
 120
 121     // Input starts at this bit time
 122     input_idx = clk_idx;
 123
 124     // Will input 16 bits
 125     for (i = 0; i < 16; ++i)
 126         bits[clk_idx++] = 0;
 127
 128     // Final clock bit
 129     bits[clk_idx++] = 0;
 130
 131     // Save the current bank
 132     oldBank = inw( ioaddr+BANK_SELECT );
 133
 134     // Select bank 3
 135     SMC_SELECT_BANK(ioaddr, 3);
 136
 137     // Get the current MII register value
 138     mii_reg = inw( ioaddr+MII_REG );
 139
 140     // Turn off all MII Interface bits
 141     mii_reg &= ~(MII_MDOE|MII_MCLK|MII_MDI|MII_MDO);
 142
 143     // Clock all 64 cycles
 144     for (i = 0; i < sizeof(bits); ++i)
 145     {
 146         // Clock Low - output data
 147         outw( mii_reg | bits[i], ioaddr+MII_REG );
 148         udelay(50);
 149
 150
 151         // Clock Hi - input data
 152         outw( mii_reg | bits[i] | MII_MCLK, ioaddr+MII_REG );
 153         udelay(50);
 154         bits[i] |= inw( ioaddr+MII_REG ) & MII_MDI;
 155     }
 156
 157     // Return to idle state
 158     // Set clock to low, data to low, and output tristated
 159     outw( mii_reg, ioaddr+MII_REG );
 160     udelay(50);
 161
 162     // Restore original bank select
 163     SMC_SELECT_BANK(ioaddr, oldBank);
 164
 165     // Recover input data
 166     phydata = 0;
 167     for (i = 0; i < 16; ++i)
 168     {
 169         phydata <<= 1;
 170
 171         if (bits[input_idx++] & MII_MDI)
 172             phydata |= 0x0001;
 173     }
 174
 175 #if (SMC_DEBUG > 2 )
 176         printf("smc_read_phy_register(): phyaddr=%x,phyreg=%x,phydata=%x\n",
 177                phyaddr, phyreg, phydata);
 178 #endif
 179
 180         return(phydata);
 181 }
 182
 183
 184 /*------------------------------------------------------------
 185  . Writes a register to the MII Management serial interface
 186  .-------------------------------------------------------------*/
 187 static void smc_write_phy_register(int ioaddr,
 188                                    byte phyaddr, byte phyreg, word phydata)
 189 {
 190     int oldBank;
 191     unsigned int i;
 192     word mask;
 193     word mii_reg;
 194     byte bits[65];
 195     int clk_idx = 0;
 196
 197     // 32 consecutive ones on MDO to establish sync
 198     for (i = 0; i < 32; ++i)
 199         bits[clk_idx++] = MII_MDOE | MII_MDO;
 200
 201     // Start code <01>
 202     bits[clk_idx++] = MII_MDOE;
 203     bits[clk_idx++] = MII_MDOE | MII_MDO;
 204
 205     // Write command <01>
 206     bits[clk_idx++] = MII_MDOE;
 207     bits[clk_idx++] = MII_MDOE | MII_MDO;
 208
 209     // Output the PHY address, msb first
 210     mask = (byte)0x10;
 211     for (i = 0; i < 5; ++i)
 212     {
 213         if (phyaddr & mask)
 214             bits[clk_idx++] = MII_MDOE | MII_MDO;
 215         else
 216             bits[clk_idx++] = MII_MDOE;
 217
 218                 // Shift to next lowest bit
 219         mask >>= 1;
 220     }
 221
 222     // Output the phy register number, msb first
 223     mask = (byte)0x10;
 224     for (i = 0; i < 5; ++i)
 225     {
 226         if (phyreg & mask)
 227             bits[clk_idx++] = MII_MDOE | MII_MDO;
 228         else
 229             bits[clk_idx++] = MII_MDOE;
 230
 231         // Shift to next lowest bit
 232         mask >>= 1;
 233     }
 234
 235     // Tristate and turnaround (2 bit times)
 236     bits[clk_idx++] = 0;
 237     bits[clk_idx++] = 0;
 238
 239     // Write out 16 bits of data, msb first
 240     mask = 0x8000;
 241     for (i = 0; i < 16; ++i)
 242     {
 243         if (phydata & mask)
 244             bits[clk_idx++] = MII_MDOE | MII_MDO;
 245         else
 246             bits[clk_idx++] = MII_MDOE;
 247
 248         // Shift to next lowest bit
 249         mask >>= 1;
 250     }
 251
 252     // Final clock bit (tristate)
 253     bits[clk_idx++] = 0;
 254
 255     // Save the current bank
 256     oldBank = inw( ioaddr+BANK_SELECT );
 257
 258     // Select bank 3
 259     SMC_SELECT_BANK(ioaddr, 3);
 260
 261     // Get the current MII register value
 262     mii_reg = inw( ioaddr+MII_REG );
 263
 264     // Turn off all MII Interface bits
 265     mii_reg &= ~(MII_MDOE|MII_MCLK|MII_MDI|MII_MDO);
 266
 267     // Clock all cycles
 268     for (i = 0; i < sizeof(bits); ++i)
 269     {
 270         // Clock Low - output data
 271         outw( mii_reg | bits[i], ioaddr+MII_REG );
 272         udelay(50);
 273
 274
 275         // Clock Hi - input data
 276         outw( mii_reg | bits[i] | MII_MCLK, ioaddr+MII_REG );
 277         udelay(50);
 278         bits[i] |= inw( ioaddr+MII_REG ) & MII_MDI;
 279     }
 280
 281     // Return to idle state
 282     // Set clock to low, data to low, and output tristated
 283     outw( mii_reg, ioaddr+MII_REG );
 284     udelay(50);
 285
 286     // Restore original bank select
 287     SMC_SELECT_BANK(ioaddr, oldBank);
 288
 289 #if (SMC_DEBUG > 2 )
 290         printf("smc_write_phy_register(): phyaddr=%x,phyreg=%x,phydata=%x\n",
 291                phyaddr, phyreg, phydata);
 292 #endif
 293 }
 294
 295
 296 /*------------------------------------------------------------
 297  . Finds and reports the PHY address
 298  .-------------------------------------------------------------*/
 299 static int smc_detect_phy(int ioaddr, byte *pphyaddr)
 300 {
 301     word phy_id1;
 302     word phy_id2;
 303     int phyaddr;
 304     int found = 0;
 305
 306     // Scan all 32 PHY addresses if necessary
 307     for (phyaddr = 0; phyaddr < 32; ++phyaddr)
 308     {
 309         // Read the PHY identifiers
 310         phy_id1  = smc_read_phy_register(ioaddr, phyaddr, PHY_ID1_REG);
 311         phy_id2  = smc_read_phy_register(ioaddr, phyaddr, PHY_ID2_REG);
 312
 313         // Make sure it is a valid identifier
 314         if ((phy_id2 > 0x0000) && (phy_id2 < 0xffff) &&
 315              (phy_id1 > 0x0000) && (phy_id1 < 0xffff))
 316         {
 317             if ((phy_id1 != 0x8000) && (phy_id2 != 0x8000))
 318             {
 319                 // Save the PHY's address
 320                 *pphyaddr = phyaddr;
 321                 found = 1;
 322                 break;
 323             }
 324         }
 325     }
 326
 327     if (!found)
 328     {
 329         printf("No PHY found\n");
 330         return(0);
 331     }
 332
 333     // Set the PHY type
 334     if ( (phy_id1 == 0x0016) && ((phy_id2 & 0xFFF0) == 0xF840 ) )
 335     {
 336         printf("PHY=LAN83C183 (LAN91C111 Internal)\n");
 337     }
 338
 339     if ( (phy_id1 == 0x0282) && ((phy_id2 & 0xFFF0) == 0x1C50) )
 340     {
 341         printf("PHY=LAN83C180\n");
 342     }
 343
 344     return(1);
 345 }
 346
 347 /*------------------------------------------------------------
 348  . Configures the specified PHY using Autonegotiation. Calls
 349  . smc_phy_fixed() if the user has requested a certain config.
 350  .-------------------------------------------------------------*/
 351 static void smc_phy_configure(int ioaddr)
 352 {
 353     int timeout;
 354     byte phyaddr;
 355     word my_phy_caps; // My PHY capabilities
 356     word my_ad_caps; // My Advertised capabilities
 357     word status;
 358     int failed = 0;
 359     int rpc_cur_mode = RPC_DEFAULT;
 360     int lastPhy18;
 361
 362     // Find the address and type of our phy
 363     if (!smc_detect_phy(ioaddr, &phyaddr))
 364     {
 365         return;
 366     }
 367
 368     // Reset the PHY, setting all other bits to zero
 369     smc_write_phy_register(ioaddr, phyaddr, PHY_CNTL_REG, PHY_CNTL_RST);
 370
 371     // Wait for the reset to complete, or time out
 372     timeout = 6; // Wait up to 3 seconds
 373     while (timeout--)
 374     {
 375         if (!(smc_read_phy_register(ioaddr, phyaddr, PHY_CNTL_REG)
 376               & PHY_CNTL_RST))
 377         {
 378             // reset complete
 379             break;
 380         }
 381
 382         mdelay(500); // wait 500 millisecs
 383     }
 384
 385     if (timeout < 1)
 386     {
 387         PRINTK2("PHY reset timed out\n");
 388         return;
 389     }
 390
 391     // Read PHY Register 18, Status Output
 392     lastPhy18 = smc_read_phy_register(ioaddr, phyaddr, PHY_INT_REG);
 393
 394     // Enable PHY Interrupts (for register 18)
 395     // Interrupts listed here are disabled
 396     smc_write_phy_register(ioaddr, phyaddr, PHY_MASK_REG,
 397                            PHY_INT_LOSSSYNC | PHY_INT_CWRD | PHY_INT_SSD |
 398                                    PHY_INT_ESD | PHY_INT_RPOL | PHY_INT_JAB |
 399                                    PHY_INT_SPDDET | PHY_INT_DPLXDET);
 400
 401     /* Configure the Receive/Phy Control register */
 402     SMC_SELECT_BANK(ioaddr, 0);
 403     outw( rpc_cur_mode, ioaddr + RPC_REG );
 404
 405     // Copy our capabilities from PHY_STAT_REG to PHY_AD_REG
 406     my_phy_caps = smc_read_phy_register(ioaddr, phyaddr, PHY_STAT_REG);
 407     my_ad_caps  = PHY_AD_CSMA; // I am CSMA capable
 408
 409     if (my_phy_caps & PHY_STAT_CAP_T4)
 410         my_ad_caps |= PHY_AD_T4;
 411
 412     if (my_phy_caps & PHY_STAT_CAP_TXF)
 413         my_ad_caps |= PHY_AD_TX_FDX;
 414
 415     if (my_phy_caps & PHY_STAT_CAP_TXH)
 416         my_ad_caps |= PHY_AD_TX_HDX;
 417
 418     if (my_phy_caps & PHY_STAT_CAP_TF)
 419         my_ad_caps |= PHY_AD_10_FDX;
 420
 421     if (my_phy_caps & PHY_STAT_CAP_TH)
 422         my_ad_caps |= PHY_AD_10_HDX;
 423
 424     // Update our Auto-Neg Advertisement Register
 425     smc_write_phy_register(ioaddr, phyaddr, PHY_AD_REG, my_ad_caps);
 426
 427     PRINTK2("phy caps=%x\n", my_phy_caps);
 428     PRINTK2("phy advertised caps=%x\n", my_ad_caps);
 429
 430     // Restart auto-negotiation process in order to advertise my caps
 431     smc_write_phy_register( ioaddr, phyaddr, PHY_CNTL_REG,
 432                             PHY_CNTL_ANEG_EN | PHY_CNTL_ANEG_RST );
 433
 434     // Wait for the auto-negotiation to complete.  This may take from
 435     // 2 to 3 seconds.
 436     // Wait for the reset to complete, or time out
 437     timeout = 20; // Wait up to 10 seconds
 438     while (timeout--)
 439     {
 440         status = smc_read_phy_register(ioaddr, phyaddr, PHY_STAT_REG);
 441         if (status & PHY_STAT_ANEG_ACK)
 442         {
 443             // auto-negotiate complete
 444             break;
 445         }
 446
 447         mdelay(500); // wait 500 millisecs
 448
 449         // Restart auto-negotiation if remote fault
 450         if (status & PHY_STAT_REM_FLT)
 451         {
 452             PRINTK2("PHY remote fault detected\n");
 453
 454             // Restart auto-negotiation
 455             PRINTK2("PHY restarting auto-negotiation\n");
 456             smc_write_phy_register( ioaddr, phyaddr, PHY_CNTL_REG,
 457                                     PHY_CNTL_ANEG_EN | PHY_CNTL_ANEG_RST |
 458                                     PHY_CNTL_SPEED | PHY_CNTL_DPLX);
 459         }
 460     }
 461
 462     if (timeout < 1)
 463     {
 464         PRINTK2("PHY auto-negotiate timed out\n");
 465         failed = 1;
 466     }
 467
 468     // Fail if we detected an auto-negotiate remote fault
 469     if (status & PHY_STAT_REM_FLT)
 470     {
 471         PRINTK2("PHY remote fault detected\n");
 472         failed = 1;
 473     }
 474
 475     // Set our sysctl parameters to match auto-negotiation results
 476     if ( lastPhy18 & PHY_INT_SPDDET )
 477     {
 478         PRINTK2("PHY 100BaseT\n");
 479         rpc_cur_mode |= RPC_SPEED;
 480     }
 481     else
 482     {
 483         PRINTK2("PHY 10BaseT\n");
 484         rpc_cur_mode &= ~RPC_SPEED;
 485     }
 486
 487     if ( lastPhy18 & PHY_INT_DPLXDET )
 488     {
 489         PRINTK2("PHY Full Duplex\n");
 490         rpc_cur_mode |= RPC_DPLX;
 491     }
 492     else
 493     {
 494         PRINTK2("PHY Half Duplex\n");
 495         rpc_cur_mode &= ~RPC_DPLX;
 496     }
 497
 498     // Re-Configure the Receive/Phy Control register
 499     outw( rpc_cur_mode, ioaddr + RPC_REG );
 500 }
 501
 502 /*
 503  * Function: smc_reset( int ioaddr )
 504  * Purpose:
 505  *      This sets the SMC91xx chip to its normal state, hopefully from whatever
 506  *      mess that any other DOS driver has put it in.
 507  *
 508  * Maybe I should reset more registers to defaults in here?  SOFTRESET  should
 509  * do that for me.
 510  *
 511  * Method:
 512  *      1.  send a SOFT RESET
 513  *      2.  wait for it to finish
 514  *      3.  reset the memory management unit
 515  *      4.  clear all interrupts
 516  *
 517 */
 518 static void smc_reset(int ioaddr)
 519 {
 520    /* This resets the registers mostly to defaults, but doesn't
 521     * affect EEPROM.  That seems unnecessary */
 522    SMC_SELECT_BANK(ioaddr, 0);
 523    _outw( RCR_SOFTRESET, ioaddr + RCR );
 524
 525    /* this should pause enough for the chip to be happy */
 526    SMC_DELAY(ioaddr);
 527
 528    /* Set the transmit and receive configuration registers to
 529     * default values */
 530    _outw(RCR_CLEAR, ioaddr + RCR);
 531    _outw(TCR_CLEAR, ioaddr + TCR);
 532
 533    /* Reset the MMU */
 534    SMC_SELECT_BANK(ioaddr, 2);
 535    _outw( MC_RESET, ioaddr + MMU_CMD );
 536
 537    /* Note:  It doesn't seem that waiting for the MMU busy is needed here,
 538     * but this is a place where future chipsets _COULD_ break.  Be wary
 539     * of issuing another MMU command right after this */
 540    _outb(0, ioaddr + INT_MASK);
 541 }
 542
 543
 544 /*----------------------------------------------------------------------
 545  * Function: smc9000_probe_addr( int ioaddr )
 546  *
 547  * Purpose:
 548  *      Tests to see if a given ioaddr points to an SMC9xxx chip.
 549  *      Returns a 1 on success
 550  *
 551  * Algorithm:
 552  *      (1) see if the high byte of BANK_SELECT is 0x33
 553  *      (2) compare the ioaddr with the base register's address
 554  *      (3) see if I recognize the chip ID in the appropriate register
 555  *
 556  * ---------------------------------------------------------------------
 557  */
 558 static int smc9000_probe_addr( isa_probe_addr_t ioaddr )
 559 {
 560    word bank;
 561    word revision_register;
 562    word base_address_register;
 563
 564    /* First, see if the high byte is 0x33 */
 565    bank = inw(ioaddr + BANK_SELECT);
 566    if ((bank & 0xFF00) != 0x3300) {
 567       return 0;
 568    }
 569    /* The above MIGHT indicate a device, but I need to write to further
 570     *   test this.  */
 571    _outw(0x0, ioaddr + BANK_SELECT);
 572    bank = inw(ioaddr + BANK_SELECT);
 573    if ((bank & 0xFF00) != 0x3300) {
 574       return 0;
 575    }
 576
 577    /* well, we've already written once, so hopefully another time won't
 578     *  hurt.  This time, I need to switch the bank register to bank 1,
 579     *  so I can access the base address register */
 580    SMC_SELECT_BANK(ioaddr, 1);
 581    base_address_register = inw(ioaddr + BASE);
 582
 583    if (ioaddr != (base_address_register >> 3 & 0x3E0))  {
 584       DBG("SMC9000: IOADDR %hX doesn't match configuration (%hX)."
 585           "Probably not a SMC chip\n",
 586           ioaddr, base_address_register >> 3 & 0x3E0);
 587       /* well, the base address register didn't match.  Must not have
 588        * been a SMC chip after all. */
 589       return 0;
 590    }
 591
 592
 593    /* check if the revision register is something that I recognize.
 594     * These might need to be added to later, as future revisions
 595     * could be added.  */
 596    SMC_SELECT_BANK(ioaddr, 3);
 597    revision_register  = inw(ioaddr + REVISION);
 598    if (!chip_ids[(revision_register >> 4) & 0xF]) {
 599       /* I don't recognize this chip, so... */
 600       DBG( "SMC9000: IO %hX: Unrecognized revision register:"
 601            " %hX, Contact author.\n", ioaddr, revision_register );
 602       return 0;
 603    }
 604
 605    /* at this point I'll assume that the chip is an SMC9xxx.
 606     * It might be prudent to check a listing of MAC addresses
 607     * against the hardware address, or do some other tests. */
 608    return 1;
 609 }
 610
 611
 612 /**************************************************************************
 613  * ETH_TRANSMIT - Transmit a frame
 614  ***************************************************************************/
 615 static void smc9000_transmit(
 616         struct nic *nic,
 617         const char *d,                  /* Destination */
 618         unsigned int t,                 /* Type */
 619         unsigned int s,                 /* size */
 620         const char *p)                  /* Packet */
 621 {
 622    word length; /* real, length incl. header */
 623    word numPages;
 624    unsigned long time_out;
 625    byte packet_no;
 626    word status;
 627    int i;
 628
 629    /* We dont pad here since we can have the hardware doing it for us */
 630    length = (s + ETH_HLEN + 1)&~1;
 631
 632    /* convert to MMU pages */
 633    numPages = length / 256;
 634
 635    if (numPages > 7 ) {
 636       DBG("SMC9000: Far too big packet error. \n");
 637       return;
 638    }
 639
 640    /* dont try more than, say 30 times */
 641    for (i=0;i<30;i++) {
 642       /* now, try to allocate the memory */
 643       SMC_SELECT_BANK(nic->ioaddr, 2);
 644       _outw(MC_ALLOC | numPages, nic->ioaddr + MMU_CMD);
 645
 646       status = 0;
 647       /* wait for the memory allocation to finnish */
 648       for (time_out = currticks() + 5*TICKS_PER_SEC; currticks() < time_out; ) {
 649          status = inb(nic->ioaddr + INTERRUPT);
 650          if ( status & IM_ALLOC_INT ) {
 651             /* acknowledge the interrupt */
 652             _outb(IM_ALLOC_INT, nic->ioaddr + INTERRUPT);
 653             break;
 654          }
 655       }
 656
 657       if ((status & IM_ALLOC_INT) != 0 ) {
 658          /* We've got the memory */
 659          break;
 660       } else {
 661          printf("SMC9000: Memory allocation timed out, resetting MMU.\n");
 662          _outw(MC_RESET, nic->ioaddr + MMU_CMD);
 663       }
 664    }
 665
 666    /* If I get here, I _know_ there is a packet slot waiting for me */
 667    packet_no = inb(nic->ioaddr + PNR_ARR + 1);
 668    if (packet_no & 0x80) {
 669       /* or isn't there?  BAD CHIP! */
 670       printf("SMC9000: Memory allocation failed. \n");
 671       return;
 672    }
 673
 674    /* we have a packet address, so tell the card to use it */
 675    _outb(packet_no, nic->ioaddr + PNR_ARR);
 676
 677    /* point to the beginning of the packet */
 678    _outw(PTR_AUTOINC, nic->ioaddr + POINTER);
 679
 680 #if     SMC9000_DEBUG > 2
 681    printf("Trying to xmit packet of length %hX\n", length );
 682 #endif
 683
 684    /* send the packet length ( +6 for status, length and ctl byte )
 685     * and the status word ( set to zeros ) */
 686    _outw(0, nic->ioaddr + DATA_1 );
 687
 688    /* send the packet length ( +6 for status words, length, and ctl) */
 689    _outb((length+6) & 0xFF,  nic->ioaddr + DATA_1);
 690    _outb((length+6) >> 8 ,   nic->ioaddr + DATA_1);
 691
 692    /* Write the contents of the packet */
 693
 694    /* The ethernet header first... */
 695    outsw(nic->ioaddr + DATA_1, d, ETH_ALEN >> 1);
 696    outsw(nic->ioaddr + DATA_1, nic->node_addr, ETH_ALEN >> 1);
 697    _outw(htons(t), nic->ioaddr + DATA_1);
 698
 699    /* ... the data ... */
 700    outsw(nic->ioaddr + DATA_1 , p, s >> 1);
 701
 702    /* ... and the last byte, if there is one.   */
 703    if ((s & 1) == 0) {
 704       _outw(0, nic->ioaddr + DATA_1);
 705    } else {
 706       _outb(p[s-1], nic->ioaddr + DATA_1);
 707       _outb(0x20, nic->ioaddr + DATA_1);
 708    }
 709
 710    /* and let the chipset deal with it */
 711    _outw(MC_ENQUEUE , nic->ioaddr + MMU_CMD);
 712
 713    status = 0; time_out = currticks() + 5*TICKS_PER_SEC;
 714    do {
 715       status = inb(nic->ioaddr + INTERRUPT);
 716
 717       if ((status & IM_TX_INT ) != 0) {
 718          word tx_status;
 719
 720          /* ack interrupt */
 721          _outb(IM_TX_INT, nic->ioaddr + INTERRUPT);
 722
 723          packet_no = inw(nic->ioaddr + FIFO_PORTS);
 724          packet_no &= 0x7F;
 725
 726          /* select this as the packet to read from */
 727          _outb( packet_no, nic->ioaddr + PNR_ARR );
 728
 729          /* read the first word from this packet */
 730          _outw( PTR_AUTOINC | PTR_READ, nic->ioaddr + POINTER );
 731
 732          tx_status = inw( nic->ioaddr + DATA_1 );
 733
 734          if (0 == (tx_status & TS_SUCCESS)) {
 735             DBG("SMC9000: TX FAIL STATUS: %hX \n", tx_status);
 736             /* re-enable transmit */
 737             SMC_SELECT_BANK(nic->ioaddr, 0);
 738             _outw(inw(nic->ioaddr + TCR ) | TCR_ENABLE, nic->ioaddr + TCR );
 739          }
 740
 741          /* kill the packet */
 742          SMC_SELECT_BANK(nic->ioaddr, 2);
 743          _outw(MC_FREEPKT, nic->ioaddr + MMU_CMD);
 744
 745          return;
 746       }
 747    }while(currticks() < time_out);
 748
 749    printf("SMC9000: TX timed out, resetting board\n");
 750    smc_reset(nic->ioaddr);
 751    return;
 752 }
 753
 754 /**************************************************************************
 755  * ETH_POLL - Wait for a frame
 756  ***************************************************************************/
 757 static int smc9000_poll(struct nic *nic, int retrieve)
 758 {
 759    SMC_SELECT_BANK(nic->ioaddr, 2);
 760    if (inw(nic->ioaddr + FIFO_PORTS) & FP_RXEMPTY)
 761      return 0;
 762
 763    if ( ! retrieve ) return 1;
 764
 765    /*  start reading from the start of the packet */
 766    _outw(PTR_READ | PTR_RCV | PTR_AUTOINC, nic->ioaddr + POINTER);
 767
 768    /* First read the status and check that we're ok */
 769    if (!(inw(nic->ioaddr + DATA_1) & RS_ERRORS)) {
 770       /* Next: read the packet length and mask off the top bits */
 771       nic->packetlen = (inw(nic->ioaddr + DATA_1) & 0x07ff);
 772
 773       /* the packet length includes the 3 extra words */
 774       nic->packetlen -= 6;
 775 #if     SMC9000_DEBUG > 2
 776       printf(" Reading %d words (and %d byte(s))\n",
 777                (nic->packetlen >> 1), nic->packetlen & 1);
 778 #endif
 779       /* read the packet (and the last "extra" word) */
 780       insw(nic->ioaddr + DATA_1, nic->packet, (nic->packetlen+2) >> 1);
 781       /* is there an odd last byte ? */
 782       if (nic->packet[nic->packetlen+1] & 0x20)
 783          nic->packetlen++;
 784
 785       /*  error or good, tell the card to get rid of this packet */
 786       _outw(MC_RELEASE, nic->ioaddr + MMU_CMD);
 787       return 1;
 788    }
 789
 790    printf("SMC9000: RX error\n");
 791    /*  error or good, tell the card to get rid of this packet */
 792    _outw(MC_RELEASE, nic->ioaddr + MMU_CMD);
 793    return 0;
 794 }
 795
 796 static void smc9000_disable ( struct nic *nic, struct isa_device *isa __unused ) {
 797
 798    smc_reset(nic->ioaddr);
 799
 800    /* no more interrupts for me */
 801    SMC_SELECT_BANK(nic->ioaddr, 2);
 802    _outb( 0, nic->ioaddr + INT_MASK);
 803
 804    /* and tell the card to stay away from that nasty outside world */
 805    SMC_SELECT_BANK(nic->ioaddr, 0);
 806    _outb( RCR_CLEAR, nic->ioaddr + RCR );
 807    _outb( TCR_CLEAR, nic->ioaddr + TCR );
 808 }
 809
 810 static void smc9000_irq(struct nic *nic __unused, irq_action_t action __unused)
 811 {
 812   switch ( action ) {
 813   case DISABLE :
 814     break;
 815   case ENABLE :
 816     break;
 817   case FORCE :
 818     break;
 819   }
 820 }
 821
 822 static struct nic_operations smc9000_operations = {
 823         .connect        = dummy_connect,
 824         .poll           = smc9000_poll,
 825         .transmit       = smc9000_transmit,
 826         .irq            = smc9000_irq,
 827
 828 };
 829
 830 /**************************************************************************
 831  * ETH_PROBE - Look for an adapter
 832  ***************************************************************************/
 833
 834 static int smc9000_probe ( struct nic *nic, struct isa_device *isa ) {
 835
 836    unsigned short   revision;
 837    int              memory;
 838    int              media;
 839    const char *     version_string;
 840    const char *     if_string;
 841    int              i;
 842
 843    nic->irqno  = 0;
 844    nic->ioaddr = isa->ioaddr;
 845
 846    /*
 847     * Get the MAC address ( bank 1, regs 4 - 9 )
 848     */
 849    SMC_SELECT_BANK(nic->ioaddr, 1);
 850    for ( i = 0; i < 6; i += 2 ) {
 851       word address;
 852
 853       address = inw(nic->ioaddr + ADDR0 + i);
 854       nic->node_addr[i+1] = address >> 8;
 855       nic->node_addr[i] = address & 0xFF;
 856    }
 857
 858    /* get the memory information */
 859    SMC_SELECT_BANK(nic->ioaddr, 0);
 860    memory = ( inw(nic->ioaddr + MCR) >> 9 )  & 0x7;  /* multiplier */
 861    memory *= 256 * (inw(nic->ioaddr + MIR) & 0xFF);
 862
 863    /*
 864     * Now, I want to find out more about the chip.  This is sort of
 865     * redundant, but it's cleaner to have it in both, rather than having
 866     * one VERY long probe procedure.
 867     */
 868    SMC_SELECT_BANK(nic->ioaddr, 3);
 869    revision  = inw(nic->ioaddr + REVISION);
 870    version_string = chip_ids[(revision >> 4) & 0xF];
 871
 872    if (((revision & 0xF0) >> 4 == CHIP_9196) &&
 873        ((revision & 0x0F) >= REV_9196)) {
 874       /* This is a 91c96. 'c96 has the same chip id as 'c94 (4) but
 875        * a revision starting at 6 */
 876       version_string = smc91c96_id;
 877    }
 878
 879    if ( !version_string ) {
 880       /* I shouldn't get here because this call was done before.... */
 881       return 0;
 882    }
 883
 884    /* is it using AUI or 10BaseT ? */
 885    SMC_SELECT_BANK(nic->ioaddr, 1);
 886    if (inw(nic->ioaddr + CONFIG) & CFG_AUI_SELECT)
 887      media = 2;
 888    else
 889      media = 1;
 890
 891    if_string = interfaces[media - 1];
 892
 893    /* now, reset the chip, and put it into a known state */
 894    smc_reset(nic->ioaddr);
 895
 896    printf("SMC9000 %s\n", smc9000_version);
 897    DBG("Copyright (C) 1998 Daniel Engstr\x94m\n");
 898    DBG("Copyright (C) 1996 Eric Stahlman\n");
 899
 900    printf("%s rev:%d I/O port:%hX Interface:%s RAM:%d bytes \n",
 901           version_string, revision & 0xF,
 902           nic->ioaddr, if_string, memory );
 903
 904    DBG ( "Ethernet MAC address: %s\n", eth_ntoa ( nic->node_addr ) );
 905
 906    SMC_SELECT_BANK(nic->ioaddr, 0);
 907
 908    /* see the header file for options in TCR/RCR NORMAL*/
 909    _outw(TCR_NORMAL, nic->ioaddr + TCR);
 910    _outw(RCR_NORMAL, nic->ioaddr + RCR);
 911
 912    /* Select which interface to use */
 913    SMC_SELECT_BANK(nic->ioaddr, 1);
 914    if ( media == 1 ) {
 915       _outw( inw( nic->ioaddr + CONFIG ) & ~CFG_AUI_SELECT,
 916            nic->ioaddr + CONFIG );
 917    }
 918    else if ( media == 2 ) {
 919       _outw( inw( nic->ioaddr + CONFIG ) | CFG_AUI_SELECT,
 920            nic->ioaddr + CONFIG );
 921    }
 922
 923    smc_phy_configure(nic->ioaddr);
 924
 925    nic->nic_op  = &smc9000_operations;
 926    return 1;
 927 }
 928
 929 /*
 930  * The SMC9000 can be at any of the following port addresses.  To
 931  * change for a slightly different card, you can add it to the array.
 932  *
 933  */
 934 static isa_probe_addr_t smc9000_probe_addrs[] = {
 935    0x200, 0x220, 0x240, 0x260, 0x280, 0x2A0, 0x2C0, 0x2E0,
 936    0x300, 0x320, 0x340, 0x360, 0x380, 0x3A0, 0x3C0, 0x3E0,
 937 };
 938
 939 ISA_DRIVER ( smc9000_driver, smc9000_probe_addrs, smc9000_probe_addr,
 940                      GENERIC_ISAPNP_VENDOR, 0x8228 );
 941
 942 DRIVER ( "SMC9000", nic_driver, isa_driver, smc9000_driver,
 943          smc9000_probe, smc9000_disable );
 944
 945 ISA_ROM ( "smc9000", "SMC9000" );
 946
 947 /*
 948  * Local variables:
 949  *  c-basic-offset: 8
 950  *  c-indent-level: 8
 951  *  tab-width: 8
 952  * End:
 953  */