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Warnings purge of drivers (continued)
[gpxe.git] / src / drivers / net / amd8111e.c
blob196ee50e39b181119e3420e72b5166a01409e1c3
1 /* Advanced Micro Devices Inc. AMD8111E Linux Network Driver
2 * Copyright (C) 2004 Advanced Micro Devices
3 * Copyright (C) 2005 Liu Tao <liutao1980@gmail.com> [etherboot port]
4 *
5 * Copyright 2001,2002 Jeff Garzik <jgarzik@mandrakesoft.com> [ 8139cp.c,tg3.c ]
6 * Copyright (C) 2001, 2002 David S. Miller (davem@redhat.com)[ tg3.c]
7 * Copyright 1996-1999 Thomas Bogendoerfer [ pcnet32.c ]
8 * Derived from the lance driver written 1993,1994,1995 by Donald Becker.
9 * Copyright 1993 United States Government as represented by the
10 * Director, National Security Agency.[ pcnet32.c ]
11 * Carsten Langgaard, carstenl@mips.com [ pcnet32.c ]
12 * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
13 *
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2 of the License, or
18 * (at your option) any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, write to the Free Software
27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
28 * USA
29 */
30
31 #include "etherboot.h"
32 #include "nic.h"
33 #include "mii.h"
34 #include <gpxe/pci.h>
35 #include <gpxe/ethernet.h>
36 #include "timer.h"
37 #include "string.h"
38 #include "stdint.h"
39 #include "amd8111e.h"
40
41
42 /* driver definitions */
43 #define NUM_TX_SLOTS 2
44 #define NUM_RX_SLOTS 4
45 #define TX_SLOTS_MASK 1
46 #define RX_SLOTS_MASK 3
47
48 #define TX_BUF_LEN 1536
49 #define RX_BUF_LEN 1536
50
51 #define TX_PKT_LEN_MAX (ETH_FRAME_LEN - ETH_HLEN)
52 #define RX_PKT_LEN_MIN 60
53 #define RX_PKT_LEN_MAX ETH_FRAME_LEN
54
55 #define TX_TIMEOUT 3000
56 #define TX_PROCESS_TIME 10
57 #define TX_RETRY (TX_TIMEOUT / TX_PROCESS_TIME)
58
59 #define PHY_RW_RETRY 10
60
61
62 struct amd8111e_tx_desc {
63 u16 buf_len;
64 u16 tx_flags;
65 u16 tag_ctrl_info;
66 u16 tag_ctrl_cmd;
67 u32 buf_phy_addr;
68 u32 reserved;
69 };
70
71 struct amd8111e_rx_desc {
72 u32 reserved;
73 u16 msg_len;
74 u16 tag_ctrl_info;
75 u16 buf_len;
76 u16 rx_flags;
77 u32 buf_phy_addr;
78 };
79
80 struct eth_frame {
81 u8 dst_addr[ETH_ALEN];
82 u8 src_addr[ETH_ALEN];
83 u16 type;
84 u8 data[ETH_FRAME_LEN - ETH_HLEN];
85 } __attribute__((packed));
86
87 struct amd8111e_priv {
88 struct amd8111e_tx_desc tx_ring[NUM_TX_SLOTS];
89 struct amd8111e_rx_desc rx_ring[NUM_RX_SLOTS];
90 unsigned char tx_buf[NUM_TX_SLOTS][TX_BUF_LEN];
91 unsigned char rx_buf[NUM_RX_SLOTS][RX_BUF_LEN];
92 unsigned long tx_idx, rx_idx;
93 int tx_consistent;
94
95 char opened;
96 char link;
97 char speed;
98 char duplex;
99 int ext_phy_addr;
100 u32 ext_phy_id;
101
102 struct pci_device *pdev;
103 struct nic *nic;
104 void *mmio;
105 };
106
107 static struct amd8111e_priv amd8111e;
108
109
110 /********************************************************
111 * locale functions *
112 ********************************************************/
113 static void amd8111e_init_hw_default(struct amd8111e_priv *lp);
114 static int amd8111e_start(struct amd8111e_priv *lp);
115 static int amd8111e_read_phy(struct amd8111e_priv *lp, int phy_addr, int reg, u32 *val);
116 #if 0
117 static int amd8111e_write_phy(struct amd8111e_priv *lp, int phy_addr, int reg, u32 val);
118 #endif
119 static void amd8111e_probe_ext_phy(struct amd8111e_priv *lp);
120 static void amd8111e_disable_interrupt(struct amd8111e_priv *lp);
121 static void amd8111e_enable_interrupt(struct amd8111e_priv *lp);
122 static void amd8111e_force_interrupt(struct amd8111e_priv *lp);
123 static int amd8111e_get_mac_address(struct amd8111e_priv *lp);
124 static int amd8111e_init_rx_ring(struct amd8111e_priv *lp);
125 static int amd8111e_init_tx_ring(struct amd8111e_priv *lp);
126 static int amd8111e_wait_tx_ring(struct amd8111e_priv *lp, unsigned int index);
127 static void amd8111e_wait_link(struct amd8111e_priv *lp);
128 static void amd8111e_poll_link(struct amd8111e_priv *lp);
129 static void amd8111e_restart(struct amd8111e_priv *lp);
130
131
132 /*
133 * This function clears necessary the device registers.
134 */
135 static void amd8111e_init_hw_default(struct amd8111e_priv *lp)
136 {
137 unsigned int reg_val;
138 void *mmio = lp->mmio;
139
140 /* stop the chip */
141 writel(RUN, mmio + CMD0);
142
143 /* Clear RCV_RING_BASE_ADDR */
144 writel(0, mmio + RCV_RING_BASE_ADDR0);
145
146 /* Clear XMT_RING_BASE_ADDR */
147 writel(0, mmio + XMT_RING_BASE_ADDR0);
148 writel(0, mmio + XMT_RING_BASE_ADDR1);
149 writel(0, mmio + XMT_RING_BASE_ADDR2);
150 writel(0, mmio + XMT_RING_BASE_ADDR3);
151
152 /* Clear CMD0 */
153 writel(CMD0_CLEAR, mmio + CMD0);
154
155 /* Clear CMD2 */
156 writel(CMD2_CLEAR, mmio + CMD2);
157
158 /* Clear CMD7 */
159 writel(CMD7_CLEAR, mmio + CMD7);
160
161 /* Clear DLY_INT_A and DLY_INT_B */
162 writel(0x0, mmio + DLY_INT_A);
163 writel(0x0, mmio + DLY_INT_B);
164
165 /* Clear FLOW_CONTROL */
166 writel(0x0, mmio + FLOW_CONTROL);
167
168 /* Clear INT0 write 1 to clear register */
169 reg_val = readl(mmio + INT0);
170 writel(reg_val, mmio + INT0);
171
172 /* Clear STVAL */
173 writel(0x0, mmio + STVAL);
174
175 /* Clear INTEN0 */
176 writel(INTEN0_CLEAR, mmio + INTEN0);
177
178 /* Clear LADRF */
179 writel(0x0, mmio + LADRF);
180
181 /* Set SRAM_SIZE & SRAM_BOUNDARY registers */
182 writel(0x80010, mmio + SRAM_SIZE);
183
184 /* Clear RCV_RING0_LEN */
185 writel(0x0, mmio + RCV_RING_LEN0);
186
187 /* Clear XMT_RING0/1/2/3_LEN */
188 writel(0x0, mmio + XMT_RING_LEN0);
189 writel(0x0, mmio + XMT_RING_LEN1);
190 writel(0x0, mmio + XMT_RING_LEN2);
191 writel(0x0, mmio + XMT_RING_LEN3);
192
193 /* Clear XMT_RING_LIMIT */
194 writel(0x0, mmio + XMT_RING_LIMIT);
195
196 /* Clear MIB */
197 writew(MIB_CLEAR, mmio + MIB_ADDR);
198
199 /* Clear LARF */
200 writel( 0, mmio + LADRF);
201 writel( 0, mmio + LADRF + 4);
202
203 /* SRAM_SIZE register */
204 reg_val = readl(mmio + SRAM_SIZE);
205
206 /* Set default value to CTRL1 Register */
207 writel(CTRL1_DEFAULT, mmio + CTRL1);
208
209 /* To avoid PCI posting bug */
210 readl(mmio + CMD2);
211 }
212
213 /*
214 * This function initializes the device registers and starts the device.
215 */
216 static int amd8111e_start(struct amd8111e_priv *lp)
217 {
218 struct nic *nic = lp->nic;
219 void *mmio = lp->mmio;
220 int i, reg_val;
221
222 /* stop the chip */
223 writel(RUN, mmio + CMD0);
224
225 /* AUTOPOLL0 Register *//*TBD default value is 8100 in FPS */
226 writew(0x8100 | lp->ext_phy_addr, mmio + AUTOPOLL0);
227
228 /* enable the port manager and set auto negotiation always */
229 writel(VAL1 | EN_PMGR, mmio + CMD3 );
230 writel(XPHYANE | XPHYRST, mmio + CTRL2);
231
232 /* set control registers */
233 reg_val = readl(mmio + CTRL1);
234 reg_val &= ~XMTSP_MASK;
235 writel(reg_val | XMTSP_128 | CACHE_ALIGN, mmio + CTRL1);
236
237 /* initialize tx and rx ring base addresses */
238 amd8111e_init_tx_ring(lp);
239 amd8111e_init_rx_ring(lp);
240 writel(virt_to_bus(lp->tx_ring), mmio + XMT_RING_BASE_ADDR0);
241 writel(virt_to_bus(lp->rx_ring), mmio + RCV_RING_BASE_ADDR0);
242 writew(NUM_TX_SLOTS, mmio + XMT_RING_LEN0);
243 writew(NUM_RX_SLOTS, mmio + RCV_RING_LEN0);
244
245 /* set default IPG to 96 */
246 writew(DEFAULT_IPG, mmio + IPG);
247 writew(DEFAULT_IPG - IFS1_DELTA, mmio + IFS1);
248
249 /* AutoPAD transmit, Retransmit on Underflow */
250 writel(VAL0 | APAD_XMT | REX_RTRY | REX_UFLO, mmio + CMD2);
251
252 /* JUMBO disabled */
253 writel(JUMBO, mmio + CMD3);
254
255 /* Setting the MAC address to the device */
256 for(i = 0; i < ETH_ALEN; i++)
257 writeb(nic->node_addr[i], mmio + PADR + i);
258
259 /* set RUN bit to start the chip, interrupt not enabled */
260 writel(VAL2 | RDMD0 | VAL0 | RUN, mmio + CMD0);
261
262 /* To avoid PCI posting bug */
263 readl(mmio + CMD0);
264 return 0;
265 }
266
267 /*
268 This function will read the PHY registers.
269 */
270 static int amd8111e_read_phy(struct amd8111e_priv *lp, int phy_addr, int reg, u32 *val)
271 {
272 void *mmio = lp->mmio;
273 unsigned int reg_val;
274 unsigned int retry = PHY_RW_RETRY;
275
276 reg_val = readl(mmio + PHY_ACCESS);
277 while (reg_val & PHY_CMD_ACTIVE)
278 reg_val = readl(mmio + PHY_ACCESS);
279
280 writel(PHY_RD_CMD | ((phy_addr & 0x1f) << 21) | ((reg & 0x1f) << 16),
281 mmio + PHY_ACCESS);
282 do {
283 reg_val = readl(mmio + PHY_ACCESS);
284 udelay(30); /* It takes 30 us to read/write data */
285 } while (--retry && (reg_val & PHY_CMD_ACTIVE));
286
287 if (reg_val & PHY_RD_ERR) {
288 *val = 0;
289 return -1;
290 }
291
292 *val = reg_val & 0xffff;
293 return 0;
294 }
295
296 /*
297 This function will write into PHY registers.
298 */
299 #if 0
300 static int amd8111e_write_phy(struct amd8111e_priv *lp, int phy_addr, int reg, u32 val)
301 {
302 void *mmio = lp->mmio;
303 unsigned int reg_val;
304 unsigned int retry = PHY_RW_RETRY;
305
306 reg_val = readl(mmio + PHY_ACCESS);
307 while (reg_val & PHY_CMD_ACTIVE)
308 reg_val = readl(mmio + PHY_ACCESS);
309
310 writel(PHY_WR_CMD | ((phy_addr & 0x1f) << 21) | ((reg & 0x1f) << 16) | val,
311 mmio + PHY_ACCESS);
312 do {
313 reg_val = readl(mmio + PHY_ACCESS);
314 udelay(30); /* It takes 30 us to read/write the data */
315 } while (--retry && (reg_val & PHY_CMD_ACTIVE));
316
317 if(reg_val & PHY_RD_ERR)
318 return -1;
319
320 return 0;
321 }
322 #endif
323
324 static void amd8111e_probe_ext_phy(struct amd8111e_priv *lp)
325 {
326 int i;
327
328 lp->ext_phy_id = 0;
329 lp->ext_phy_addr = 1;
330
331 for (i = 0x1e; i >= 0; i--) {
332 u32 id1, id2;
333
334 if (amd8111e_read_phy(lp, i, MII_PHYSID1, &id1))
335 continue;
336 if (amd8111e_read_phy(lp, i, MII_PHYSID2, &id2))
337 continue;
338 lp->ext_phy_id = (id1 << 16) | id2;
339 lp->ext_phy_addr = i;
340 break;
341 }
342
343 if (lp->ext_phy_id)
344 printf("Found MII PHY ID 0x%08x at address 0x%02x\n",
345 (unsigned int) lp->ext_phy_id, lp->ext_phy_addr);
346 else
347 printf("Couldn't detect MII PHY, assuming address 0x01\n");
348 }
349
350 static void amd8111e_disable_interrupt(struct amd8111e_priv *lp)
351 {
352 void *mmio = lp->mmio;
353 unsigned int int0;
354
355 writel(INTREN, mmio + CMD0);
356 writel(INTEN0_CLEAR, mmio + INTEN0);
357 int0 = readl(mmio + INT0);
358 writel(int0, mmio + INT0);
359 readl(mmio + INT0);
360 }
361
362 static void amd8111e_enable_interrupt(struct amd8111e_priv *lp)
363 {
364 void *mmio = lp->mmio;
365
366 writel(VAL3 | LCINTEN | VAL1 | TINTEN0 | VAL0 | RINTEN0, mmio + INTEN0);
367 writel(VAL0 | INTREN, mmio + CMD0);
368 readl(mmio + CMD0);
369 }
370
371 static void amd8111e_force_interrupt(struct amd8111e_priv *lp)
372 {
373 void *mmio = lp->mmio;
374
375 writel(VAL0 | UINTCMD, mmio + CMD0);
376 readl(mmio + CMD0);
377 }
378
379 static int amd8111e_get_mac_address(struct amd8111e_priv *lp)
380 {
381 struct nic *nic = lp->nic;
382 void *mmio = lp->mmio;
383 int i;
384
385 /* BIOS should have set mac address to PADR register,
386 * so we read PADR to get it.
387 */
388 for (i = 0; i < ETH_ALEN; i++)
389 nic->node_addr[i] = readb(mmio + PADR + i);
390
391 DBG ( "Ethernet addr: %s\n", eth_ntoa ( nic->node_addr ) );
392
393 return 0;
394 }
395
396 static int amd8111e_init_rx_ring(struct amd8111e_priv *lp)
397 {
398 int i;
399
400 lp->rx_idx = 0;
401
402 /* Initilaizing receive descriptors */
403 for (i = 0; i < NUM_RX_SLOTS; i++) {
404 lp->rx_ring[i].buf_phy_addr = cpu_to_le32(virt_to_bus(lp->rx_buf[i]));
405 lp->rx_ring[i].buf_len = cpu_to_le16(RX_BUF_LEN);
406 wmb();
407 lp->rx_ring[i].rx_flags = cpu_to_le16(OWN_BIT);
408 }
409
410 return 0;
411 }
412
413 static int amd8111e_init_tx_ring(struct amd8111e_priv *lp)
414 {
415 int i;
416
417 lp->tx_idx = 0;
418 lp->tx_consistent = 1;
419
420 /* Initializing transmit descriptors */
421 for (i = 0; i < NUM_TX_SLOTS; i++) {
422 lp->tx_ring[i].tx_flags = 0;
423 lp->tx_ring[i].buf_phy_addr = 0;
424 lp->tx_ring[i].buf_len = 0;
425 }
426
427 return 0;
428 }
429
430 static int amd8111e_wait_tx_ring(struct amd8111e_priv *lp, unsigned int index)
431 {
432 volatile u16 status;
433 int retry = TX_RETRY;
434
435 status = le16_to_cpu(lp->tx_ring[index].tx_flags);
436 while (--retry && (status & OWN_BIT)) {
437 mdelay(TX_PROCESS_TIME);
438 status = le16_to_cpu(lp->tx_ring[index].tx_flags);
439 }
440 if (status & OWN_BIT) {
441 printf("Error: tx slot %d timeout, stat = 0x%x\n", index, status);
442 amd8111e_restart(lp);
443 return -1;
444 }
445
446 return 0;
447 }
448
449 static void amd8111e_wait_link(struct amd8111e_priv *lp)
450 {
451 unsigned int status;
452 u32 reg_val;
453
454 do {
455 /* read phy to update STAT0 register */
456 amd8111e_read_phy(lp, lp->ext_phy_addr, MII_BMCR, &reg_val);
457 amd8111e_read_phy(lp, lp->ext_phy_addr, MII_BMSR, &reg_val);
458 amd8111e_read_phy(lp, lp->ext_phy_addr, MII_ADVERTISE, &reg_val);
459 amd8111e_read_phy(lp, lp->ext_phy_addr, MII_LPA, &reg_val);
460 status = readl(lp->mmio + STAT0);
461 } while (!(status & AUTONEG_COMPLETE) || !(status & LINK_STATS));
462 }
463
464 static void amd8111e_poll_link(struct amd8111e_priv *lp)
465 {
466 unsigned int status, speed;
467 u32 reg_val;
468
469 if (!lp->link) {
470 /* read phy to update STAT0 register */
471 amd8111e_read_phy(lp, lp->ext_phy_addr, MII_BMCR, &reg_val);
472 amd8111e_read_phy(lp, lp->ext_phy_addr, MII_BMSR, &reg_val);
473 amd8111e_read_phy(lp, lp->ext_phy_addr, MII_ADVERTISE, &reg_val);
474 amd8111e_read_phy(lp, lp->ext_phy_addr, MII_LPA, &reg_val);
475 status = readl(lp->mmio + STAT0);
476
477 if (status & LINK_STATS) {
478 lp->link = 1;
479 speed = (status & SPEED_MASK) >> 7;
480 if (speed == PHY_SPEED_100)
481 lp->speed = 1;
482 else
483 lp->speed = 0;
484 if (status & FULL_DPLX)
485 lp->duplex = 1;
486 else
487 lp->duplex = 0;
488
489 printf("Link is up: %s Mbps %s duplex\n",
490 lp->speed ? "100" : "10", lp->duplex ? "full" : "half");
491 }
492 } else {
493 status = readl(lp->mmio + STAT0);
494 if (!(status & LINK_STATS)) {
495 lp->link = 0;
496 printf("Link is down\n");
497 }
498 }
499 }
500
501 static void amd8111e_restart(struct amd8111e_priv *lp)
502 {
503 printf("\nStarting nic...\n");
504 amd8111e_disable_interrupt(lp);
505 amd8111e_init_hw_default(lp);
506 amd8111e_probe_ext_phy(lp);
507 amd8111e_get_mac_address(lp);
508 amd8111e_start(lp);
509
510 printf("Waiting link up...\n");
511 lp->link = 0;
512 amd8111e_wait_link(lp);
513 amd8111e_poll_link(lp);
514 }
515
516
517 /********************************************************
518 * Interface Functions *
519 ********************************************************/
520
521 static void amd8111e_transmit(struct nic *nic, const char *dst_addr,
522 unsigned int type, unsigned int size, const char *packet)
523 {
524 struct amd8111e_priv *lp = nic->priv_data;
525 struct eth_frame *frame;
526 unsigned int index;
527
528 /* check packet size */
529 if (size > TX_PKT_LEN_MAX) {
530 printf("amd8111e_transmit(): too large packet, drop\n");
531 return;
532 }
533
534 /* get tx slot */
535 index = lp->tx_idx;
536 if (amd8111e_wait_tx_ring(lp, index))
537 return;
538
539 /* fill frame */
540 frame = (struct eth_frame *)lp->tx_buf[index];
541 memset(frame->data, 0, TX_PKT_LEN_MAX);
542 memcpy(frame->dst_addr, dst_addr, ETH_ALEN);
543 memcpy(frame->src_addr, nic->node_addr, ETH_ALEN);
544 frame->type = htons(type);
545 memcpy(frame->data, packet, size);
546
547 /* start xmit */
548 lp->tx_ring[index].buf_len = cpu_to_le16(ETH_HLEN + size);
549 lp->tx_ring[index].buf_phy_addr = cpu_to_le32(virt_to_bus(frame));
550 wmb();
551 lp->tx_ring[index].tx_flags =
552 cpu_to_le16(OWN_BIT | STP_BIT | ENP_BIT | ADD_FCS_BIT | LTINT_BIT);
553 writel(VAL1 | TDMD0, lp->mmio + CMD0);
554 readl(lp->mmio + CMD0);
555
556 /* update slot pointer */
557 lp->tx_idx = (lp->tx_idx + 1) & TX_SLOTS_MASK;
558 }
559
560 static int amd8111e_poll(struct nic *nic, int retrieve)
561 {
562 /* return true if there's an ethernet packet ready to read */
563 /* nic->packet should contain data on return */
564 /* nic->packetlen should contain length of data */
565
566 struct amd8111e_priv *lp = nic->priv_data;
567 u16 status, pkt_len;
568 unsigned int index, pkt_ok;
569
570 amd8111e_poll_link(lp);
571
572 index = lp->rx_idx;
573 status = le16_to_cpu(lp->rx_ring[index].rx_flags);
574 pkt_len = le16_to_cpu(lp->rx_ring[index].msg_len) - 4; /* remove 4bytes FCS */
575
576 if (status & OWN_BIT)
577 return 0;
578
579 if (status & ERR_BIT)
580 pkt_ok = 0;
581 else if (!(status & STP_BIT))
582 pkt_ok = 0;
583 else if (!(status & ENP_BIT))
584 pkt_ok = 0;
585 else if (pkt_len < RX_PKT_LEN_MIN)
586 pkt_ok = 0;
587 else if (pkt_len > RX_PKT_LEN_MAX)
588 pkt_ok = 0;
589 else
590 pkt_ok = 1;
591
592 if (pkt_ok) {
593 if (!retrieve)
594 return 1;
595 nic->packetlen = pkt_len;
596 memcpy(nic->packet, lp->rx_buf[index], nic->packetlen);
597 }
598
599 lp->rx_ring[index].buf_phy_addr = cpu_to_le32(virt_to_bus(lp->rx_buf[index]));
600 lp->rx_ring[index].buf_len = cpu_to_le16(RX_BUF_LEN);
601 wmb();
602 lp->rx_ring[index].rx_flags = cpu_to_le16(OWN_BIT);
603 writel(VAL2 | RDMD0, lp->mmio + CMD0);
604 readl(lp->mmio + CMD0);
605
606 lp->rx_idx = (lp->rx_idx + 1) & RX_SLOTS_MASK;
607 return pkt_ok;
608 }
609
610 static void amd8111e_disable(struct nic *nic)
611 {
612 struct amd8111e_priv *lp = nic->priv_data;
613
614 /* disable interrupt */
615 amd8111e_disable_interrupt(lp);
616
617 /* stop chip */
618 amd8111e_init_hw_default(lp);
619
620 /* unmap mmio */
621 iounmap(lp->mmio);
622
623 /* update status */
624 lp->opened = 0;
625 }
626
627 static void amd8111e_irq(struct nic *nic, irq_action_t action)
628 {
629 struct amd8111e_priv *lp = nic->priv_data;
630
631 switch (action) {
632 case DISABLE:
633 amd8111e_disable_interrupt(lp);
634 break;
635 case ENABLE:
636 amd8111e_enable_interrupt(lp);
637 break;
638 case FORCE:
639 amd8111e_force_interrupt(lp);
640 break;
641 }
642 }
643
644 static struct nic_operations amd8111e_operations = {
645 .connect = dummy_connect,
646 .poll = amd8111e_poll,
647 .transmit = amd8111e_transmit,
648 .irq = amd8111e_irq,
649 };
650
651 static int amd8111e_probe(struct nic *nic, struct pci_device *pdev)
652 {
653 struct amd8111e_priv *lp = &amd8111e;
654 unsigned long mmio_start, mmio_len;
655
656 pci_fill_nic ( nic, pdev );
657
658 mmio_start = pci_bar_start(pdev, PCI_BASE_ADDRESS_0);
659 mmio_len = pci_bar_size(pdev, PCI_BASE_ADDRESS_0);
660
661 memset(lp, 0, sizeof(*lp));
662 lp->pdev = pdev;
663 lp->nic = nic;
664 lp->mmio = ioremap(mmio_start, mmio_len);
665 lp->opened = 1;
666 adjust_pci_device(pdev);
667
668 nic->priv_data = lp;
669
670 amd8111e_restart(lp);
671
672 nic->nic_op = &amd8111e_operations;
673 return 1;
674 }
675
676 static struct pci_device_id amd8111e_nics[] = {
677 PCI_ROM(0x1022, 0x7462, "amd8111e", "AMD8111E"),
678 };
679
680 PCI_DRIVER ( amd8111e_driver, amd8111e_nics, PCI_NO_CLASS );
681
682 DRIVER ( "AMD8111E", nic_driver, pci_driver, amd8111e_driver,
683 amd8111e_probe, amd8111e_disable );
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