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Warnings purge of drivers (continued)
[gpxe.git] / src / drivers / net / bnx2.c
blob8d4b0176afd504e9503dbebc1286a05a5f01bdf1
1 /* bnx2.c: Broadcom NX2 network driver.
2 *
3 * Copyright (c) 2004, 2005, 2006 Broadcom Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 *
9 * Written by: Michael Chan (mchan@broadcom.com)
10 *
11 * Etherboot port by Ryan Jackson (rjackson@lnxi.com), based on driver
12 * version 1.4.40 from linux 2.6.17
13 */
14
15
16 #include "etherboot.h"
17 #include "nic.h"
18 #include <gpxe/pci.h>
19 #include <gpxe/ethernet.h>
20 #include "timer.h"
21 #include "string.h"
22 #include "bnx2.h"
23 #include "bnx2_fw.h"
24
25 #if 0
26 /* Dummy defines for error handling */
27 #define EBUSY 1
28 #define ENODEV 2
29 #define EINVAL 3
30 #define ENOMEM 4
31 #define EIO 5
32 #endif
33
34 /* The bnx2 seems to be picky about the alignment of the receive buffers
35 * and possibly the status block.
36 */
37 static struct bss {
38 struct tx_bd tx_desc_ring[TX_DESC_CNT];
39 struct rx_bd rx_desc_ring[RX_DESC_CNT];
40 unsigned char rx_buf[RX_BUF_CNT][RX_BUF_SIZE];
41 struct status_block status_blk;
42 struct statistics_block stats_blk;
43 } bnx2_bss;
44
45 struct bnx2 bnx2;
46
47 static struct flash_spec flash_table[] =
48 {
49 /* Slow EEPROM */
50 {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400,
51 1, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
52 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
53 "EEPROM - slow"},
54 /* Expansion entry 0001 */
55 {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406,
56 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
57 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
58 "Entry 0001"},
59 /* Saifun SA25F010 (non-buffered flash) */
60 /* strap, cfg1, & write1 need updates */
61 {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406,
62 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
63 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2,
64 "Non-buffered flash (128kB)"},
65 /* Saifun SA25F020 (non-buffered flash) */
66 /* strap, cfg1, & write1 need updates */
67 {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406,
68 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
69 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4,
70 "Non-buffered flash (256kB)"},
71 /* Expansion entry 0100 */
72 {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406,
73 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
74 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
75 "Entry 0100"},
76 /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */
77 {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406,
78 0, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
79 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2,
80 "Entry 0101: ST M45PE10 (128kB non-bufferred)"},
81 /* Entry 0110: ST M45PE20 (non-buffered flash)*/
82 {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406,
83 0, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
84 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4,
85 "Entry 0110: ST M45PE20 (256kB non-bufferred)"},
86 /* Saifun SA25F005 (non-buffered flash) */
87 /* strap, cfg1, & write1 need updates */
88 {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406,
89 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
90 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE,
91 "Non-buffered flash (64kB)"},
92 /* Fast EEPROM */
93 {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400,
94 1, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
95 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
96 "EEPROM - fast"},
97 /* Expansion entry 1001 */
98 {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406,
99 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
100 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
101 "Entry 1001"},
102 /* Expansion entry 1010 */
103 {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406,
104 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
105 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
106 "Entry 1010"},
107 /* ATMEL AT45DB011B (buffered flash) */
108 {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400,
109 1, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
110 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE,
111 "Buffered flash (128kB)"},
112 /* Expansion entry 1100 */
113 {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406,
114 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
115 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
116 "Entry 1100"},
117 /* Expansion entry 1101 */
118 {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406,
119 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
120 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
121 "Entry 1101"},
122 /* Ateml Expansion entry 1110 */
123 {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400,
124 1, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
125 BUFFERED_FLASH_BYTE_ADDR_MASK, 0,
126 "Entry 1110 (Atmel)"},
127 /* ATMEL AT45DB021B (buffered flash) */
128 {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400,
129 1, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
130 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2,
131 "Buffered flash (256kB)"},
132 };
133
134 static u32
135 bnx2_reg_rd_ind(struct bnx2 *bp, u32 offset)
136 {
137 REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
138 return (REG_RD(bp, BNX2_PCICFG_REG_WINDOW));
139 }
140
141 static void
142 bnx2_reg_wr_ind(struct bnx2 *bp, u32 offset, u32 val)
143 {
144 REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
145 REG_WR(bp, BNX2_PCICFG_REG_WINDOW, val);
146 }
147
148 static void
149 bnx2_ctx_wr(struct bnx2 *bp, u32 cid_addr, u32 offset, u32 val)
150 {
151 offset += cid_addr;
152 REG_WR(bp, BNX2_CTX_DATA_ADR, offset);
153 REG_WR(bp, BNX2_CTX_DATA, val);
154 }
155
156 static int
157 bnx2_read_phy(struct bnx2 *bp, u32 reg, u32 *val)
158 {
159 u32 val1;
160 int i, ret;
161
162 if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
163 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
164 val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;
165
166 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
167 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
168
169 udelay(40);
170 }
171
172 val1 = (bp->phy_addr << 21) | (reg << 16) |
173 BNX2_EMAC_MDIO_COMM_COMMAND_READ | BNX2_EMAC_MDIO_COMM_DISEXT |
174 BNX2_EMAC_MDIO_COMM_START_BUSY;
175 REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
176
177 for (i = 0; i < 50; i++) {
178 udelay(10);
179
180 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
181 if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
182 udelay(5);
183
184 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
185 val1 &= BNX2_EMAC_MDIO_COMM_DATA;
186
187 break;
188 }
189 }
190
191 if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY) {
192 *val = 0x0;
193 ret = -EBUSY;
194 }
195 else {
196 *val = val1;
197 ret = 0;
198 }
199
200 if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
201 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
202 val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;
203
204 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
205 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
206
207 udelay(40);
208 }
209
210 return ret;
211 }
212
213 static int
214 bnx2_write_phy(struct bnx2 *bp, u32 reg, u32 val)
215 {
216 u32 val1;
217 int i, ret;
218
219 if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
220 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
221 val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;
222
223 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
224 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
225
226 udelay(40);
227 }
228
229 val1 = (bp->phy_addr << 21) | (reg << 16) | val |
230 BNX2_EMAC_MDIO_COMM_COMMAND_WRITE |
231 BNX2_EMAC_MDIO_COMM_START_BUSY | BNX2_EMAC_MDIO_COMM_DISEXT;
232 REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
233
234 for (i = 0; i < 50; i++) {
235 udelay(10);
236
237 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
238 if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
239 udelay(5);
240 break;
241 }
242 }
243
244 if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)
245 ret = -EBUSY;
246 else
247 ret = 0;
248
249 if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
250 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
251 val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;
252
253 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
254 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
255
256 udelay(40);
257 }
258
259 return ret;
260 }
261
262 static void
263 bnx2_disable_int(struct bnx2 *bp)
264 {
265 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
266 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
267 REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD);
268
269 }
270
271 static int
272 bnx2_alloc_mem(struct bnx2 *bp)
273 {
274 bp->tx_desc_ring = bnx2_bss.tx_desc_ring;
275 bp->tx_desc_mapping = virt_to_bus(bp->tx_desc_ring);
276
277 bp->rx_desc_ring = bnx2_bss.rx_desc_ring;
278 memset(bp->rx_desc_ring, 0, sizeof(struct rx_bd) * RX_DESC_CNT);
279 bp->rx_desc_mapping = virt_to_bus(bp->rx_desc_ring);
280
281 memset(&bnx2_bss.status_blk, 0, sizeof(struct status_block));
282 bp->status_blk = &bnx2_bss.status_blk;
283 bp->status_blk_mapping = virt_to_bus(&bnx2_bss.status_blk);
284
285 bp->stats_blk = &bnx2_bss.stats_blk;
286 memset(&bnx2_bss.stats_blk, 0, sizeof(struct statistics_block));
287 bp->stats_blk_mapping = virt_to_bus(&bnx2_bss.stats_blk);
288
289 return 0;
290 }
291
292 static void
293 bnx2_report_fw_link(struct bnx2 *bp)
294 {
295 u32 fw_link_status = 0;
296
297 if (bp->link_up) {
298 u32 bmsr;
299
300 switch (bp->line_speed) {
301 case SPEED_10:
302 if (bp->duplex == DUPLEX_HALF)
303 fw_link_status = BNX2_LINK_STATUS_10HALF;
304 else
305 fw_link_status = BNX2_LINK_STATUS_10FULL;
306 break;
307 case SPEED_100:
308 if (bp->duplex == DUPLEX_HALF)
309 fw_link_status = BNX2_LINK_STATUS_100HALF;
310 else
311 fw_link_status = BNX2_LINK_STATUS_100FULL;
312 break;
313 case SPEED_1000:
314 if (bp->duplex == DUPLEX_HALF)
315 fw_link_status = BNX2_LINK_STATUS_1000HALF;
316 else
317 fw_link_status = BNX2_LINK_STATUS_1000FULL;
318 break;
319 case SPEED_2500:
320 if (bp->duplex == DUPLEX_HALF)
321 fw_link_status = BNX2_LINK_STATUS_2500HALF;
322 else
323 fw_link_status = BNX2_LINK_STATUS_2500FULL;
324 break;
325 }
326
327 fw_link_status |= BNX2_LINK_STATUS_LINK_UP;
328
329 if (bp->autoneg) {
330 fw_link_status |= BNX2_LINK_STATUS_AN_ENABLED;
331
332 bnx2_read_phy(bp, MII_BMSR, &bmsr);
333 bnx2_read_phy(bp, MII_BMSR, &bmsr);
334
335 if (!(bmsr & BMSR_ANEGCOMPLETE) ||
336 bp->phy_flags & PHY_PARALLEL_DETECT_FLAG)
337 fw_link_status |= BNX2_LINK_STATUS_PARALLEL_DET;
338 else
339 fw_link_status |= BNX2_LINK_STATUS_AN_COMPLETE;
340 }
341 }
342 else
343 fw_link_status = BNX2_LINK_STATUS_LINK_DOWN;
344
345 REG_WR_IND(bp, bp->shmem_base + BNX2_LINK_STATUS, fw_link_status);
346 }
347
348 static void
349 bnx2_report_link(struct bnx2 *bp)
350 {
351 if (bp->link_up) {
352 printf("NIC Link is Up, ");
353
354 printf("%d Mbps ", bp->line_speed);
355
356 if (bp->duplex == DUPLEX_FULL)
357 printf("full duplex");
358 else
359 printf("half duplex");
360
361 if (bp->flow_ctrl) {
362 if (bp->flow_ctrl & FLOW_CTRL_RX) {
363 printf(", receive ");
364 if (bp->flow_ctrl & FLOW_CTRL_TX)
365 printf("& transmit ");
366 }
367 else {
368 printf(", transmit ");
369 }
370 printf("flow control ON");
371 }
372 printf("\n");
373 }
374 else {
375 printf("NIC Link is Down\n");
376 }
377
378 bnx2_report_fw_link(bp);
379 }
380
381 static void
382 bnx2_resolve_flow_ctrl(struct bnx2 *bp)
383 {
384 u32 local_adv, remote_adv;
385
386 bp->flow_ctrl = 0;
387 if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) !=
388 (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) {
389
390 if (bp->duplex == DUPLEX_FULL) {
391 bp->flow_ctrl = bp->req_flow_ctrl;
392 }
393 return;
394 }
395
396 if (bp->duplex != DUPLEX_FULL) {
397 return;
398 }
399
400 if ((bp->phy_flags & PHY_SERDES_FLAG) &&
401 (CHIP_NUM(bp) == CHIP_NUM_5708)) {
402 u32 val;
403
404 bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);
405 if (val & BCM5708S_1000X_STAT1_TX_PAUSE)
406 bp->flow_ctrl |= FLOW_CTRL_TX;
407 if (val & BCM5708S_1000X_STAT1_RX_PAUSE)
408 bp->flow_ctrl |= FLOW_CTRL_RX;
409 return;
410 }
411
412 bnx2_read_phy(bp, MII_ADVERTISE, &local_adv);
413 bnx2_read_phy(bp, MII_LPA, &remote_adv);
414
415 if (bp->phy_flags & PHY_SERDES_FLAG) {
416 u32 new_local_adv = 0;
417 u32 new_remote_adv = 0;
418
419 if (local_adv & ADVERTISE_1000XPAUSE)
420 new_local_adv |= ADVERTISE_PAUSE_CAP;
421 if (local_adv & ADVERTISE_1000XPSE_ASYM)
422 new_local_adv |= ADVERTISE_PAUSE_ASYM;
423 if (remote_adv & ADVERTISE_1000XPAUSE)
424 new_remote_adv |= ADVERTISE_PAUSE_CAP;
425 if (remote_adv & ADVERTISE_1000XPSE_ASYM)
426 new_remote_adv |= ADVERTISE_PAUSE_ASYM;
427
428 local_adv = new_local_adv;
429 remote_adv = new_remote_adv;
430 }
431
432 /* See Table 28B-3 of 802.3ab-1999 spec. */
433 if (local_adv & ADVERTISE_PAUSE_CAP) {
434 if(local_adv & ADVERTISE_PAUSE_ASYM) {
435 if (remote_adv & ADVERTISE_PAUSE_CAP) {
436 bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
437 }
438 else if (remote_adv & ADVERTISE_PAUSE_ASYM) {
439 bp->flow_ctrl = FLOW_CTRL_RX;
440 }
441 }
442 else {
443 if (remote_adv & ADVERTISE_PAUSE_CAP) {
444 bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
445 }
446 }
447 }
448 else if (local_adv & ADVERTISE_PAUSE_ASYM) {
449 if ((remote_adv & ADVERTISE_PAUSE_CAP) &&
450 (remote_adv & ADVERTISE_PAUSE_ASYM)) {
451
452 bp->flow_ctrl = FLOW_CTRL_TX;
453 }
454 }
455 }
456
457 static int
458 bnx2_5708s_linkup(struct bnx2 *bp)
459 {
460 u32 val;
461
462 bp->link_up = 1;
463 bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);
464 switch (val & BCM5708S_1000X_STAT1_SPEED_MASK) {
465 case BCM5708S_1000X_STAT1_SPEED_10:
466 bp->line_speed = SPEED_10;
467 break;
468 case BCM5708S_1000X_STAT1_SPEED_100:
469 bp->line_speed = SPEED_100;
470 break;
471 case BCM5708S_1000X_STAT1_SPEED_1G:
472 bp->line_speed = SPEED_1000;
473 break;
474 case BCM5708S_1000X_STAT1_SPEED_2G5:
475 bp->line_speed = SPEED_2500;
476 break;
477 }
478 if (val & BCM5708S_1000X_STAT1_FD)
479 bp->duplex = DUPLEX_FULL;
480 else
481 bp->duplex = DUPLEX_HALF;
482
483 return 0;
484 }
485
486 static int
487 bnx2_5706s_linkup(struct bnx2 *bp)
488 {
489 u32 bmcr, local_adv, remote_adv, common;
490
491 bp->link_up = 1;
492 bp->line_speed = SPEED_1000;
493
494 bnx2_read_phy(bp, MII_BMCR, &bmcr);
495 if (bmcr & BMCR_FULLDPLX) {
496 bp->duplex = DUPLEX_FULL;
497 }
498 else {
499 bp->duplex = DUPLEX_HALF;
500 }
501
502 if (!(bmcr & BMCR_ANENABLE)) {
503 return 0;
504 }
505
506 bnx2_read_phy(bp, MII_ADVERTISE, &local_adv);
507 bnx2_read_phy(bp, MII_LPA, &remote_adv);
508
509 common = local_adv & remote_adv;
510 if (common & (ADVERTISE_1000XHALF | ADVERTISE_1000XFULL)) {
511
512 if (common & ADVERTISE_1000XFULL) {
513 bp->duplex = DUPLEX_FULL;
514 }
515 else {
516 bp->duplex = DUPLEX_HALF;
517 }
518 }
519
520 return 0;
521 }
522
523 static int
524 bnx2_copper_linkup(struct bnx2 *bp)
525 {
526 u32 bmcr;
527
528 bnx2_read_phy(bp, MII_BMCR, &bmcr);
529 if (bmcr & BMCR_ANENABLE) {
530 u32 local_adv, remote_adv, common;
531
532 bnx2_read_phy(bp, MII_CTRL1000, &local_adv);
533 bnx2_read_phy(bp, MII_STAT1000, &remote_adv);
534
535 common = local_adv & (remote_adv >> 2);
536 if (common & ADVERTISE_1000FULL) {
537 bp->line_speed = SPEED_1000;
538 bp->duplex = DUPLEX_FULL;
539 }
540 else if (common & ADVERTISE_1000HALF) {
541 bp->line_speed = SPEED_1000;
542 bp->duplex = DUPLEX_HALF;
543 }
544 else {
545 bnx2_read_phy(bp, MII_ADVERTISE, &local_adv);
546 bnx2_read_phy(bp, MII_LPA, &remote_adv);
547
548 common = local_adv & remote_adv;
549 if (common & ADVERTISE_100FULL) {
550 bp->line_speed = SPEED_100;
551 bp->duplex = DUPLEX_FULL;
552 }
553 else if (common & ADVERTISE_100HALF) {
554 bp->line_speed = SPEED_100;
555 bp->duplex = DUPLEX_HALF;
556 }
557 else if (common & ADVERTISE_10FULL) {
558 bp->line_speed = SPEED_10;
559 bp->duplex = DUPLEX_FULL;
560 }
561 else if (common & ADVERTISE_10HALF) {
562 bp->line_speed = SPEED_10;
563 bp->duplex = DUPLEX_HALF;
564 }
565 else {
566 bp->line_speed = 0;
567 bp->link_up = 0;
568 }
569 }
570 }
571 else {
572 if (bmcr & BMCR_SPEED100) {
573 bp->line_speed = SPEED_100;
574 }
575 else {
576 bp->line_speed = SPEED_10;
577 }
578 if (bmcr & BMCR_FULLDPLX) {
579 bp->duplex = DUPLEX_FULL;
580 }
581 else {
582 bp->duplex = DUPLEX_HALF;
583 }
584 }
585
586 return 0;
587 }
588
589 static int
590 bnx2_set_mac_link(struct bnx2 *bp)
591 {
592 u32 val;
593
594 REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x2620);
595 if (bp->link_up && (bp->line_speed == SPEED_1000) &&
596 (bp->duplex == DUPLEX_HALF)) {
597 REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x26ff);
598 }
599
600 /* Configure the EMAC mode register. */
601 val = REG_RD(bp, BNX2_EMAC_MODE);
602
603 val &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX |
604 BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK |
605 BNX2_EMAC_MODE_25G);
606
607 if (bp->link_up) {
608 switch (bp->line_speed) {
609 case SPEED_10:
610 if (CHIP_NUM(bp) == CHIP_NUM_5708) {
611 val |= BNX2_EMAC_MODE_PORT_MII_10;
612 break;
613 }
614 /* fall through */
615 case SPEED_100:
616 val |= BNX2_EMAC_MODE_PORT_MII;
617 break;
618 case SPEED_2500:
619 val |= BNX2_EMAC_MODE_25G;
620 /* fall through */
621 case SPEED_1000:
622 val |= BNX2_EMAC_MODE_PORT_GMII;
623 break;
624 }
625 }
626 else {
627 val |= BNX2_EMAC_MODE_PORT_GMII;
628 }
629
630 /* Set the MAC to operate in the appropriate duplex mode. */
631 if (bp->duplex == DUPLEX_HALF)
632 val |= BNX2_EMAC_MODE_HALF_DUPLEX;
633 REG_WR(bp, BNX2_EMAC_MODE, val);
634
635 /* Enable/disable rx PAUSE. */
636 bp->rx_mode &= ~BNX2_EMAC_RX_MODE_FLOW_EN;
637
638 if (bp->flow_ctrl & FLOW_CTRL_RX)
639 bp->rx_mode |= BNX2_EMAC_RX_MODE_FLOW_EN;
640 REG_WR(bp, BNX2_EMAC_RX_MODE, bp->rx_mode);
641
642 /* Enable/disable tx PAUSE. */
643 val = REG_RD(bp, BNX2_EMAC_TX_MODE);
644 val &= ~BNX2_EMAC_TX_MODE_FLOW_EN;
645
646 if (bp->flow_ctrl & FLOW_CTRL_TX)
647 val |= BNX2_EMAC_TX_MODE_FLOW_EN;
648 REG_WR(bp, BNX2_EMAC_TX_MODE, val);
649
650 /* Acknowledge the interrupt. */
651 REG_WR(bp, BNX2_EMAC_STATUS, BNX2_EMAC_STATUS_LINK_CHANGE);
652
653 return 0;
654 }
655
656 static int
657 bnx2_set_link(struct bnx2 *bp)
658 {
659 u32 bmsr;
660 u8 link_up;
661
662 if (bp->loopback == MAC_LOOPBACK) {
663 bp->link_up = 1;
664 return 0;
665 }
666
667 link_up = bp->link_up;
668
669 bnx2_read_phy(bp, MII_BMSR, &bmsr);
670 bnx2_read_phy(bp, MII_BMSR, &bmsr);
671
672 if ((bp->phy_flags & PHY_SERDES_FLAG) &&
673 (CHIP_NUM(bp) == CHIP_NUM_5706)) {
674 u32 val;
675
676 val = REG_RD(bp, BNX2_EMAC_STATUS);
677 if (val & BNX2_EMAC_STATUS_LINK)
678 bmsr |= BMSR_LSTATUS;
679 else
680 bmsr &= ~BMSR_LSTATUS;
681 }
682
683 if (bmsr & BMSR_LSTATUS) {
684 bp->link_up = 1;
685
686 if (bp->phy_flags & PHY_SERDES_FLAG) {
687 if (CHIP_NUM(bp) == CHIP_NUM_5706)
688 bnx2_5706s_linkup(bp);
689 else if (CHIP_NUM(bp) == CHIP_NUM_5708)
690 bnx2_5708s_linkup(bp);
691 }
692 else {
693 bnx2_copper_linkup(bp);
694 }
695 bnx2_resolve_flow_ctrl(bp);
696 }
697 else {
698 if ((bp->phy_flags & PHY_SERDES_FLAG) &&
699 (bp->autoneg & AUTONEG_SPEED)) {
700
701 u32 bmcr;
702
703 bnx2_read_phy(bp, MII_BMCR, &bmcr);
704 if (!(bmcr & BMCR_ANENABLE)) {
705 bnx2_write_phy(bp, MII_BMCR, bmcr |
706 BMCR_ANENABLE);
707 }
708 }
709 bp->phy_flags &= ~PHY_PARALLEL_DETECT_FLAG;
710 bp->link_up = 0;
711 }
712
713 if (bp->link_up != link_up) {
714 bnx2_report_link(bp);
715 }
716
717 bnx2_set_mac_link(bp);
718
719 return 0;
720 }
721
722 static int
723 bnx2_reset_phy(struct bnx2 *bp)
724 {
725 int i;
726 u32 reg;
727
728 bnx2_write_phy(bp, MII_BMCR, BMCR_RESET);
729
730 #define PHY_RESET_MAX_WAIT 100
731 for (i = 0; i < PHY_RESET_MAX_WAIT; i++) {
732 udelay(10);
733
734 bnx2_read_phy(bp, MII_BMCR, &reg);
735 if (!(reg & BMCR_RESET)) {
736 udelay(20);
737 break;
738 }
739 }
740 if (i == PHY_RESET_MAX_WAIT) {
741 return -EBUSY;
742 }
743 return 0;
744 }
745
746 static u32
747 bnx2_phy_get_pause_adv(struct bnx2 *bp)
748 {
749 u32 adv = 0;
750
751 if ((bp->req_flow_ctrl & (FLOW_CTRL_RX | FLOW_CTRL_TX)) ==
752 (FLOW_CTRL_RX | FLOW_CTRL_TX)) {
753
754 if (bp->phy_flags & PHY_SERDES_FLAG) {
755 adv = ADVERTISE_1000XPAUSE;
756 }
757 else {
758 adv = ADVERTISE_PAUSE_CAP;
759 }
760 }
761 else if (bp->req_flow_ctrl & FLOW_CTRL_TX) {
762 if (bp->phy_flags & PHY_SERDES_FLAG) {
763 adv = ADVERTISE_1000XPSE_ASYM;
764 }
765 else {
766 adv = ADVERTISE_PAUSE_ASYM;
767 }
768 }
769 else if (bp->req_flow_ctrl & FLOW_CTRL_RX) {
770 if (bp->phy_flags & PHY_SERDES_FLAG) {
771 adv = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
772 }
773 else {
774 adv = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
775 }
776 }
777 return adv;
778 }
779
780 static int
781 bnx2_setup_serdes_phy(struct bnx2 *bp)
782 {
783 u32 adv, bmcr, up1;
784 u32 new_adv = 0;
785
786 if (!(bp->autoneg & AUTONEG_SPEED)) {
787 u32 new_bmcr;
788 int force_link_down = 0;
789
790 if (CHIP_NUM(bp) == CHIP_NUM_5708) {
791 bnx2_read_phy(bp, BCM5708S_UP1, &up1);
792 if (up1 & BCM5708S_UP1_2G5) {
793 up1 &= ~BCM5708S_UP1_2G5;
794 bnx2_write_phy(bp, BCM5708S_UP1, up1);
795 force_link_down = 1;
796 }
797 }
798
799 bnx2_read_phy(bp, MII_ADVERTISE, &adv);
800 adv &= ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF);
801
802 bnx2_read_phy(bp, MII_BMCR, &bmcr);
803 new_bmcr = bmcr & ~BMCR_ANENABLE;
804 new_bmcr |= BMCR_SPEED1000;
805 if (bp->req_duplex == DUPLEX_FULL) {
806 adv |= ADVERTISE_1000XFULL;
807 new_bmcr |= BMCR_FULLDPLX;
808 }
809 else {
810 adv |= ADVERTISE_1000XHALF;
811 new_bmcr &= ~BMCR_FULLDPLX;
812 }
813 if ((new_bmcr != bmcr) || (force_link_down)) {
814 /* Force a link down visible on the other side */
815 if (bp->link_up) {
816 bnx2_write_phy(bp, MII_ADVERTISE, adv &
817 ~(ADVERTISE_1000XFULL |
818 ADVERTISE_1000XHALF));
819 bnx2_write_phy(bp, MII_BMCR, bmcr |
820 BMCR_ANRESTART | BMCR_ANENABLE);
821
822 bp->link_up = 0;
823 bnx2_write_phy(bp, MII_BMCR, new_bmcr);
824 }
825 bnx2_write_phy(bp, MII_ADVERTISE, adv);
826 bnx2_write_phy(bp, MII_BMCR, new_bmcr);
827 }
828 return 0;
829 }
830
831 if (bp->phy_flags & PHY_2_5G_CAPABLE_FLAG) {
832 bnx2_read_phy(bp, BCM5708S_UP1, &up1);
833 up1 |= BCM5708S_UP1_2G5;
834 bnx2_write_phy(bp, BCM5708S_UP1, up1);
835 }
836
837 if (bp->advertising & ADVERTISED_1000baseT_Full)
838 new_adv |= ADVERTISE_1000XFULL;
839
840 new_adv |= bnx2_phy_get_pause_adv(bp);
841
842 bnx2_read_phy(bp, MII_ADVERTISE, &adv);
843 bnx2_read_phy(bp, MII_BMCR, &bmcr);
844
845 bp->serdes_an_pending = 0;
846 if ((adv != new_adv) || ((bmcr & BMCR_ANENABLE) == 0)) {
847 /* Force a link down visible on the other side */
848 if (bp->link_up) {
849 int i;
850
851 bnx2_write_phy(bp, MII_BMCR, BMCR_LOOPBACK);
852 for (i = 0; i < 110; i++) {
853 udelay(100);
854 }
855 }
856
857 bnx2_write_phy(bp, MII_ADVERTISE, new_adv);
858 bnx2_write_phy(bp, MII_BMCR, bmcr | BMCR_ANRESTART |
859 BMCR_ANENABLE);
860 #if 0
861 if (CHIP_NUM(bp) == CHIP_NUM_5706) {
862 /* Speed up link-up time when the link partner
863 * does not autonegotiate which is very common
864 * in blade servers. Some blade servers use
865 * IPMI for kerboard input and it's important
866 * to minimize link disruptions. Autoneg. involves
867 * exchanging base pages plus 3 next pages and
868 * normally completes in about 120 msec.
869 */
870 bp->current_interval = SERDES_AN_TIMEOUT;
871 bp->serdes_an_pending = 1;
872 mod_timer(&bp->timer, jiffies + bp->current_interval);
873 }
874 #endif
875 }
876
877 return 0;
878 }
879
880 #define ETHTOOL_ALL_FIBRE_SPEED \
881 (ADVERTISED_1000baseT_Full)
882
883 #define ETHTOOL_ALL_COPPER_SPEED \
884 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full | \
885 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full | \
886 ADVERTISED_1000baseT_Full)
887
888 #define PHY_ALL_10_100_SPEED (ADVERTISE_10HALF | ADVERTISE_10FULL | \
889 ADVERTISE_100HALF | ADVERTISE_100FULL | ADVERTISE_CSMA)
890
891 #define PHY_ALL_1000_SPEED (ADVERTISE_1000HALF | ADVERTISE_1000FULL)
892
893 static int
894 bnx2_setup_copper_phy(struct bnx2 *bp)
895 {
896 u32 bmcr;
897 u32 new_bmcr;
898
899 bnx2_read_phy(bp, MII_BMCR, &bmcr);
900
901 if (bp->autoneg & AUTONEG_SPEED) {
902 u32 adv_reg, adv1000_reg;
903 u32 new_adv_reg = 0;
904 u32 new_adv1000_reg = 0;
905
906 bnx2_read_phy(bp, MII_ADVERTISE, &adv_reg);
907 adv_reg &= (PHY_ALL_10_100_SPEED | ADVERTISE_PAUSE_CAP |
908 ADVERTISE_PAUSE_ASYM);
909
910 bnx2_read_phy(bp, MII_CTRL1000, &adv1000_reg);
911 adv1000_reg &= PHY_ALL_1000_SPEED;
912
913 if (bp->advertising & ADVERTISED_10baseT_Half)
914 new_adv_reg |= ADVERTISE_10HALF;
915 if (bp->advertising & ADVERTISED_10baseT_Full)
916 new_adv_reg |= ADVERTISE_10FULL;
917 if (bp->advertising & ADVERTISED_100baseT_Half)
918 new_adv_reg |= ADVERTISE_100HALF;
919 if (bp->advertising & ADVERTISED_100baseT_Full)
920 new_adv_reg |= ADVERTISE_100FULL;
921 if (bp->advertising & ADVERTISED_1000baseT_Full)
922 new_adv1000_reg |= ADVERTISE_1000FULL;
923
924 new_adv_reg |= ADVERTISE_CSMA;
925
926 new_adv_reg |= bnx2_phy_get_pause_adv(bp);
927
928 if ((adv1000_reg != new_adv1000_reg) ||
929 (adv_reg != new_adv_reg) ||
930 ((bmcr & BMCR_ANENABLE) == 0)) {
931
932 bnx2_write_phy(bp, MII_ADVERTISE, new_adv_reg);
933 bnx2_write_phy(bp, MII_CTRL1000, new_adv1000_reg);
934 bnx2_write_phy(bp, MII_BMCR, BMCR_ANRESTART |
935 BMCR_ANENABLE);
936 }
937 else if (bp->link_up) {
938 /* Flow ctrl may have changed from auto to forced */
939 /* or vice-versa. */
940
941 bnx2_resolve_flow_ctrl(bp);
942 bnx2_set_mac_link(bp);
943 }
944 return 0;
945 }
946
947 new_bmcr = 0;
948 if (bp->req_line_speed == SPEED_100) {
949 new_bmcr |= BMCR_SPEED100;
950 }
951 if (bp->req_duplex == DUPLEX_FULL) {
952 new_bmcr |= BMCR_FULLDPLX;
953 }
954 if (new_bmcr != bmcr) {
955 u32 bmsr;
956 int i = 0;
957
958 bnx2_read_phy(bp, MII_BMSR, &bmsr);
959 bnx2_read_phy(bp, MII_BMSR, &bmsr);
960
961 if (bmsr & BMSR_LSTATUS) {
962 /* Force link down */
963 bnx2_write_phy(bp, MII_BMCR, BMCR_LOOPBACK);
964 do {
965 udelay(100);
966 bnx2_read_phy(bp, MII_BMSR, &bmsr);
967 bnx2_read_phy(bp, MII_BMSR, &bmsr);
968 i++;
969 } while ((bmsr & BMSR_LSTATUS) && (i < 620));
970 }
971
972 bnx2_write_phy(bp, MII_BMCR, new_bmcr);
973
974 /* Normally, the new speed is setup after the link has
975 * gone down and up again. In some cases, link will not go
976 * down so we need to set up the new speed here.
977 */
978 if (bmsr & BMSR_LSTATUS) {
979 bp->line_speed = bp->req_line_speed;
980 bp->duplex = bp->req_duplex;
981 bnx2_resolve_flow_ctrl(bp);
982 bnx2_set_mac_link(bp);
983 }
984 }
985 return 0;
986 }
987
988 static int
989 bnx2_setup_phy(struct bnx2 *bp)
990 {
991 if (bp->loopback == MAC_LOOPBACK)
992 return 0;
993
994 if (bp->phy_flags & PHY_SERDES_FLAG) {
995 return (bnx2_setup_serdes_phy(bp));
996 }
997 else {
998 return (bnx2_setup_copper_phy(bp));
999 }
1000 }
1001
1002 static int
1003 bnx2_init_5708s_phy(struct bnx2 *bp)
1004 {
1005 u32 val;
1006
1007 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG3);
1008 bnx2_write_phy(bp, BCM5708S_DIG_3_0, BCM5708S_DIG_3_0_USE_IEEE);
1009 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
1010
1011 bnx2_read_phy(bp, BCM5708S_1000X_CTL1, &val);
1012 val |= BCM5708S_1000X_CTL1_FIBER_MODE | BCM5708S_1000X_CTL1_AUTODET_EN;
1013 bnx2_write_phy(bp, BCM5708S_1000X_CTL1, val);
1014
1015 bnx2_read_phy(bp, BCM5708S_1000X_CTL2, &val);
1016 val |= BCM5708S_1000X_CTL2_PLLEL_DET_EN;
1017 bnx2_write_phy(bp, BCM5708S_1000X_CTL2, val);
1018
1019 if (bp->phy_flags & PHY_2_5G_CAPABLE_FLAG) {
1020 bnx2_read_phy(bp, BCM5708S_UP1, &val);
1021 val |= BCM5708S_UP1_2G5;
1022 bnx2_write_phy(bp, BCM5708S_UP1, val);
1023 }
1024
1025 if ((CHIP_ID(bp) == CHIP_ID_5708_A0) ||
1026 (CHIP_ID(bp) == CHIP_ID_5708_B0) ||
1027 (CHIP_ID(bp) == CHIP_ID_5708_B1)) {
1028 /* increase tx signal amplitude */
1029 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
1030 BCM5708S_BLK_ADDR_TX_MISC);
1031 bnx2_read_phy(bp, BCM5708S_TX_ACTL1, &val);
1032 val &= ~BCM5708S_TX_ACTL1_DRIVER_VCM;
1033 bnx2_write_phy(bp, BCM5708S_TX_ACTL1, val);
1034 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
1035 }
1036
1037 val = REG_RD_IND(bp, bp->shmem_base + BNX2_PORT_HW_CFG_CONFIG) &
1038 BNX2_PORT_HW_CFG_CFG_TXCTL3_MASK;
1039
1040 if (val) {
1041 u32 is_backplane;
1042
1043 is_backplane = REG_RD_IND(bp, bp->shmem_base +
1044 BNX2_SHARED_HW_CFG_CONFIG);
1045 if (is_backplane & BNX2_SHARED_HW_CFG_PHY_BACKPLANE) {
1046 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
1047 BCM5708S_BLK_ADDR_TX_MISC);
1048 bnx2_write_phy(bp, BCM5708S_TX_ACTL3, val);
1049 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
1050 BCM5708S_BLK_ADDR_DIG);
1051 }
1052 }
1053 return 0;
1054 }
1055
1056 static int
1057 bnx2_init_5706s_phy(struct bnx2 *bp)
1058 {
1059 u32 val;
1060
1061 bp->phy_flags &= ~PHY_PARALLEL_DETECT_FLAG;
1062
1063 if (CHIP_NUM(bp) == CHIP_NUM_5706) {
1064 REG_WR(bp, BNX2_MISC_UNUSED0, 0x300);
1065 }
1066
1067
1068 bnx2_write_phy(bp, 0x18, 0x7);
1069 bnx2_read_phy(bp, 0x18, &val);
1070 bnx2_write_phy(bp, 0x18, val & ~0x4007);
1071
1072 bnx2_write_phy(bp, 0x1c, 0x6c00);
1073 bnx2_read_phy(bp, 0x1c, &val);
1074 bnx2_write_phy(bp, 0x1c, (val & 0x3fd) | 0xec00);
1075
1076 return 0;
1077 }
1078
1079 static int
1080 bnx2_init_copper_phy(struct bnx2 *bp)
1081 {
1082 u32 val;
1083
1084 bp->phy_flags |= PHY_CRC_FIX_FLAG;
1085
1086 if (bp->phy_flags & PHY_CRC_FIX_FLAG) {
1087 bnx2_write_phy(bp, 0x18, 0x0c00);
1088 bnx2_write_phy(bp, 0x17, 0x000a);
1089 bnx2_write_phy(bp, 0x15, 0x310b);
1090 bnx2_write_phy(bp, 0x17, 0x201f);
1091 bnx2_write_phy(bp, 0x15, 0x9506);
1092 bnx2_write_phy(bp, 0x17, 0x401f);
1093 bnx2_write_phy(bp, 0x15, 0x14e2);
1094 bnx2_write_phy(bp, 0x18, 0x0400);
1095 }
1096
1097 bnx2_write_phy(bp, 0x18, 0x7);
1098 bnx2_read_phy(bp, 0x18, &val);
1099 bnx2_write_phy(bp, 0x18, val & ~0x4007);
1100
1101 bnx2_read_phy(bp, 0x10, &val);
1102 bnx2_write_phy(bp, 0x10, val & ~0x1);
1103
1104 /* ethernet@wirespeed */
1105 bnx2_write_phy(bp, 0x18, 0x7007);
1106 bnx2_read_phy(bp, 0x18, &val);
1107 bnx2_write_phy(bp, 0x18, val | (1 << 15) | (1 << 4));
1108 return 0;
1109 }
1110
1111 static int
1112 bnx2_init_phy(struct bnx2 *bp)
1113 {
1114 u32 val;
1115 int rc = 0;
1116
1117 bp->phy_flags &= ~PHY_INT_MODE_MASK_FLAG;
1118 bp->phy_flags |= PHY_INT_MODE_LINK_READY_FLAG;
1119
1120 REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
1121
1122 bnx2_reset_phy(bp);
1123
1124 bnx2_read_phy(bp, MII_PHYSID1, &val);
1125 bp->phy_id = val << 16;
1126 bnx2_read_phy(bp, MII_PHYSID2, &val);
1127 bp->phy_id |= val & 0xffff;
1128
1129 if (bp->phy_flags & PHY_SERDES_FLAG) {
1130 if (CHIP_NUM(bp) == CHIP_NUM_5706)
1131 rc = bnx2_init_5706s_phy(bp);
1132 else if (CHIP_NUM(bp) == CHIP_NUM_5708)
1133 rc = bnx2_init_5708s_phy(bp);
1134 }
1135 else {
1136 rc = bnx2_init_copper_phy(bp);
1137 }
1138
1139 bnx2_setup_phy(bp);
1140
1141 return rc;
1142 }
1143
1144 static int
1145 bnx2_fw_sync(struct bnx2 *bp, u32 msg_data, int silent)
1146 {
1147 int i;
1148 u32 val;
1149
1150 bp->fw_wr_seq++;
1151 msg_data |= bp->fw_wr_seq;
1152
1153 REG_WR_IND(bp, bp->shmem_base + BNX2_DRV_MB, msg_data);
1154
1155 /* wait for an acknowledgement. */
1156 for (i = 0; i < (FW_ACK_TIME_OUT_MS / 50); i++) {
1157 mdelay(50);
1158
1159 val = REG_RD_IND(bp, bp->shmem_base + BNX2_FW_MB);
1160
1161 if ((val & BNX2_FW_MSG_ACK) == (msg_data & BNX2_DRV_MSG_SEQ))
1162 break;
1163 }
1164 if ((msg_data & BNX2_DRV_MSG_DATA) == BNX2_DRV_MSG_DATA_WAIT0)
1165 return 0;
1166
1167 /* If we timed out, inform the firmware that this is the case. */
1168 if ((val & BNX2_FW_MSG_ACK) != (msg_data & BNX2_DRV_MSG_SEQ)) {
1169 if (!silent)
1170 printf("fw sync timeout, reset code = %x\n", (unsigned int) msg_data);
1171
1172 msg_data &= ~BNX2_DRV_MSG_CODE;
1173 msg_data |= BNX2_DRV_MSG_CODE_FW_TIMEOUT;
1174
1175 REG_WR_IND(bp, bp->shmem_base + BNX2_DRV_MB, msg_data);
1176
1177 return -EBUSY;
1178 }
1179
1180 if ((val & BNX2_FW_MSG_STATUS_MASK) != BNX2_FW_MSG_STATUS_OK)
1181 return -EIO;
1182
1183 return 0;
1184 }
1185
1186 static void
1187 bnx2_init_context(struct bnx2 *bp)
1188 {
1189 u32 vcid;
1190
1191 vcid = 96;
1192 while (vcid) {
1193 u32 vcid_addr, pcid_addr, offset;
1194
1195 vcid--;
1196
1197 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
1198 u32 new_vcid;
1199
1200 vcid_addr = GET_PCID_ADDR(vcid);
1201 if (vcid & 0x8) {
1202 new_vcid = 0x60 + (vcid & 0xf0) + (vcid & 0x7);
1203 }
1204 else {
1205 new_vcid = vcid;
1206 }
1207 pcid_addr = GET_PCID_ADDR(new_vcid);
1208 }
1209 else {
1210 vcid_addr = GET_CID_ADDR(vcid);
1211 pcid_addr = vcid_addr;
1212 }
1213
1214 REG_WR(bp, BNX2_CTX_VIRT_ADDR, 0x00);
1215 REG_WR(bp, BNX2_CTX_PAGE_TBL, pcid_addr);
1216
1217 /* Zero out the context. */
1218 for (offset = 0; offset < PHY_CTX_SIZE; offset += 4) {
1219 CTX_WR(bp, 0x00, offset, 0);
1220 }
1221
1222 REG_WR(bp, BNX2_CTX_VIRT_ADDR, vcid_addr);
1223 REG_WR(bp, BNX2_CTX_PAGE_TBL, pcid_addr);
1224 }
1225 }
1226
1227 static int
1228 bnx2_alloc_bad_rbuf(struct bnx2 *bp)
1229 {
1230 u16 good_mbuf[512];
1231 u32 good_mbuf_cnt;
1232 u32 val;
1233
1234 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
1235 BNX2_MISC_ENABLE_SET_BITS_RX_MBUF_ENABLE);
1236
1237 good_mbuf_cnt = 0;
1238
1239 /* Allocate a bunch of mbufs and save the good ones in an array. */
1240 val = REG_RD_IND(bp, BNX2_RBUF_STATUS1);
1241 while (val & BNX2_RBUF_STATUS1_FREE_COUNT) {
1242 REG_WR_IND(bp, BNX2_RBUF_COMMAND, BNX2_RBUF_COMMAND_ALLOC_REQ);
1243
1244 val = REG_RD_IND(bp, BNX2_RBUF_FW_BUF_ALLOC);
1245
1246 val &= BNX2_RBUF_FW_BUF_ALLOC_VALUE;
1247
1248 /* The addresses with Bit 9 set are bad memory blocks. */
1249 if (!(val & (1 << 9))) {
1250 good_mbuf[good_mbuf_cnt] = (u16) val;
1251 good_mbuf_cnt++;
1252 }
1253
1254 val = REG_RD_IND(bp, BNX2_RBUF_STATUS1);
1255 }
1256
1257 /* Free the good ones back to the mbuf pool thus discarding
1258 * all the bad ones. */
1259 while (good_mbuf_cnt) {
1260 good_mbuf_cnt--;
1261
1262 val = good_mbuf[good_mbuf_cnt];
1263 val = (val << 9) | val | 1;
1264
1265 REG_WR_IND(bp, BNX2_RBUF_FW_BUF_FREE, val);
1266 }
1267 return 0;
1268 }
1269
1270 static void
1271 bnx2_set_mac_addr(struct bnx2 *bp)
1272 {
1273 u32 val;
1274 u8 *mac_addr = bp->nic->node_addr;
1275
1276 val = (mac_addr[0] << 8) | mac_addr[1];
1277
1278 REG_WR(bp, BNX2_EMAC_MAC_MATCH0, val);
1279
1280 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
1281 (mac_addr[4] << 8) | mac_addr[5];
1282
1283 REG_WR(bp, BNX2_EMAC_MAC_MATCH1, val);
1284 }
1285
1286 static void
1287 bnx2_set_rx_mode(struct nic *nic __unused)
1288 {
1289 struct bnx2 *bp = &bnx2;
1290 u32 rx_mode, sort_mode;
1291 int i;
1292
1293 rx_mode = bp->rx_mode & ~(BNX2_EMAC_RX_MODE_PROMISCUOUS |
1294 BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG);
1295 sort_mode = 1 | BNX2_RPM_SORT_USER0_BC_EN;
1296
1297 if (!(bp->flags & ASF_ENABLE_FLAG)) {
1298 rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG;
1299 }
1300
1301 /* Accept all multicasts */
1302 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
1303 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
1304 0xffffffff);
1305 }
1306 sort_mode |= BNX2_RPM_SORT_USER0_MC_EN;
1307
1308 if (rx_mode != bp->rx_mode) {
1309 bp->rx_mode = rx_mode;
1310 REG_WR(bp, BNX2_EMAC_RX_MODE, rx_mode);
1311 }
1312
1313 REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
1314 REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode);
1315 REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode | BNX2_RPM_SORT_USER0_ENA);
1316 }
1317
1318 static void
1319 load_rv2p_fw(struct bnx2 *bp, u32 *rv2p_code, u32 rv2p_code_len, u32 rv2p_proc)
1320 {
1321 unsigned int i;
1322 u32 val;
1323
1324
1325 for (i = 0; i < rv2p_code_len; i += 8) {
1326 REG_WR(bp, BNX2_RV2P_INSTR_HIGH, *rv2p_code);
1327 rv2p_code++;
1328 REG_WR(bp, BNX2_RV2P_INSTR_LOW, *rv2p_code);
1329 rv2p_code++;
1330
1331 if (rv2p_proc == RV2P_PROC1) {
1332 val = (i / 8) | BNX2_RV2P_PROC1_ADDR_CMD_RDWR;
1333 REG_WR(bp, BNX2_RV2P_PROC1_ADDR_CMD, val);
1334 }
1335 else {
1336 val = (i / 8) | BNX2_RV2P_PROC2_ADDR_CMD_RDWR;
1337 REG_WR(bp, BNX2_RV2P_PROC2_ADDR_CMD, val);
1338 }
1339 }
1340
1341 /* Reset the processor, un-stall is done later. */
1342 if (rv2p_proc == RV2P_PROC1) {
1343 REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC1_RESET);
1344 }
1345 else {
1346 REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC2_RESET);
1347 }
1348 }
1349
1350 static void
1351 load_cpu_fw(struct bnx2 *bp, struct cpu_reg *cpu_reg, struct fw_info *fw)
1352 {
1353 u32 offset;
1354 u32 val;
1355
1356 /* Halt the CPU. */
1357 val = REG_RD_IND(bp, cpu_reg->mode);
1358 val |= cpu_reg->mode_value_halt;
1359 REG_WR_IND(bp, cpu_reg->mode, val);
1360 REG_WR_IND(bp, cpu_reg->state, cpu_reg->state_value_clear);
1361
1362 /* Load the Text area. */
1363 offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base);
1364 if (fw->text) {
1365 unsigned int j;
1366
1367 for (j = 0; j < (fw->text_len / 4); j++, offset += 4) {
1368 REG_WR_IND(bp, offset, fw->text[j]);
1369 }
1370 }
1371
1372 /* Load the Data area. */
1373 offset = cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base);
1374 if (fw->data) {
1375 unsigned int j;
1376
1377 for (j = 0; j < (fw->data_len / 4); j++, offset += 4) {
1378 REG_WR_IND(bp, offset, fw->data[j]);
1379 }
1380 }
1381
1382 /* Load the SBSS area. */
1383 offset = cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base);
1384 if (fw->sbss) {
1385 unsigned int j;
1386
1387 for (j = 0; j < (fw->sbss_len / 4); j++, offset += 4) {
1388 REG_WR_IND(bp, offset, fw->sbss[j]);
1389 }
1390 }
1391
1392 /* Load the BSS area. */
1393 offset = cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base);
1394 if (fw->bss) {
1395 unsigned int j;
1396
1397 for (j = 0; j < (fw->bss_len/4); j++, offset += 4) {
1398 REG_WR_IND(bp, offset, fw->bss[j]);
1399 }
1400 }
1401
1402 /* Load the Read-Only area. */
1403 offset = cpu_reg->spad_base +
1404 (fw->rodata_addr - cpu_reg->mips_view_base);
1405 if (fw->rodata) {
1406 unsigned int j;
1407
1408 for (j = 0; j < (fw->rodata_len / 4); j++, offset += 4) {
1409 REG_WR_IND(bp, offset, fw->rodata[j]);
1410 }
1411 }
1412
1413 /* Clear the pre-fetch instruction. */
1414 REG_WR_IND(bp, cpu_reg->inst, 0);
1415 REG_WR_IND(bp, cpu_reg->pc, fw->start_addr);
1416
1417 /* Start the CPU. */
1418 val = REG_RD_IND(bp, cpu_reg->mode);
1419 val &= ~cpu_reg->mode_value_halt;
1420 REG_WR_IND(bp, cpu_reg->state, cpu_reg->state_value_clear);
1421 REG_WR_IND(bp, cpu_reg->mode, val);
1422 }
1423
1424 static void
1425 bnx2_init_cpus(struct bnx2 *bp)
1426 {
1427 struct cpu_reg cpu_reg;
1428 struct fw_info fw;
1429
1430 /* Unfortunately, it looks like we need to load the firmware
1431 * before the card will work properly. That means this driver
1432 * will be huge by Etherboot standards (approx. 50K compressed).
1433 */
1434
1435 /* Initialize the RV2P processor. */
1436 load_rv2p_fw(bp, bnx2_rv2p_proc1, sizeof(bnx2_rv2p_proc1), RV2P_PROC1);
1437 load_rv2p_fw(bp, bnx2_rv2p_proc2, sizeof(bnx2_rv2p_proc2), RV2P_PROC2);
1438
1439 /* Initialize the RX Processor. */
1440 cpu_reg.mode = BNX2_RXP_CPU_MODE;
1441 cpu_reg.mode_value_halt = BNX2_RXP_CPU_MODE_SOFT_HALT;
1442 cpu_reg.mode_value_sstep = BNX2_RXP_CPU_MODE_STEP_ENA;
1443 cpu_reg.state = BNX2_RXP_CPU_STATE;
1444 cpu_reg.state_value_clear = 0xffffff;
1445 cpu_reg.gpr0 = BNX2_RXP_CPU_REG_FILE;
1446 cpu_reg.evmask = BNX2_RXP_CPU_EVENT_MASK;
1447 cpu_reg.pc = BNX2_RXP_CPU_PROGRAM_COUNTER;
1448 cpu_reg.inst = BNX2_RXP_CPU_INSTRUCTION;
1449 cpu_reg.bp = BNX2_RXP_CPU_HW_BREAKPOINT;
1450 cpu_reg.spad_base = BNX2_RXP_SCRATCH;
1451 cpu_reg.mips_view_base = 0x8000000;
1452
1453 fw.ver_major = bnx2_RXP_b06FwReleaseMajor;
1454 fw.ver_minor = bnx2_RXP_b06FwReleaseMinor;
1455 fw.ver_fix = bnx2_RXP_b06FwReleaseFix;
1456 fw.start_addr = bnx2_RXP_b06FwStartAddr;
1457
1458 fw.text_addr = bnx2_RXP_b06FwTextAddr;
1459 fw.text_len = bnx2_RXP_b06FwTextLen;
1460 fw.text_index = 0;
1461 fw.text = bnx2_RXP_b06FwText;
1462
1463 fw.data_addr = bnx2_RXP_b06FwDataAddr;
1464 fw.data_len = bnx2_RXP_b06FwDataLen;
1465 fw.data_index = 0;
1466 fw.data = bnx2_RXP_b06FwData;
1467
1468 fw.sbss_addr = bnx2_RXP_b06FwSbssAddr;
1469 fw.sbss_len = bnx2_RXP_b06FwSbssLen;
1470 fw.sbss_index = 0;
1471 fw.sbss = bnx2_RXP_b06FwSbss;
1472
1473 fw.bss_addr = bnx2_RXP_b06FwBssAddr;
1474 fw.bss_len = bnx2_RXP_b06FwBssLen;
1475 fw.bss_index = 0;
1476 fw.bss = bnx2_RXP_b06FwBss;
1477
1478 fw.rodata_addr = bnx2_RXP_b06FwRodataAddr;
1479 fw.rodata_len = bnx2_RXP_b06FwRodataLen;
1480 fw.rodata_index = 0;
1481 fw.rodata = bnx2_RXP_b06FwRodata;
1482
1483 load_cpu_fw(bp, &cpu_reg, &fw);
1484
1485 /* Initialize the TX Processor. */
1486 cpu_reg.mode = BNX2_TXP_CPU_MODE;
1487 cpu_reg.mode_value_halt = BNX2_TXP_CPU_MODE_SOFT_HALT;
1488 cpu_reg.mode_value_sstep = BNX2_TXP_CPU_MODE_STEP_ENA;
1489 cpu_reg.state = BNX2_TXP_CPU_STATE;
1490 cpu_reg.state_value_clear = 0xffffff;
1491 cpu_reg.gpr0 = BNX2_TXP_CPU_REG_FILE;
1492 cpu_reg.evmask = BNX2_TXP_CPU_EVENT_MASK;
1493 cpu_reg.pc = BNX2_TXP_CPU_PROGRAM_COUNTER;
1494 cpu_reg.inst = BNX2_TXP_CPU_INSTRUCTION;
1495 cpu_reg.bp = BNX2_TXP_CPU_HW_BREAKPOINT;
1496 cpu_reg.spad_base = BNX2_TXP_SCRATCH;
1497 cpu_reg.mips_view_base = 0x8000000;
1498
1499 fw.ver_major = bnx2_TXP_b06FwReleaseMajor;
1500 fw.ver_minor = bnx2_TXP_b06FwReleaseMinor;
1501 fw.ver_fix = bnx2_TXP_b06FwReleaseFix;
1502 fw.start_addr = bnx2_TXP_b06FwStartAddr;
1503
1504 fw.text_addr = bnx2_TXP_b06FwTextAddr;
1505 fw.text_len = bnx2_TXP_b06FwTextLen;
1506 fw.text_index = 0;
1507 fw.text = bnx2_TXP_b06FwText;
1508
1509 fw.data_addr = bnx2_TXP_b06FwDataAddr;
1510 fw.data_len = bnx2_TXP_b06FwDataLen;
1511 fw.data_index = 0;
1512 fw.data = bnx2_TXP_b06FwData;
1513
1514 fw.sbss_addr = bnx2_TXP_b06FwSbssAddr;
1515 fw.sbss_len = bnx2_TXP_b06FwSbssLen;
1516 fw.sbss_index = 0;
1517 fw.sbss = bnx2_TXP_b06FwSbss;
1518
1519 fw.bss_addr = bnx2_TXP_b06FwBssAddr;
1520 fw.bss_len = bnx2_TXP_b06FwBssLen;
1521 fw.bss_index = 0;
1522 fw.bss = bnx2_TXP_b06FwBss;
1523
1524 fw.rodata_addr = bnx2_TXP_b06FwRodataAddr;
1525 fw.rodata_len = bnx2_TXP_b06FwRodataLen;
1526 fw.rodata_index = 0;
1527 fw.rodata = bnx2_TXP_b06FwRodata;
1528
1529 load_cpu_fw(bp, &cpu_reg, &fw);
1530
1531 /* Initialize the TX Patch-up Processor. */
1532 cpu_reg.mode = BNX2_TPAT_CPU_MODE;
1533 cpu_reg.mode_value_halt = BNX2_TPAT_CPU_MODE_SOFT_HALT;
1534 cpu_reg.mode_value_sstep = BNX2_TPAT_CPU_MODE_STEP_ENA;
1535 cpu_reg.state = BNX2_TPAT_CPU_STATE;
1536 cpu_reg.state_value_clear = 0xffffff;
1537 cpu_reg.gpr0 = BNX2_TPAT_CPU_REG_FILE;
1538 cpu_reg.evmask = BNX2_TPAT_CPU_EVENT_MASK;
1539 cpu_reg.pc = BNX2_TPAT_CPU_PROGRAM_COUNTER;
1540 cpu_reg.inst = BNX2_TPAT_CPU_INSTRUCTION;
1541 cpu_reg.bp = BNX2_TPAT_CPU_HW_BREAKPOINT;
1542 cpu_reg.spad_base = BNX2_TPAT_SCRATCH;
1543 cpu_reg.mips_view_base = 0x8000000;
1544
1545 fw.ver_major = bnx2_TPAT_b06FwReleaseMajor;
1546 fw.ver_minor = bnx2_TPAT_b06FwReleaseMinor;
1547 fw.ver_fix = bnx2_TPAT_b06FwReleaseFix;
1548 fw.start_addr = bnx2_TPAT_b06FwStartAddr;
1549
1550 fw.text_addr = bnx2_TPAT_b06FwTextAddr;
1551 fw.text_len = bnx2_TPAT_b06FwTextLen;
1552 fw.text_index = 0;
1553 fw.text = bnx2_TPAT_b06FwText;
1554
1555 fw.data_addr = bnx2_TPAT_b06FwDataAddr;
1556 fw.data_len = bnx2_TPAT_b06FwDataLen;
1557 fw.data_index = 0;
1558 fw.data = bnx2_TPAT_b06FwData;
1559
1560 fw.sbss_addr = bnx2_TPAT_b06FwSbssAddr;
1561 fw.sbss_len = bnx2_TPAT_b06FwSbssLen;
1562 fw.sbss_index = 0;
1563 fw.sbss = bnx2_TPAT_b06FwSbss;
1564
1565 fw.bss_addr = bnx2_TPAT_b06FwBssAddr;
1566 fw.bss_len = bnx2_TPAT_b06FwBssLen;
1567 fw.bss_index = 0;
1568 fw.bss = bnx2_TPAT_b06FwBss;
1569
1570 fw.rodata_addr = bnx2_TPAT_b06FwRodataAddr;
1571 fw.rodata_len = bnx2_TPAT_b06FwRodataLen;
1572 fw.rodata_index = 0;
1573 fw.rodata = bnx2_TPAT_b06FwRodata;
1574
1575 load_cpu_fw(bp, &cpu_reg, &fw);
1576
1577 /* Initialize the Completion Processor. */
1578 cpu_reg.mode = BNX2_COM_CPU_MODE;
1579 cpu_reg.mode_value_halt = BNX2_COM_CPU_MODE_SOFT_HALT;
1580 cpu_reg.mode_value_sstep = BNX2_COM_CPU_MODE_STEP_ENA;
1581 cpu_reg.state = BNX2_COM_CPU_STATE;
1582 cpu_reg.state_value_clear = 0xffffff;
1583 cpu_reg.gpr0 = BNX2_COM_CPU_REG_FILE;
1584 cpu_reg.evmask = BNX2_COM_CPU_EVENT_MASK;
1585 cpu_reg.pc = BNX2_COM_CPU_PROGRAM_COUNTER;
1586 cpu_reg.inst = BNX2_COM_CPU_INSTRUCTION;
1587 cpu_reg.bp = BNX2_COM_CPU_HW_BREAKPOINT;
1588 cpu_reg.spad_base = BNX2_COM_SCRATCH;
1589 cpu_reg.mips_view_base = 0x8000000;
1590
1591 fw.ver_major = bnx2_COM_b06FwReleaseMajor;
1592 fw.ver_minor = bnx2_COM_b06FwReleaseMinor;
1593 fw.ver_fix = bnx2_COM_b06FwReleaseFix;
1594 fw.start_addr = bnx2_COM_b06FwStartAddr;
1595
1596 fw.text_addr = bnx2_COM_b06FwTextAddr;
1597 fw.text_len = bnx2_COM_b06FwTextLen;
1598 fw.text_index = 0;
1599 fw.text = bnx2_COM_b06FwText;
1600
1601 fw.data_addr = bnx2_COM_b06FwDataAddr;
1602 fw.data_len = bnx2_COM_b06FwDataLen;
1603 fw.data_index = 0;
1604 fw.data = bnx2_COM_b06FwData;
1605
1606 fw.sbss_addr = bnx2_COM_b06FwSbssAddr;
1607 fw.sbss_len = bnx2_COM_b06FwSbssLen;
1608 fw.sbss_index = 0;
1609 fw.sbss = bnx2_COM_b06FwSbss;
1610
1611 fw.bss_addr = bnx2_COM_b06FwBssAddr;
1612 fw.bss_len = bnx2_COM_b06FwBssLen;
1613 fw.bss_index = 0;
1614 fw.bss = bnx2_COM_b06FwBss;
1615
1616 fw.rodata_addr = bnx2_COM_b06FwRodataAddr;
1617 fw.rodata_len = bnx2_COM_b06FwRodataLen;
1618 fw.rodata_index = 0;
1619 fw.rodata = bnx2_COM_b06FwRodata;
1620
1621 load_cpu_fw(bp, &cpu_reg, &fw);
1622
1623 }
1624
1625 static int
1626 bnx2_set_power_state_0(struct bnx2 *bp)
1627 {
1628 u16 pmcsr;
1629 u32 val;
1630
1631 pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &pmcsr);
1632
1633 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
1634 (pmcsr & ~PCI_PM_CTRL_STATE_MASK) |
1635 PCI_PM_CTRL_PME_STATUS);
1636
1637 if (pmcsr & PCI_PM_CTRL_STATE_MASK)
1638 /* delay required during transition out of D3hot */
1639 mdelay(20);
1640
1641 val = REG_RD(bp, BNX2_EMAC_MODE);
1642 val |= BNX2_EMAC_MODE_MPKT_RCVD | BNX2_EMAC_MODE_ACPI_RCVD;
1643 val &= ~BNX2_EMAC_MODE_MPKT;
1644 REG_WR(bp, BNX2_EMAC_MODE, val);
1645
1646 val = REG_RD(bp, BNX2_RPM_CONFIG);
1647 val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
1648 REG_WR(bp, BNX2_RPM_CONFIG, val);
1649
1650 return 0;
1651 }
1652
1653 static void
1654 bnx2_enable_nvram_access(struct bnx2 *bp)
1655 {
1656 u32 val;
1657
1658 val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE);
1659 /* Enable both bits, even on read. */
1660 REG_WR(bp, BNX2_NVM_ACCESS_ENABLE,
1661 val | BNX2_NVM_ACCESS_ENABLE_EN | BNX2_NVM_ACCESS_ENABLE_WR_EN);
1662 }
1663
1664 static void
1665 bnx2_disable_nvram_access(struct bnx2 *bp)
1666 {
1667 u32 val;
1668
1669 val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE);
1670 /* Disable both bits, even after read. */
1671 REG_WR(bp, BNX2_NVM_ACCESS_ENABLE,
1672 val & ~(BNX2_NVM_ACCESS_ENABLE_EN |
1673 BNX2_NVM_ACCESS_ENABLE_WR_EN));
1674 }
1675
1676 static int
1677 bnx2_init_nvram(struct bnx2 *bp)
1678 {
1679 u32 val;
1680 int j, entry_count, rc;
1681 struct flash_spec *flash;
1682
1683 /* Determine the selected interface. */
1684 val = REG_RD(bp, BNX2_NVM_CFG1);
1685
1686 entry_count = sizeof(flash_table) / sizeof(struct flash_spec);
1687
1688 rc = 0;
1689 if (val & 0x40000000) {
1690 /* Flash interface has been reconfigured */
1691 for (j = 0, flash = &flash_table[0]; j < entry_count;
1692 j++, flash++) {
1693 if ((val & FLASH_BACKUP_STRAP_MASK) ==
1694 (flash->config1 & FLASH_BACKUP_STRAP_MASK)) {
1695 bp->flash_info = flash;
1696 break;
1697 }
1698 }
1699 }
1700 else {
1701 u32 mask;
1702 /* Not yet been reconfigured */
1703
1704 if (val & (1 << 23))
1705 mask = FLASH_BACKUP_STRAP_MASK;
1706 else
1707 mask = FLASH_STRAP_MASK;
1708
1709 for (j = 0, flash = &flash_table[0]; j < entry_count;
1710 j++, flash++) {
1711
1712 if ((val & mask) == (flash->strapping & mask)) {
1713 bp->flash_info = flash;
1714
1715 /* Enable access to flash interface */
1716 bnx2_enable_nvram_access(bp);
1717
1718 /* Reconfigure the flash interface */
1719 REG_WR(bp, BNX2_NVM_CFG1, flash->config1);
1720 REG_WR(bp, BNX2_NVM_CFG2, flash->config2);
1721 REG_WR(bp, BNX2_NVM_CFG3, flash->config3);
1722 REG_WR(bp, BNX2_NVM_WRITE1, flash->write1);
1723
1724 /* Disable access to flash interface */
1725 bnx2_disable_nvram_access(bp);
1726
1727 break;
1728 }
1729 }
1730 } /* if (val & 0x40000000) */
1731
1732 if (j == entry_count) {
1733 bp->flash_info = NULL;
1734 printf("Unknown flash/EEPROM type.\n");
1735 return -ENODEV;
1736 }
1737
1738 val = REG_RD_IND(bp, bp->shmem_base + BNX2_SHARED_HW_CFG_CONFIG2);
1739 val &= BNX2_SHARED_HW_CFG2_NVM_SIZE_MASK;
1740 if (val) {
1741 bp->flash_size = val;
1742 }
1743 else {
1744 bp->flash_size = bp->flash_info->total_size;
1745 }
1746
1747 return rc;
1748 }
1749
1750 static int
1751 bnx2_reset_chip(struct bnx2 *bp, u32 reset_code)
1752 {
1753 u32 val;
1754 int i, rc = 0;
1755
1756 /* Wait for the current PCI transaction to complete before
1757 * issuing a reset. */
1758 REG_WR(bp, BNX2_MISC_ENABLE_CLR_BITS,
1759 BNX2_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE |
1760 BNX2_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE |
1761 BNX2_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE |
1762 BNX2_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE);
1763 val = REG_RD(bp, BNX2_MISC_ENABLE_CLR_BITS);
1764 udelay(5);
1765
1766
1767 /* Wait for the firmware to tell us it is ok to issue a reset. */
1768 bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT0 | reset_code, 1);
1769
1770 /* Deposit a driver reset signature so the firmware knows that
1771 * this is a soft reset. */
1772 REG_WR_IND(bp, bp->shmem_base + BNX2_DRV_RESET_SIGNATURE,
1773 BNX2_DRV_RESET_SIGNATURE_MAGIC);
1774
1775 /* Do a dummy read to force the chip to complete all current transaction
1776 * before we issue a reset. */
1777 val = REG_RD(bp, BNX2_MISC_ID);
1778
1779 val = BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
1780 BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
1781 BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
1782
1783 /* Chip reset. */
1784 REG_WR(bp, BNX2_PCICFG_MISC_CONFIG, val);
1785
1786 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
1787 (CHIP_ID(bp) == CHIP_ID_5706_A1))
1788 mdelay(15);
1789
1790 /* Reset takes approximate 30 usec */
1791 for (i = 0; i < 10; i++) {
1792 val = REG_RD(bp, BNX2_PCICFG_MISC_CONFIG);
1793 if ((val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
1794 BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0) {
1795 break;
1796 }
1797 udelay(10);
1798 }
1799
1800 if (val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
1801 BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) {
1802 printf("Chip reset did not complete\n");
1803 return -EBUSY;
1804 }
1805
1806 /* Make sure byte swapping is properly configured. */
1807 val = REG_RD(bp, BNX2_PCI_SWAP_DIAG0);
1808 if (val != 0x01020304) {
1809 printf("Chip not in correct endian mode\n");
1810 return -ENODEV;
1811 }
1812
1813 /* Wait for the firmware to finish its initialization. */
1814 rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT1 | reset_code, 0);
1815 if (rc) {
1816 return rc;
1817 }
1818
1819 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
1820 /* Adjust the voltage regular to two steps lower. The default
1821 * of this register is 0x0000000e. */
1822 REG_WR(bp, BNX2_MISC_VREG_CONTROL, 0x000000fa);
1823
1824 /* Remove bad rbuf memory from the free pool. */
1825 rc = bnx2_alloc_bad_rbuf(bp);
1826 }
1827
1828 return rc;
1829 }
1830
1831 static void
1832 bnx2_disable(struct nic *nic __unused)
1833 {
1834 struct bnx2* bp = &bnx2;
1835
1836 if (bp->regview) {
1837 bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_UNLOAD);
1838 iounmap(bp->regview);
1839 }
1840 }
1841
1842 static int
1843 bnx2_init_chip(struct bnx2 *bp)
1844 {
1845 u32 val;
1846 int rc;
1847
1848 /* Make sure the interrupt is not active. */
1849 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
1850
1851 val = BNX2_DMA_CONFIG_DATA_BYTE_SWAP |
1852 BNX2_DMA_CONFIG_DATA_WORD_SWAP |
1853 #if __BYTE_ORDER == __BIG_ENDIAN
1854 BNX2_DMA_CONFIG_CNTL_BYTE_SWAP |
1855 #endif
1856 BNX2_DMA_CONFIG_CNTL_WORD_SWAP |
1857 DMA_READ_CHANS << 12 |
1858 DMA_WRITE_CHANS << 16;
1859
1860 val |= (0x2 << 20) | (1 << 11);
1861
1862 if ((bp->flags & PCIX_FLAG) && (bp->bus_speed_mhz == 133))
1863 val |= (1 << 23);
1864
1865 if ((CHIP_NUM(bp) == CHIP_NUM_5706) &&
1866 (CHIP_ID(bp) != CHIP_ID_5706_A0) && !(bp->flags & PCIX_FLAG))
1867 val |= BNX2_DMA_CONFIG_CNTL_PING_PONG_DMA;
1868
1869 REG_WR(bp, BNX2_DMA_CONFIG, val);
1870
1871 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
1872 val = REG_RD(bp, BNX2_TDMA_CONFIG);
1873 val |= BNX2_TDMA_CONFIG_ONE_DMA;
1874 REG_WR(bp, BNX2_TDMA_CONFIG, val);
1875 }
1876
1877 if (bp->flags & PCIX_FLAG) {
1878 u16 val16;
1879
1880 pci_read_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
1881 &val16);
1882 pci_write_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
1883 val16 & ~PCI_X_CMD_ERO);
1884 }
1885
1886 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
1887 BNX2_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE |
1888 BNX2_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE |
1889 BNX2_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE);
1890
1891 /* Initialize context mapping and zero out the quick contexts. The
1892 * context block must have already been enabled. */
1893 bnx2_init_context(bp);
1894
1895 bnx2_init_nvram(bp);
1896 bnx2_init_cpus(bp);
1897
1898 bnx2_set_mac_addr(bp);
1899
1900 val = REG_RD(bp, BNX2_MQ_CONFIG);
1901 val &= ~BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE;
1902 val |= BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_256;
1903 REG_WR(bp, BNX2_MQ_CONFIG, val);
1904
1905 val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE);
1906 REG_WR(bp, BNX2_MQ_KNL_BYP_WIND_START, val);
1907 REG_WR(bp, BNX2_MQ_KNL_WIND_END, val);
1908
1909 val = (BCM_PAGE_BITS - 8) << 24;
1910 REG_WR(bp, BNX2_RV2P_CONFIG, val);
1911
1912 /* Configure page size. */
1913 val = REG_RD(bp, BNX2_TBDR_CONFIG);
1914 val &= ~BNX2_TBDR_CONFIG_PAGE_SIZE;
1915 val |= (BCM_PAGE_BITS - 8) << 24 | 0x40;
1916 REG_WR(bp, BNX2_TBDR_CONFIG, val);
1917
1918 val = bp->mac_addr[0] +
1919 (bp->mac_addr[1] << 8) +
1920 (bp->mac_addr[2] << 16) +
1921 bp->mac_addr[3] +
1922 (bp->mac_addr[4] << 8) +
1923 (bp->mac_addr[5] << 16);
1924 REG_WR(bp, BNX2_EMAC_BACKOFF_SEED, val);
1925
1926 /* Program the MTU. Also include 4 bytes for CRC32. */
1927 val = ETH_MAX_MTU + ETH_HLEN + 4;
1928 if (val > (MAX_ETHERNET_PACKET_SIZE + 4))
1929 val |= BNX2_EMAC_RX_MTU_SIZE_JUMBO_ENA;
1930 REG_WR(bp, BNX2_EMAC_RX_MTU_SIZE, val);
1931
1932 bp->last_status_idx = 0;
1933 bp->rx_mode = BNX2_EMAC_RX_MODE_SORT_MODE;
1934
1935 /* Set up how to generate a link change interrupt. */
1936 REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
1937
1938 REG_WR(bp, BNX2_HC_STATUS_ADDR_L,
1939 (u64) bp->status_blk_mapping & 0xffffffff);
1940 REG_WR(bp, BNX2_HC_STATUS_ADDR_H, (u64) bp->status_blk_mapping >> 32);
1941
1942 REG_WR(bp, BNX2_HC_STATISTICS_ADDR_L,
1943 (u64) bp->stats_blk_mapping & 0xffffffff);
1944 REG_WR(bp, BNX2_HC_STATISTICS_ADDR_H,
1945 (u64) bp->stats_blk_mapping >> 32);
1946
1947 REG_WR(bp, BNX2_HC_TX_QUICK_CONS_TRIP,
1948 (bp->tx_quick_cons_trip_int << 16) | bp->tx_quick_cons_trip);
1949
1950 REG_WR(bp, BNX2_HC_RX_QUICK_CONS_TRIP,
1951 (bp->rx_quick_cons_trip_int << 16) | bp->rx_quick_cons_trip);
1952
1953 REG_WR(bp, BNX2_HC_COMP_PROD_TRIP,
1954 (bp->comp_prod_trip_int << 16) | bp->comp_prod_trip);
1955
1956 REG_WR(bp, BNX2_HC_TX_TICKS, (bp->tx_ticks_int << 16) | bp->tx_ticks);
1957
1958 REG_WR(bp, BNX2_HC_RX_TICKS, (bp->rx_ticks_int << 16) | bp->rx_ticks);
1959
1960 REG_WR(bp, BNX2_HC_COM_TICKS,
1961 (bp->com_ticks_int << 16) | bp->com_ticks);
1962
1963 REG_WR(bp, BNX2_HC_CMD_TICKS,
1964 (bp->cmd_ticks_int << 16) | bp->cmd_ticks);
1965
1966 REG_WR(bp, BNX2_HC_STATS_TICKS, bp->stats_ticks & 0xffff00);
1967 REG_WR(bp, BNX2_HC_STAT_COLLECT_TICKS, 0xbb8); /* 3ms */
1968
1969 if (CHIP_ID(bp) == CHIP_ID_5706_A1)
1970 REG_WR(bp, BNX2_HC_CONFIG, BNX2_HC_CONFIG_COLLECT_STATS);
1971 else {
1972 REG_WR(bp, BNX2_HC_CONFIG, BNX2_HC_CONFIG_RX_TMR_MODE |
1973 BNX2_HC_CONFIG_TX_TMR_MODE |
1974 BNX2_HC_CONFIG_COLLECT_STATS);
1975 }
1976
1977 /* Clear internal stats counters. */
1978 REG_WR(bp, BNX2_HC_COMMAND, BNX2_HC_COMMAND_CLR_STAT_NOW);
1979
1980 REG_WR(bp, BNX2_HC_ATTN_BITS_ENABLE, STATUS_ATTN_BITS_LINK_STATE);
1981
1982 if (REG_RD_IND(bp, bp->shmem_base + BNX2_PORT_FEATURE) &
1983 BNX2_PORT_FEATURE_ASF_ENABLED)
1984 bp->flags |= ASF_ENABLE_FLAG;
1985
1986 /* Initialize the receive filter. */
1987 bnx2_set_rx_mode(bp->nic);
1988
1989 rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT2 | BNX2_DRV_MSG_CODE_RESET,
1990 0);
1991
1992 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS, 0x5ffffff);
1993 REG_RD(bp, BNX2_MISC_ENABLE_SET_BITS);
1994
1995 udelay(20);
1996
1997 bp->hc_cmd = REG_RD(bp, BNX2_HC_COMMAND);
1998
1999 return rc;
2000 }
2001
2002 static void
2003 bnx2_init_tx_ring(struct bnx2 *bp)
2004 {
2005 struct tx_bd *txbd;
2006 u32 val;
2007
2008 txbd = &bp->tx_desc_ring[MAX_TX_DESC_CNT];
2009
2010 /* Etherboot lives below 4GB, so hi is always 0 */
2011 txbd->tx_bd_haddr_hi = 0;
2012 txbd->tx_bd_haddr_lo = bp->tx_desc_mapping;
2013
2014 bp->tx_prod = 0;
2015 bp->tx_cons = 0;
2016 bp->hw_tx_cons = 0;
2017 bp->tx_prod_bseq = 0;
2018
2019 val = BNX2_L2CTX_TYPE_TYPE_L2;
2020 val |= BNX2_L2CTX_TYPE_SIZE_L2;
2021 CTX_WR(bp, GET_CID_ADDR(TX_CID), BNX2_L2CTX_TYPE, val);
2022
2023 val = BNX2_L2CTX_CMD_TYPE_TYPE_L2;
2024 val |= 8 << 16;
2025 CTX_WR(bp, GET_CID_ADDR(TX_CID), BNX2_L2CTX_CMD_TYPE, val);
2026
2027 /* Etherboot lives below 4GB, so hi is always 0 */
2028 CTX_WR(bp, GET_CID_ADDR(TX_CID), BNX2_L2CTX_TBDR_BHADDR_HI, 0);
2029
2030 val = (u64) bp->tx_desc_mapping & 0xffffffff;
2031 CTX_WR(bp, GET_CID_ADDR(TX_CID), BNX2_L2CTX_TBDR_BHADDR_LO, val);
2032 }
2033
2034 static void
2035 bnx2_init_rx_ring(struct bnx2 *bp)
2036 {
2037 struct rx_bd *rxbd;
2038 unsigned int i;
2039 u16 prod, ring_prod;
2040 u32 val;
2041
2042 bp->rx_buf_use_size = RX_BUF_USE_SIZE;
2043 bp->rx_buf_size = RX_BUF_SIZE;
2044
2045 ring_prod = prod = bp->rx_prod = 0;
2046 bp->rx_cons = 0;
2047 bp->hw_rx_cons = 0;
2048 bp->rx_prod_bseq = 0;
2049
2050 memset(bnx2_bss.rx_buf, 0, sizeof(bnx2_bss.rx_buf));
2051
2052 rxbd = &bp->rx_desc_ring[0];
2053 for (i = 0; i < MAX_RX_DESC_CNT; i++, rxbd++) {
2054 rxbd->rx_bd_len = bp->rx_buf_use_size;
2055 rxbd->rx_bd_flags = RX_BD_FLAGS_START | RX_BD_FLAGS_END;
2056 }
2057 rxbd->rx_bd_haddr_hi = 0;
2058 rxbd->rx_bd_haddr_lo = (u64) bp->rx_desc_mapping & 0xffffffff;
2059
2060 val = BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE;
2061 val |= BNX2_L2CTX_CTX_TYPE_SIZE_L2;
2062 val |= 0x02 << 8;
2063 CTX_WR(bp, GET_CID_ADDR(RX_CID), BNX2_L2CTX_CTX_TYPE, val);
2064
2065 /* Etherboot doesn't use memory above 4GB, so this is always 0 */
2066 CTX_WR(bp, GET_CID_ADDR(RX_CID), BNX2_L2CTX_NX_BDHADDR_HI, 0);
2067
2068 val = bp->rx_desc_mapping & 0xffffffff;
2069 CTX_WR(bp, GET_CID_ADDR(RX_CID), BNX2_L2CTX_NX_BDHADDR_LO, val);
2070
2071 for (i = 0; (int) i < bp->rx_ring_size; i++) {
2072 rxbd = &bp->rx_desc_ring[RX_RING_IDX(ring_prod)];
2073 rxbd->rx_bd_haddr_hi = 0;
2074 rxbd->rx_bd_haddr_lo = virt_to_bus(&bnx2_bss.rx_buf[ring_prod][0]);
2075 bp->rx_prod_bseq += bp->rx_buf_use_size;
2076 prod = NEXT_RX_BD(prod);
2077 ring_prod = RX_RING_IDX(prod);
2078 }
2079 bp->rx_prod = prod;
2080
2081 REG_WR16(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BDIDX, bp->rx_prod);
2082
2083 REG_WR(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BSEQ, bp->rx_prod_bseq);
2084 }
2085
2086 static int
2087 bnx2_reset_nic(struct bnx2 *bp, u32 reset_code)
2088 {
2089 int rc;
2090
2091 rc = bnx2_reset_chip(bp, reset_code);
2092 if (rc) {
2093 return rc;
2094 }
2095
2096 bnx2_init_chip(bp);
2097 bnx2_init_tx_ring(bp);
2098 bnx2_init_rx_ring(bp);
2099 return 0;
2100 }
2101
2102 static int
2103 bnx2_init_nic(struct bnx2 *bp)
2104 {
2105 int rc;
2106
2107 if ((rc = bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET)) != 0)
2108 return rc;
2109
2110 bnx2_init_phy(bp);
2111 bnx2_set_link(bp);
2112 return 0;
2113 }
2114
2115 static int
2116 bnx2_init_board(struct pci_device *pdev, struct nic *nic)
2117 {
2118 unsigned long bnx2reg_base, bnx2reg_len;
2119 struct bnx2 *bp = &bnx2;
2120 int rc;
2121 u32 reg;
2122
2123 bp->flags = 0;
2124 bp->phy_flags = 0;
2125
2126 /* enable device (incl. PCI PM wakeup), and bus-mastering */
2127 adjust_pci_device(pdev);
2128
2129 nic->ioaddr = pdev->ioaddr & ~3;
2130 nic->irqno = 0;
2131
2132 rc = 0;
2133 bp->pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
2134 if (bp->pm_cap == 0) {
2135 printf("Cannot find power management capability, aborting.\n");
2136 rc = -EIO;
2137 goto err_out_disable;
2138 }
2139
2140 bp->pcix_cap = pci_find_capability(pdev, PCI_CAP_ID_PCIX);
2141 if (bp->pcix_cap == 0) {
2142 printf("Cannot find PCIX capability, aborting.\n");
2143 rc = -EIO;
2144 goto err_out_disable;
2145 }
2146
2147 bp->pdev = pdev;
2148 bp->nic = nic;
2149
2150 bnx2reg_base = pci_bar_start(pdev, PCI_BASE_ADDRESS_0);
2151 bnx2reg_len = MB_GET_CID_ADDR(17);
2152
2153 bp->regview = ioremap(bnx2reg_base, bnx2reg_len);
2154
2155 if (!bp->regview) {
2156 printf("Cannot map register space, aborting.\n");
2157 rc = -EIO;
2158 goto err_out_disable;
2159 }
2160
2161 /* Configure byte swap and enable write to the reg_window registers.
2162 * Rely on CPU to do target byte swapping on big endian systems
2163 * The chip's target access swapping will not swap all accesses
2164 */
2165 pci_write_config_dword(bp->pdev, BNX2_PCICFG_MISC_CONFIG,
2166 BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
2167 BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP);
2168
2169 bnx2_set_power_state_0(bp);
2170
2171 bp->chip_id = REG_RD(bp, BNX2_MISC_ID);
2172
2173 /* Get bus information. */
2174 reg = REG_RD(bp, BNX2_PCICFG_MISC_STATUS);
2175 if (reg & BNX2_PCICFG_MISC_STATUS_PCIX_DET) {
2176 u32 clkreg;
2177
2178 bp->flags |= PCIX_FLAG;
2179
2180 clkreg = REG_RD(bp, BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS);
2181
2182 clkreg &= BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET;
2183 switch (clkreg) {
2184 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ:
2185 bp->bus_speed_mhz = 133;
2186 break;
2187
2188 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ:
2189 bp->bus_speed_mhz = 100;
2190 break;
2191
2192 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ:
2193 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ:
2194 bp->bus_speed_mhz = 66;
2195 break;
2196
2197 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ:
2198 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ:
2199 bp->bus_speed_mhz = 50;
2200 break;
2201
2202 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW:
2203 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ:
2204 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ:
2205 bp->bus_speed_mhz = 33;
2206 break;
2207 }
2208 }
2209 else {
2210 if (reg & BNX2_PCICFG_MISC_STATUS_M66EN)
2211 bp->bus_speed_mhz = 66;
2212 else
2213 bp->bus_speed_mhz = 33;
2214 }
2215
2216 if (reg & BNX2_PCICFG_MISC_STATUS_32BIT_DET)
2217 bp->flags |= PCI_32BIT_FLAG;
2218
2219 /* 5706A0 may falsely detect SERR and PERR. */
2220 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
2221 reg = REG_RD(bp, PCI_COMMAND);
2222 reg &= ~(PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
2223 REG_WR(bp, PCI_COMMAND, reg);
2224 }
2225 else if ((CHIP_ID(bp) == CHIP_ID_5706_A1) &&
2226 !(bp->flags & PCIX_FLAG)) {
2227
2228 printf("5706 A1 can only be used in a PCIX bus, aborting.\n");
2229 goto err_out_disable;
2230 }
2231
2232 bnx2_init_nvram(bp);
2233
2234 reg = REG_RD_IND(bp, BNX2_SHM_HDR_SIGNATURE);
2235
2236 if ((reg & BNX2_SHM_HDR_SIGNATURE_SIG_MASK) ==
2237 BNX2_SHM_HDR_SIGNATURE_SIG)
2238 bp->shmem_base = REG_RD_IND(bp, BNX2_SHM_HDR_ADDR_0);
2239 else
2240 bp->shmem_base = HOST_VIEW_SHMEM_BASE;
2241
2242 /* Get the permanent MAC address. First we need to make sure the
2243 * firmware is actually running.
2244 */
2245 reg = REG_RD_IND(bp, bp->shmem_base + BNX2_DEV_INFO_SIGNATURE);
2246
2247 if ((reg & BNX2_DEV_INFO_SIGNATURE_MAGIC_MASK) !=
2248 BNX2_DEV_INFO_SIGNATURE_MAGIC) {
2249 printf("Firmware not running, aborting.\n");
2250 rc = -ENODEV;
2251 goto err_out_disable;
2252 }
2253
2254 bp->fw_ver = REG_RD_IND(bp, bp->shmem_base + BNX2_DEV_INFO_BC_REV);
2255
2256 reg = REG_RD_IND(bp, bp->shmem_base + BNX2_PORT_HW_CFG_MAC_UPPER);
2257 bp->mac_addr[0] = (u8) (reg >> 8);
2258 bp->mac_addr[1] = (u8) reg;
2259
2260 reg = REG_RD_IND(bp, bp->shmem_base + BNX2_PORT_HW_CFG_MAC_LOWER);
2261 bp->mac_addr[2] = (u8) (reg >> 24);
2262 bp->mac_addr[3] = (u8) (reg >> 16);
2263 bp->mac_addr[4] = (u8) (reg >> 8);
2264 bp->mac_addr[5] = (u8) reg;
2265
2266 bp->tx_ring_size = MAX_TX_DESC_CNT;
2267 bp->rx_ring_size = RX_BUF_CNT;
2268 bp->rx_max_ring_idx = MAX_RX_DESC_CNT;
2269
2270 bp->rx_offset = RX_OFFSET;
2271
2272 bp->tx_quick_cons_trip_int = 20;
2273 bp->tx_quick_cons_trip = 20;
2274 bp->tx_ticks_int = 80;
2275 bp->tx_ticks = 80;
2276
2277 bp->rx_quick_cons_trip_int = 6;
2278 bp->rx_quick_cons_trip = 6;
2279 bp->rx_ticks_int = 18;
2280 bp->rx_ticks = 18;
2281
2282 bp->stats_ticks = 1000000 & 0xffff00;
2283
2284 bp->phy_addr = 1;
2285
2286 /* No need for WOL support in Etherboot */
2287 bp->flags |= NO_WOL_FLAG;
2288
2289 /* Disable WOL support if we are running on a SERDES chip. */
2290 if (CHIP_BOND_ID(bp) & CHIP_BOND_ID_SERDES_BIT) {
2291 bp->phy_flags |= PHY_SERDES_FLAG;
2292 if (CHIP_NUM(bp) == CHIP_NUM_5708) {
2293 bp->phy_addr = 2;
2294 reg = REG_RD_IND(bp, bp->shmem_base +
2295 BNX2_SHARED_HW_CFG_CONFIG);
2296 if (reg & BNX2_SHARED_HW_CFG_PHY_2_5G)
2297 bp->phy_flags |= PHY_2_5G_CAPABLE_FLAG;
2298 }
2299 }
2300
2301 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
2302 bp->tx_quick_cons_trip_int =
2303 bp->tx_quick_cons_trip;
2304 bp->tx_ticks_int = bp->tx_ticks;
2305 bp->rx_quick_cons_trip_int =
2306 bp->rx_quick_cons_trip;
2307 bp->rx_ticks_int = bp->rx_ticks;
2308 bp->comp_prod_trip_int = bp->comp_prod_trip;
2309 bp->com_ticks_int = bp->com_ticks;
2310 bp->cmd_ticks_int = bp->cmd_ticks;
2311 }
2312
2313 bp->autoneg = AUTONEG_SPEED | AUTONEG_FLOW_CTRL;
2314 bp->req_line_speed = 0;
2315 if (bp->phy_flags & PHY_SERDES_FLAG) {
2316 bp->advertising = ETHTOOL_ALL_FIBRE_SPEED | ADVERTISED_Autoneg;
2317
2318 reg = REG_RD_IND(bp, bp->shmem_base + BNX2_PORT_HW_CFG_CONFIG);
2319 reg &= BNX2_PORT_HW_CFG_CFG_DFLT_LINK_MASK;
2320 if (reg == BNX2_PORT_HW_CFG_CFG_DFLT_LINK_1G) {
2321 bp->autoneg = 0;
2322 bp->req_line_speed = bp->line_speed = SPEED_1000;
2323 bp->req_duplex = DUPLEX_FULL;
2324 }
2325 }
2326 else {
2327 bp->advertising = ETHTOOL_ALL_COPPER_SPEED | ADVERTISED_Autoneg;
2328 }
2329
2330 bp->req_flow_ctrl = FLOW_CTRL_RX | FLOW_CTRL_TX;
2331
2332 /* Disable driver heartbeat checking */
2333 REG_WR_IND(bp, bp->shmem_base + BNX2_DRV_PULSE_MB,
2334 BNX2_DRV_MSG_DATA_PULSE_CODE_ALWAYS_ALIVE);
2335 REG_RD_IND(bp, bp->shmem_base + BNX2_DRV_PULSE_MB);
2336
2337 return 0;
2338
2339 err_out_disable:
2340 bnx2_disable(nic);
2341
2342 return rc;
2343 }
2344
2345 static void
2346 bnx2_transmit(struct nic *nic, const char *dst_addr,
2347 unsigned int type, unsigned int size, const char *packet)
2348 {
2349 /* Sometimes the nic will be behind by a frame. Using two transmit
2350 * buffers prevents us from timing out in that case.
2351 */
2352 static struct eth_frame {
2353 uint8_t dst_addr[ETH_ALEN];
2354 uint8_t src_addr[ETH_ALEN];
2355 uint16_t type;
2356 uint8_t data [ETH_FRAME_LEN - ETH_HLEN];
2357 } frame[2];
2358 static int frame_idx = 0;
2359
2360 /* send the packet to destination */
2361 struct tx_bd *txbd;
2362 struct bnx2 *bp = &bnx2;
2363 u16 prod, ring_prod;
2364 u16 hw_cons;
2365 int i = 0;
2366
2367 prod = bp->tx_prod;
2368 ring_prod = TX_RING_IDX(prod);
2369 hw_cons = bp->status_blk->status_tx_quick_consumer_index0;
2370 if ((hw_cons & MAX_TX_DESC_CNT) == MAX_TX_DESC_CNT) {
2371 hw_cons++;
2372 }
2373
2374 while((hw_cons != prod) && (hw_cons != (PREV_TX_BD(prod)))) {
2375 mdelay(10); /* give the nic a chance */
2376 //poll_interruptions();
2377 if (++i > 500) { /* timeout 5s for transmit */
2378 printf("transmit timed out\n");
2379 bnx2_disable(bp->nic);
2380 bnx2_init_board(bp->pdev, bp->nic);
2381 return;
2382 }
2383 }
2384 if (i != 0) {
2385 printf("#");
2386 }
2387
2388 /* Copy the packet to the our local buffer */
2389 memcpy(&frame[frame_idx].dst_addr, dst_addr, ETH_ALEN);
2390 memcpy(&frame[frame_idx].src_addr, nic->node_addr, ETH_ALEN);
2391 frame[frame_idx].type = htons(type);
2392 memset(&frame[frame_idx].data, 0, sizeof(frame[frame_idx].data));
2393 memcpy(&frame[frame_idx].data, packet, size);
2394
2395 /* Setup the ring buffer entry to transmit */
2396 txbd = &bp->tx_desc_ring[ring_prod];
2397 txbd->tx_bd_haddr_hi = 0; /* Etherboot runs under 4GB */
2398 txbd->tx_bd_haddr_lo = virt_to_bus(&frame[frame_idx]);
2399 txbd->tx_bd_mss_nbytes = (size + ETH_HLEN);
2400 txbd->tx_bd_vlan_tag_flags = TX_BD_FLAGS_START | TX_BD_FLAGS_END;
2401
2402 /* Advance to the next entry */
2403 prod = NEXT_TX_BD(prod);
2404 frame_idx ^= 1;
2405
2406 bp->tx_prod_bseq += (size + ETH_HLEN);
2407
2408 REG_WR16(bp, MB_TX_CID_ADDR + BNX2_L2CTX_TX_HOST_BIDX, prod);
2409 REG_WR(bp, MB_TX_CID_ADDR + BNX2_L2CTX_TX_HOST_BSEQ, bp->tx_prod_bseq);
2410
2411 wmb();
2412
2413 bp->tx_prod = prod;
2414 }
2415
2416 static int
2417 bnx2_poll_link(struct bnx2 *bp)
2418 {
2419 u32 new_link_state, old_link_state, emac_status;
2420
2421 new_link_state = bp->status_blk->status_attn_bits &
2422 STATUS_ATTN_BITS_LINK_STATE;
2423
2424 old_link_state = bp->status_blk->status_attn_bits_ack &
2425 STATUS_ATTN_BITS_LINK_STATE;
2426
2427 if (!new_link_state && !old_link_state) {
2428 /* For some reason the card doesn't always update the link
2429 * status bits properly. Kick the stupid thing and try again.
2430 */
2431 u32 bmsr;
2432
2433 bnx2_read_phy(bp, MII_BMSR, &bmsr);
2434 bnx2_read_phy(bp, MII_BMSR, &bmsr);
2435
2436 if ((bp->phy_flags & PHY_SERDES_FLAG) &&
2437 (CHIP_NUM(bp) == CHIP_NUM_5706)) {
2438 REG_RD(bp, BNX2_EMAC_STATUS);
2439 }
2440
2441 new_link_state = bp->status_blk->status_attn_bits &
2442 STATUS_ATTN_BITS_LINK_STATE;
2443
2444 old_link_state = bp->status_blk->status_attn_bits_ack &
2445 STATUS_ATTN_BITS_LINK_STATE;
2446
2447 /* Okay, for some reason the above doesn't work with some
2448 * switches (like HP ProCurve). If the above doesn't work,
2449 * check the MAC directly to see if we have a link. Perhaps we
2450 * should always check the MAC instead probing the MII.
2451 */
2452 if (!new_link_state && !old_link_state) {
2453 emac_status = REG_RD(bp, BNX2_EMAC_STATUS);
2454 if (emac_status & BNX2_EMAC_STATUS_LINK_CHANGE) {
2455 /* Acknowledge the link change */
2456 REG_WR(bp, BNX2_EMAC_STATUS, BNX2_EMAC_STATUS_LINK_CHANGE);
2457 } else if (emac_status & BNX2_EMAC_STATUS_LINK) {
2458 new_link_state = !old_link_state;
2459 }
2460 }
2461
2462 }
2463
2464 if (new_link_state != old_link_state) {
2465 if (new_link_state) {
2466 REG_WR(bp, BNX2_PCICFG_STATUS_BIT_SET_CMD,
2467 STATUS_ATTN_BITS_LINK_STATE);
2468 }
2469 else {
2470 REG_WR(bp, BNX2_PCICFG_STATUS_BIT_CLEAR_CMD,
2471 STATUS_ATTN_BITS_LINK_STATE);
2472 }
2473
2474 bnx2_set_link(bp);
2475
2476 /* This is needed to take care of transient status
2477 * during link changes.
2478 */
2479
2480 REG_WR(bp, BNX2_HC_COMMAND,
2481 bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
2482 REG_RD(bp, BNX2_HC_COMMAND);
2483
2484 }
2485
2486 return bp->link_up;
2487 }
2488
2489 static int
2490 bnx2_poll(struct nic* nic, int retrieve)
2491 {
2492 struct bnx2 *bp = &bnx2;
2493 struct rx_bd *cons_bd, *prod_bd;
2494 u16 hw_cons, sw_cons, sw_ring_cons, sw_prod, sw_ring_prod;
2495 struct l2_fhdr *rx_hdr;
2496 int result = 0;
2497 unsigned int len;
2498 unsigned char *data;
2499 u32 status;
2500
2501 #if 0
2502 if ((bp->status_blk->status_idx == bp->last_status_idx) &&
2503 (REG_RD(bp, BNX2_PCICFG_MISC_STATUS) &
2504 BNX2_PCICFG_MISC_STATUS_INTA_VALUE)) {
2505
2506 bp->last_status_idx = bp->status_blk->status_idx;
2507 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
2508 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
2509 BNX2_PCICFG_INT_ACK_CMD_MASK_INT |
2510 bp->last_status_idx);
2511 return 0;
2512 }
2513 #endif
2514
2515 if ((bp->status_blk->status_rx_quick_consumer_index0 != bp->rx_cons) && !retrieve)
2516 return 1;
2517
2518 if (bp->status_blk->status_rx_quick_consumer_index0 != bp->rx_cons) {
2519
2520 hw_cons = bp->hw_rx_cons = bp->status_blk->status_rx_quick_consumer_index0;
2521 if ((hw_cons & MAX_RX_DESC_CNT) == MAX_RX_DESC_CNT) {
2522 hw_cons++;
2523 }
2524 sw_cons = bp->rx_cons;
2525 sw_prod = bp->rx_prod;
2526
2527 rmb();
2528 if (sw_cons != hw_cons) {
2529
2530 sw_ring_cons = RX_RING_IDX(sw_cons);
2531 sw_ring_prod = RX_RING_IDX(sw_prod);
2532
2533 data = bus_to_virt(bp->rx_desc_ring[sw_ring_cons].rx_bd_haddr_lo);
2534
2535 rx_hdr = (struct l2_fhdr *)data;
2536 len = rx_hdr->l2_fhdr_pkt_len - 4;
2537 if ((len > (ETH_MAX_MTU + ETH_HLEN)) ||
2538 ((status = rx_hdr->l2_fhdr_status) &
2539 (L2_FHDR_ERRORS_BAD_CRC |
2540 L2_FHDR_ERRORS_PHY_DECODE |
2541 L2_FHDR_ERRORS_ALIGNMENT |
2542 L2_FHDR_ERRORS_TOO_SHORT |
2543 L2_FHDR_ERRORS_GIANT_FRAME))) {
2544 result = 0;
2545 }
2546 else
2547 {
2548 nic->packetlen = len;
2549 memcpy(nic->packet, data + bp->rx_offset, len);
2550 result = 1;
2551 }
2552
2553 /* Reuse the buffer */
2554 bp->rx_prod_bseq += bp->rx_buf_use_size;
2555 if (sw_cons != sw_prod) {
2556 cons_bd = &bp->rx_desc_ring[sw_ring_cons];
2557 prod_bd = &bp->rx_desc_ring[sw_ring_prod];
2558 prod_bd->rx_bd_haddr_hi = 0; /* Etherboot runs under 4GB */
2559 prod_bd->rx_bd_haddr_lo = cons_bd->rx_bd_haddr_lo;
2560 }
2561
2562 sw_cons = NEXT_RX_BD(sw_cons);
2563 sw_prod = NEXT_RX_BD(sw_prod);
2564
2565 }
2566
2567 bp->rx_cons = sw_cons;
2568 bp->rx_prod = sw_prod;
2569
2570 REG_WR16(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BDIDX, bp->rx_prod);
2571
2572 REG_WR(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BSEQ, bp->rx_prod_bseq);
2573
2574 wmb();
2575
2576 }
2577
2578 bnx2_poll_link(bp);
2579
2580 #if 0
2581 bp->last_status_idx = bp->status_blk->status_idx;
2582 rmb();
2583
2584 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
2585 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
2586 BNX2_PCICFG_INT_ACK_CMD_MASK_INT |
2587 bp->last_status_idx);
2588
2589 REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
2590 #endif
2591
2592 return result;
2593 }
2594
2595 static void
2596 bnx2_irq(struct nic *nic __unused, irq_action_t action __unused)
2597 {
2598 switch ( action ) {
2599 case DISABLE: break;
2600 case ENABLE: break;
2601 case FORCE: break;
2602 }
2603 }
2604
2605 static struct nic_operations bnx2_operations = {
2606 .connect = dummy_connect,
2607 .poll = bnx2_poll,
2608 .transmit = bnx2_transmit,
2609 .irq = bnx2_irq,
2610 };
2611
2612 static int
2613 bnx2_probe(struct nic *nic, struct pci_device *pdev)
2614 {
2615 struct bnx2 *bp = &bnx2;
2616 int i, rc;
2617
2618 if (pdev == 0)
2619 return 0;
2620
2621 memset(bp, 0, sizeof(*bp));
2622
2623 rc = bnx2_init_board(pdev, nic);
2624 if (rc < 0) {
2625 return 0;
2626 }
2627
2628 /*
2629 nic->disable = bnx2_disable;
2630 nic->transmit = bnx2_transmit;
2631 nic->poll = bnx2_poll;
2632 nic->irq = bnx2_irq;
2633 */
2634
2635 nic->nic_op = &bnx2_operations;
2636
2637 memcpy(nic->node_addr, bp->mac_addr, ETH_ALEN);
2638 printf("Ethernet addr: %s\n", eth_ntoa( nic->node_addr ) );
2639 printf("Broadcom NetXtreme II (%c%d) PCI%s %s %dMHz\n",
2640 (int) ((CHIP_ID(bp) & 0xf000) >> 12) + 'A',
2641 (int) ((CHIP_ID(bp) & 0x0ff0) >> 4),
2642 ((bp->flags & PCIX_FLAG) ? "-X" : ""),
2643 ((bp->flags & PCI_32BIT_FLAG) ? "32-bit" : "64-bit"),
2644 bp->bus_speed_mhz);
2645
2646 bnx2_set_power_state_0(bp);
2647 bnx2_disable_int(bp);
2648
2649 bnx2_alloc_mem(bp);
2650
2651 rc = bnx2_init_nic(bp);
2652 if (rc) {
2653 return 0;
2654 }
2655
2656 bnx2_poll_link(bp);
2657 for(i = 0; !bp->link_up && (i < VALID_LINK_TIMEOUT*100); i++) {
2658 mdelay(1);
2659 bnx2_poll_link(bp);
2660 }
2661 #if 1
2662 if (!bp->link_up){
2663 printf("Valid link not established\n");
2664 goto err_out_disable;
2665 }
2666 #endif
2667
2668 return 1;
2669
2670 err_out_disable:
2671 bnx2_disable(nic);
2672 return 0;
2673 }
2674
2675 static struct pci_device_id bnx2_nics[] = {
2676 PCI_ROM(0x14e4, 0x164a, "bnx2-5706", "Broadcom NetXtreme II BCM5706"),
2677 PCI_ROM(0x14e4, 0x164c, "bnx2-5708", "Broadcom NetXtreme II BCM5708"),
2678 PCI_ROM(0x14e4, 0x16aa, "bnx2-5706S", "Broadcom NetXtreme II BCM5706S"),
2679 PCI_ROM(0x14e4, 0x16ac, "bnx2-5708S", "Broadcom NetXtreme II BCM5708S"),
2680 };
2681
2682 PCI_DRIVER ( bnx2_driver, bnx2_nics, PCI_NO_CLASS );
2683
2684 DRIVER ( "BNX2", nic_driver, pci_driver, bnx2_driver, bnx2_probe, bnx2_disable );
2685
2686 /*
2687 static struct pci_driver bnx2_driver __pci_driver = {
2688 .type = NIC_DRIVER,
2689 .name = "BNX2",
2690 .probe = bnx2_probe,
2691 .ids = bnx2_nics,
2692 .id_count = sizeof(bnx2_nics)/sizeof(bnx2_nics[0]),
2693 .class = 0,
2694 };
2695 */
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