src/drivers/net/eepro.c

   1 #ifdef ALLMULTI
   2 #error multicast support is not yet implemented
   3 #endif
   4 /**************************************************************************
   5 Etherboot -  BOOTP/TFTP Bootstrap Program
   6 Intel EEPRO/10 NIC driver for Etherboot
   7 Adapted from Linux eepro.c from kernel 2.2.17
   8
   9 This board accepts a 32 pin EEPROM (29C256), however a test with a
  10 27C010 shows that this EPROM also works in the socket, but it's not clear
  11 how repeatably. The two top address pins appear to be held low, thus
  12 the bottom 32kB of the 27C010 is visible in the CPU's address space.
  13 To be sure you could put 4 copies of the code in the 27C010, then
  14 it doesn't matter whether the extra lines are held low or high, just
  15 hopefully not floating as CMOS chips don't like floating inputs.
  16
  17 Be careful with seating the EPROM as the socket on my board actually
  18 has 34 pins, the top row of 2 are not used.
  19 ***************************************************************************/
  20
  21 /*
  22
  23  timlegge       2005-05-18      remove the relocation changes cards that
  24                                 write directly to the hardware don't need it
  25 */
  26
  27 /*
  28  * This program is free software; you can redistribute it and/or
  29  * modify it under the terms of the GNU General Public License as
  30  * published by the Free Software Foundation; either version 2, or (at
  31  * your option) any later version.
  32  */
  33
  34 #include "etherboot.h"
  35 #include "nic.h"
  36 #include <gpxe/isa.h>
  37 #include "timer.h"
  38 #include <gpxe/ethernet.h>
  39
  40 /* Different 82595 chips */
  41 #define LAN595          0
  42 #define LAN595TX        1
  43 #define LAN595FX        2
  44 #define LAN595FX_10ISA  3
  45
  46 #define SLOW_DOWN       inb(0x80);
  47
  48 /* The station (ethernet) address prefix, used for IDing the board. */
  49 #define SA_ADDR0 0x00   /* Etherexpress Pro/10 */
  50 #define SA_ADDR1 0xaa
  51 #define SA_ADDR2 0x00
  52
  53 #define GetBit(x,y) ((x & (1<<y))>>y)
  54
  55 /* EEPROM Word 0: */
  56 #define ee_PnP       0  /* Plug 'n Play enable bit */
  57 #define ee_Word1     1  /* Word 1? */
  58 #define ee_BusWidth  2  /* 8/16 bit */
  59 #define ee_FlashAddr 3  /* Flash Address */
  60 #define ee_FlashMask 0x7   /* Mask */
  61 #define ee_AutoIO    6  /* */
  62 #define ee_reserved0 7  /* =0! */
  63 #define ee_Flash     8  /* Flash there? */
  64 #define ee_AutoNeg   9  /* Auto Negotiation enabled? */
  65 #define ee_IO0       10 /* IO Address LSB */
  66 #define ee_IO0Mask   0x /*...*/
  67 #define ee_IO1       15 /* IO MSB */
  68
  69 /* EEPROM Word 1: */
  70 #define ee_IntSel    0   /* Interrupt */
  71 #define ee_IntMask   0x7
  72 #define ee_LI        3   /* Link Integrity 0= enabled */
  73 #define ee_PC        4   /* Polarity Correction 0= enabled */
  74 #define ee_TPE_AUI   5   /* PortSelection 1=TPE */
  75 #define ee_Jabber    6   /* Jabber prevention 0= enabled */
  76 #define ee_AutoPort  7   /* Auto Port Selection 1= Disabled */
  77 #define ee_SMOUT     8   /* SMout Pin Control 0= Input */
  78 #define ee_PROM      9   /* Flash EPROM / PROM 0=Flash */
  79 #define ee_reserved1 10  /* .. 12 =0! */
  80 #define ee_AltReady  13  /* Alternate Ready, 0=normal */
  81 #define ee_reserved2 14  /* =0! */
  82 #define ee_Duplex    15
  83
  84 /* Word2,3,4: */
  85 #define ee_IA5       0 /*bit start for individual Addr Byte 5 */
  86 #define ee_IA4       8 /*bit start for individual Addr Byte 5 */
  87 #define ee_IA3       0 /*bit start for individual Addr Byte 5 */
  88 #define ee_IA2       8 /*bit start for individual Addr Byte 5 */
  89 #define ee_IA1       0 /*bit start for individual Addr Byte 5 */
  90 #define ee_IA0       8 /*bit start for individual Addr Byte 5 */
  91
  92 /* Word 5: */
  93 #define ee_BNC_TPE   0 /* 0=TPE */
  94 #define ee_BootType  1 /* 00=None, 01=IPX, 10=ODI, 11=NDIS */
  95 #define ee_BootTypeMask 0x3
  96 #define ee_NumConn   3  /* Number of Connections 0= One or Two */
  97 #define ee_FlashSock 4  /* Presence of Flash Socket 0= Present */
  98 #define ee_PortTPE   5
  99 #define ee_PortBNC   6
 100 #define ee_PortAUI   7
 101 #define ee_PowerMgt  10 /* 0= disabled */
 102 #define ee_CP        13 /* Concurrent Processing */
 103 #define ee_CPMask    0x7
 104
 105 /* Word 6: */
 106 #define ee_Stepping  0 /* Stepping info */
 107 #define ee_StepMask  0x0F
 108 #define ee_BoardID   4 /* Manucaturer Board ID, reserved */
 109 #define ee_BoardMask 0x0FFF
 110
 111 /* Word 7: */
 112 #define ee_INT_TO_IRQ 0 /* int to IRQ Mapping  = 0x1EB8 for Pro/10+ */
 113 #define ee_FX_INT2IRQ 0x1EB8 /* the _only_ mapping allowed for FX chips */
 114
 115 /*..*/
 116 #define ee_SIZE 0x40 /* total EEprom Size */
 117 #define ee_Checksum 0xBABA /* initial and final value for adding checksum */
 118
 119
 120 /* Card identification via EEprom:   */
 121 #define ee_addr_vendor 0x10  /* Word offset for EISA Vendor ID */
 122 #define ee_addr_id 0x11      /* Word offset for Card ID */
 123 #define ee_addr_SN 0x12      /* Serial Number */
 124 #define ee_addr_CRC_8 0x14   /* CRC over last thee Bytes */
 125
 126
 127 #define ee_vendor_intel0 0x25  /* Vendor ID Intel */
 128 #define ee_vendor_intel1 0xD4
 129 #define ee_id_eepro10p0 0x10   /* ID for eepro/10+ */
 130 #define ee_id_eepro10p1 0x31
 131
 132 /* now this section could be used by both boards: the oldies and the ee10:
 133  * ee10 uses tx buffer before of rx buffer and the oldies the inverse.
 134  * (aris)
 135  */
 136 #define RAM_SIZE        0x8000
 137
 138 #define RCV_HEADER      8
 139 #define RCV_DEFAULT_RAM 0x6000
 140 #define RCV_RAM         rcv_ram
 141
 142 static unsigned rcv_ram = RCV_DEFAULT_RAM;
 143
 144 #define XMT_HEADER      8
 145 #define XMT_RAM         (RAM_SIZE - RCV_RAM)
 146
 147 #define XMT_START       ((rcv_start + RCV_RAM) % RAM_SIZE)
 148
 149 #define RCV_LOWER_LIMIT (rcv_start >> 8)
 150 #define RCV_UPPER_LIMIT (((rcv_start + RCV_RAM) - 2) >> 8)
 151 #define XMT_LOWER_LIMIT (XMT_START >> 8)
 152 #define XMT_UPPER_LIMIT (((XMT_START + XMT_RAM) - 2) >> 8)
 153
 154 #define RCV_START_PRO   0x00
 155 #define RCV_START_10    XMT_RAM
 156                                         /* by default the old driver */
 157 static unsigned rcv_start = RCV_START_PRO;
 158
 159 #define RCV_DONE        0x0008
 160 #define RX_OK           0x2000
 161 #define RX_ERROR        0x0d81
 162
 163 #define TX_DONE_BIT     0x0080
 164 #define CHAIN_BIT       0x8000
 165 #define XMT_STATUS      0x02
 166 #define XMT_CHAIN       0x04
 167 #define XMT_COUNT       0x06
 168
 169 #define BANK0_SELECT    0x00
 170 #define BANK1_SELECT    0x40
 171 #define BANK2_SELECT    0x80
 172
 173 /* Bank 0 registers */
 174 #define COMMAND_REG     0x00    /* Register 0 */
 175 #define MC_SETUP        0x03
 176 #define XMT_CMD         0x04
 177 #define DIAGNOSE_CMD    0x07
 178 #define RCV_ENABLE_CMD  0x08
 179 #define RCV_DISABLE_CMD 0x0a
 180 #define STOP_RCV_CMD    0x0b
 181 #define RESET_CMD       0x0e
 182 #define POWER_DOWN_CMD  0x18
 183 #define RESUME_XMT_CMD  0x1c
 184 #define SEL_RESET_CMD   0x1e
 185 #define STATUS_REG      0x01    /* Register 1 */
 186 #define RX_INT          0x02
 187 #define TX_INT          0x04
 188 #define EXEC_STATUS     0x30
 189 #define ID_REG          0x02    /* Register 2   */
 190 #define R_ROBIN_BITS    0xc0    /* round robin counter */
 191 #define ID_REG_MASK     0x2c
 192 #define ID_REG_SIG      0x24
 193 #define AUTO_ENABLE     0x10
 194 #define INT_MASK_REG    0x03    /* Register 3   */
 195 #define RX_STOP_MASK    0x01
 196 #define RX_MASK         0x02
 197 #define TX_MASK         0x04
 198 #define EXEC_MASK       0x08
 199 #define ALL_MASK        0x0f
 200 #define IO_32_BIT       0x10
 201 #define RCV_BAR         0x04    /* The following are word (16-bit) registers */
 202 #define RCV_STOP        0x06
 203
 204 #define XMT_BAR_PRO     0x0a
 205 #define XMT_BAR_10      0x0b
 206 static unsigned xmt_bar = XMT_BAR_PRO;
 207
 208 #define HOST_ADDRESS_REG        0x0c
 209 #define IO_PORT         0x0e
 210 #define IO_PORT_32_BIT  0x0c
 211
 212 /* Bank 1 registers */
 213 #define REG1    0x01
 214 #define WORD_WIDTH      0x02
 215 #define INT_ENABLE      0x80
 216 #define INT_NO_REG      0x02
 217 #define RCV_LOWER_LIMIT_REG     0x08
 218 #define RCV_UPPER_LIMIT_REG     0x09
 219
 220 #define XMT_LOWER_LIMIT_REG_PRO 0x0a
 221 #define XMT_UPPER_LIMIT_REG_PRO 0x0b
 222 #define XMT_LOWER_LIMIT_REG_10  0x0b
 223 #define XMT_UPPER_LIMIT_REG_10  0x0a
 224 static unsigned xmt_lower_limit_reg = XMT_LOWER_LIMIT_REG_PRO;
 225 static unsigned xmt_upper_limit_reg = XMT_UPPER_LIMIT_REG_PRO;
 226
 227 /* Bank 2 registers */
 228 #define XMT_Chain_Int   0x20    /* Interrupt at the end of the transmit chain */
 229 #define XMT_Chain_ErrStop       0x40 /* Interrupt at the end of the chain even if there are errors */
 230 #define RCV_Discard_BadFrame    0x80 /* Throw bad frames away, and continue to receive others */
 231 #define REG2            0x02
 232 #define PRMSC_Mode      0x01
 233 #define Multi_IA        0x20
 234 #define REG3            0x03
 235 #define TPE_BIT         0x04
 236 #define BNC_BIT         0x20
 237 #define REG13           0x0d
 238 #define FDX             0x00
 239 #define A_N_ENABLE      0x02
 240
 241 #define I_ADD_REG0      0x04
 242 #define I_ADD_REG1      0x05
 243 #define I_ADD_REG2      0x06
 244 #define I_ADD_REG3      0x07
 245 #define I_ADD_REG4      0x08
 246 #define I_ADD_REG5      0x09
 247
 248 #define EEPROM_REG_PRO  0x0a
 249 #define EEPROM_REG_10   0x0b
 250 static unsigned eeprom_reg = EEPROM_REG_PRO;
 251
 252 #define EESK 0x01
 253 #define EECS 0x02
 254 #define EEDI 0x04
 255 #define EEDO 0x08
 256
 257 /* The horrible routine to read a word from the serial EEPROM. */
 258 /* IMPORTANT - the 82595 will be set to Bank 0 after the eeprom is read */
 259
 260 /* The delay between EEPROM clock transitions. */
 261 #define eeprom_delay() { udelay(40); }
 262 #define EE_READ_CMD (6 << 6)
 263
 264 /* do a full reset; data sheet asks for 250us delay */
 265 #define eepro_full_reset(ioaddr)        outb(RESET_CMD, ioaddr); udelay(255);
 266
 267 /* do a nice reset */
 268 #define eepro_sel_reset(ioaddr) \
 269   do {  \
 270     outb ( SEL_RESET_CMD, ioaddr ); \
 271     (void) SLOW_DOWN; \
 272     (void) SLOW_DOWN; \
 273   } while (0)
 274
 275 /* clear all interrupts */
 276 #define eepro_clear_int(ioaddr) outb(ALL_MASK, ioaddr + STATUS_REG)
 277
 278 /* enable rx */
 279 #define eepro_en_rx(ioaddr)     outb(RCV_ENABLE_CMD, ioaddr)
 280
 281 /* disable rx */
 282 #define eepro_dis_rx(ioaddr)    outb(RCV_DISABLE_CMD, ioaddr)
 283
 284 /* switch bank */
 285 #define eepro_sw2bank0(ioaddr) outb(BANK0_SELECT, ioaddr)
 286 #define eepro_sw2bank1(ioaddr) outb(BANK1_SELECT, ioaddr)
 287 #define eepro_sw2bank2(ioaddr) outb(BANK2_SELECT, ioaddr)
 288
 289 static unsigned int     rx_start, tx_start;
 290 static int              tx_last;
 291 static unsigned int     tx_end;
 292 static int              eepro = 0;
 293 static unsigned int     mem_start, mem_end = RCV_DEFAULT_RAM / 1024;
 294
 295 /**************************************************************************
 296 RESET - Reset adapter
 297 ***************************************************************************/
 298 static void eepro_reset(struct nic *nic)
 299 {
 300         int             temp_reg, i;
 301
 302         /* put the card in its initial state */
 303         eepro_sw2bank2(nic->ioaddr);    /* be careful, bank2 now */
 304         temp_reg = inb(nic->ioaddr + eeprom_reg);
 305         DBG("Stepping %d\n", temp_reg >> 5);
 306         if (temp_reg & 0x10)    /* check the TurnOff Enable bit */
 307                 outb(temp_reg & 0xEF, nic->ioaddr + eeprom_reg);
 308         for (i = 0; i < ETH_ALEN; i++)  /* fill the MAC address */
 309                 outb(nic->node_addr[i], nic->ioaddr + I_ADD_REG0 + i);
 310         temp_reg = inb(nic->ioaddr + REG1);
 311         /* setup Transmit Chaining and discard bad RCV frames */
 312         outb(temp_reg | XMT_Chain_Int | XMT_Chain_ErrStop
 313                 | RCV_Discard_BadFrame, nic->ioaddr + REG1);
 314         temp_reg = inb(nic->ioaddr + REG2);             /* match broadcast */
 315         outb(temp_reg | 0x14, nic->ioaddr + REG2);
 316         temp_reg = inb(nic->ioaddr + REG3);
 317         outb(temp_reg & 0x3F, nic->ioaddr + REG3);      /* clear test mode */
 318         /* set the receiving mode */
 319         eepro_sw2bank1(nic->ioaddr);    /* be careful, bank1 now */
 320         /* initialise the RCV and XMT upper and lower limits */
 321         outb(RCV_LOWER_LIMIT, nic->ioaddr + RCV_LOWER_LIMIT_REG);
 322         outb(RCV_UPPER_LIMIT, nic->ioaddr + RCV_UPPER_LIMIT_REG);
 323         outb(XMT_LOWER_LIMIT, nic->ioaddr + xmt_lower_limit_reg);
 324         outb(XMT_UPPER_LIMIT, nic->ioaddr + xmt_upper_limit_reg);
 325         eepro_sw2bank0(nic->ioaddr);    /* Switch back to bank 0 */
 326         eepro_clear_int(nic->ioaddr);
 327         /* Initialise RCV */
 328         outw(rx_start = (RCV_LOWER_LIMIT << 8), nic->ioaddr + RCV_BAR);
 329         outw(((RCV_UPPER_LIMIT << 8) | 0xFE), nic->ioaddr + RCV_STOP);
 330         /* Make sure 1st poll won't find a valid packet header */
 331         outw((RCV_LOWER_LIMIT << 8), nic->ioaddr + HOST_ADDRESS_REG);
 332         outw(0,                      nic->ioaddr + IO_PORT);
 333         /* Intialise XMT */
 334         outw((XMT_LOWER_LIMIT << 8), nic->ioaddr + xmt_bar);
 335         eepro_sel_reset(nic->ioaddr);
 336         tx_start = tx_end = (unsigned int) (XMT_LOWER_LIMIT << 8);
 337         tx_last = 0;
 338         eepro_en_rx(nic->ioaddr);
 339 }
 340
 341 /**************************************************************************
 342 POLL - Wait for a frame
 343 ***************************************************************************/
 344 static int eepro_poll(struct nic *nic, int retrieve)
 345 {
 346         unsigned int    rcv_car = rx_start;
 347         unsigned int    rcv_event, rcv_status, rcv_next_frame, rcv_size;
 348
 349         /* return true if there's an ethernet packet ready to read */
 350         /* nic->packet should contain data on return */
 351         /* nic->packetlen should contain length of data */
 352 #if     0
 353         if ((inb(nic->ioaddr + STATUS_REG) & 0x40) == 0)
 354                 return (0);
 355         outb(0x40, nic->ioaddr + STATUS_REG);
 356 #endif
 357         outw(rcv_car, nic->ioaddr + HOST_ADDRESS_REG);
 358         rcv_event = inw(nic->ioaddr + IO_PORT);
 359         if (rcv_event != RCV_DONE)
 360                 return (0);
 361
 362         /* FIXME: I'm guessing this might not work with this card, since
 363            it looks like once a rcv_event is started it must be completed.
 364            maybe there's another way. */
 365         if ( ! retrieve ) return 1;
 366
 367         rcv_status = inw(nic->ioaddr + IO_PORT);
 368         rcv_next_frame = inw(nic->ioaddr + IO_PORT);
 369         rcv_size = inw(nic->ioaddr + IO_PORT);
 370 #if     0
 371         printf("%hX %hX %d %hhX\n", rcv_status, rcv_next_frame, rcv_size,
 372                 inb(nic->ioaddr + STATUS_REG));
 373 #endif
 374         if ((rcv_status & (RX_OK|RX_ERROR)) != RX_OK) {
 375                 printf("Receive error %hX\n", rcv_status);
 376                 return (0);
 377         }
 378         rcv_size &= 0x3FFF;
 379         insw(nic->ioaddr + IO_PORT, nic->packet, ((rcv_size + 3) >> 1));
 380 #if     0
 381 {
 382         int i;
 383         for (i = 0; i < 48; i++) {
 384                 printf("%hhX", nic->packet[i]);
 385                 putchar(i % 16 == 15 ? '\n' : ' ');
 386         }
 387 }
 388 #endif
 389         nic->packetlen = rcv_size;
 390         rcv_car  = (rx_start + RCV_HEADER + rcv_size);
 391         rx_start = rcv_next_frame;
 392 /*
 393         hex_dump(rcv_car, nic->packetlen);
 394 */
 395
 396         if (rcv_car == 0)
 397                 rcv_car = ((RCV_UPPER_LIMIT << 8) | 0xff);
 398         outw(rcv_car - 1, nic->ioaddr + RCV_STOP);
 399         return (1);
 400 }
 401
 402 /**************************************************************************
 403 TRANSMIT - Transmit a frame
 404 ***************************************************************************/
 405 static void eepro_transmit(
 406         struct nic *nic,
 407         const char *d,                  /* Destination */
 408         unsigned int t,                 /* Type */
 409         unsigned int s,                 /* size */
 410         const char *p)                  /* Packet */
 411 {
 412         unsigned int    status, tx_available, last, end, length;
 413         unsigned short  type;
 414         int             boguscount = 20;
 415
 416         length = s + ETH_HLEN;
 417         if (tx_end > tx_start)
 418                 tx_available = XMT_RAM - (tx_end - tx_start);
 419         else if (tx_end < tx_start)
 420                 tx_available = tx_start - tx_end;
 421         else
 422                 tx_available = XMT_RAM;
 423         last = tx_end;
 424         end = last + (((length + 3) >> 1) << 1) + XMT_HEADER;
 425         if (end >= (XMT_UPPER_LIMIT << 8)) {
 426                 last = (XMT_LOWER_LIMIT << 8);
 427                 end = last + (((length + 3) >> 1) << 1) + XMT_HEADER;
 428         }
 429         outw(last, nic->ioaddr + HOST_ADDRESS_REG);
 430         outw(XMT_CMD, nic->ioaddr + IO_PORT);
 431         outw(0, nic->ioaddr + IO_PORT);
 432         outw(end, nic->ioaddr + IO_PORT);
 433         outw(length, nic->ioaddr + IO_PORT);
 434         outsw(nic->ioaddr + IO_PORT, d, ETH_ALEN / 2);
 435         outsw(nic->ioaddr + IO_PORT, nic->node_addr, ETH_ALEN / 2);
 436         type = htons(t);
 437         outsw(nic->ioaddr + IO_PORT, &type, sizeof(type) / 2);
 438         outsw(nic->ioaddr + IO_PORT, p, (s + 3) >> 1);
 439         /* A dummy read to flush the DRAM write pipeline */
 440         status = inw(nic->ioaddr + IO_PORT);
 441         outw(last, nic->ioaddr + xmt_bar);
 442         outb(XMT_CMD, nic->ioaddr);
 443         tx_start = last;
 444         tx_last = last;
 445         tx_end = end;
 446 #if     0
 447         printf("%d %d\n", tx_start, tx_end);
 448 #endif
 449         while (boguscount > 0) {
 450                 if (((status = inw(nic->ioaddr + IO_PORT)) & TX_DONE_BIT) == 0) {
 451                         udelay(40);
 452                         boguscount--;
 453                         continue;
 454                 }
 455                 if ((status & 0x2000) == 0) {
 456                         DBG("Transmit status %hX\n", status);
 457                 }
 458         }
 459 }
 460
 461 /**************************************************************************
 462 DISABLE - Turn off ethernet interface
 463 ***************************************************************************/
 464 static void eepro_disable ( struct nic *nic, struct isa_device *isa __unused ) {
 465         eepro_sw2bank0(nic->ioaddr);    /* Switch to bank 0 */
 466         /* Flush the Tx and disable Rx */
 467         outb(STOP_RCV_CMD, nic->ioaddr);
 468         tx_start = tx_end = (XMT_LOWER_LIMIT << 8);
 469         tx_last = 0;
 470         /* Reset the 82595 */
 471         eepro_full_reset(nic->ioaddr);
 472 }
 473
 474 /**************************************************************************
 475 DISABLE - Enable, Disable, or Force interrupts
 476 ***************************************************************************/
 477 static void eepro_irq(struct nic *nic __unused, irq_action_t action __unused)
 478 {
 479   switch ( action ) {
 480   case DISABLE :
 481     break;
 482   case ENABLE :
 483     break;
 484   case FORCE :
 485     break;
 486   }
 487 }
 488
 489 static int read_eeprom(uint16_t ioaddr, int location)
 490 {
 491         int             i;
 492         unsigned short  retval = 0;
 493         int             ee_addr = ioaddr + eeprom_reg;
 494         int             read_cmd = location | EE_READ_CMD;
 495         int             ctrl_val = EECS;
 496
 497         if (eepro == LAN595FX_10ISA) {
 498                 eepro_sw2bank1(ioaddr);
 499                 outb(0x00, ioaddr + STATUS_REG);
 500         }
 501         eepro_sw2bank2(ioaddr);
 502         outb(ctrl_val, ee_addr);
 503         /* shift the read command bits out */
 504         for (i = 8; i >= 0; i--) {
 505                 short outval = (read_cmd & (1 << i)) ? ctrl_val | EEDI : ctrl_val;
 506                 outb(outval, ee_addr);
 507                 outb(outval | EESK, ee_addr);   /* EEPROM clock tick */
 508                 eeprom_delay();
 509                 outb(outval, ee_addr);          /* finish EEPROM clock tick */
 510                 eeprom_delay();
 511         }
 512         outb(ctrl_val, ee_addr);
 513         for (i = 16; i > 0; i--) {
 514                 outb(ctrl_val | EESK, ee_addr);
 515                 eeprom_delay();
 516                 retval = (retval << 1) | ((inb(ee_addr) & EEDO) ? 1 : 0);
 517                 outb(ctrl_val, ee_addr);
 518                 eeprom_delay();
 519         }
 520         /* terminate the EEPROM access */
 521         ctrl_val &= ~EECS;
 522         outb(ctrl_val | EESK, ee_addr);
 523         eeprom_delay();
 524         outb(ctrl_val, ee_addr);
 525         eeprom_delay();
 526         eepro_sw2bank0(ioaddr);
 527         return (retval);
 528 }
 529
 530 static int eepro_probe1 ( isa_probe_addr_t ioaddr ) {
 531         int             id, counter;
 532
 533         id = inb(ioaddr + ID_REG);
 534         if ((id & ID_REG_MASK) != ID_REG_SIG)
 535                 return (0);
 536         counter = id & R_ROBIN_BITS;
 537         if (((id = inb(ioaddr + ID_REG)) & R_ROBIN_BITS) != (counter + 0x40))
 538                 return (0);
 539         /* yes the 82595 has been found */
 540         return (1);
 541 }
 542
 543 static struct nic_operations eepro_operations = {
 544         .connect        = dummy_connect,
 545         .poll           = eepro_poll,
 546         .transmit       = eepro_transmit,
 547         .irq            = eepro_irq,
 548
 549 };
 550
 551 /**************************************************************************
 552 PROBE - Look for an adapter, this routine's visible to the outside
 553 ***************************************************************************/
 554 static int eepro_probe ( struct nic *nic, struct isa_device *isa ) {
 555
 556         int             i, l_eepro = 0;
 557         union {
 558                 unsigned char   caddr[ETH_ALEN];
 559                 unsigned short  saddr[ETH_ALEN/2];
 560         } station_addr;
 561         const char *name;
 562
 563         nic->irqno  = 0;
 564         isa_fill_nic ( nic, isa );
 565         nic->ioaddr = isa->ioaddr;
 566
 567         station_addr.saddr[2] = read_eeprom(nic->ioaddr,2);
 568         if ( ( station_addr.saddr[2] == 0x0000 ) ||
 569              ( station_addr.saddr[2] == 0xFFFF ) ) {
 570                 l_eepro = 3;
 571                 eepro = LAN595FX_10ISA;
 572                 eeprom_reg= EEPROM_REG_10;
 573                 rcv_start = RCV_START_10;
 574                 xmt_lower_limit_reg = XMT_LOWER_LIMIT_REG_10;
 575                 xmt_upper_limit_reg = XMT_UPPER_LIMIT_REG_10;
 576                 station_addr.saddr[2] = read_eeprom(nic->ioaddr,2);
 577         }
 578         station_addr.saddr[1] = read_eeprom(nic->ioaddr,3);
 579         station_addr.saddr[0] = read_eeprom(nic->ioaddr,4);
 580         if (l_eepro)
 581                 name = "Intel EtherExpress 10 ISA";
 582         else if (read_eeprom(nic->ioaddr,7) == ee_FX_INT2IRQ) {
 583                 name = "Intel EtherExpress Pro/10+ ISA";
 584                 l_eepro = 2;
 585         } else if (station_addr.saddr[0] == SA_ADDR1) {
 586                 name = "Intel EtherExpress Pro/10 ISA";
 587                 l_eepro = 1;
 588         } else {
 589                 l_eepro = 0;
 590                 name = "Intel 82595-based LAN card";
 591         }
 592         station_addr.saddr[0] = swap16(station_addr.saddr[0]);
 593         station_addr.saddr[1] = swap16(station_addr.saddr[1]);
 594         station_addr.saddr[2] = swap16(station_addr.saddr[2]);
 595         for (i = 0; i < ETH_ALEN; i++) {
 596                 nic->node_addr[i] = station_addr.caddr[i];
 597         }
 598
 599         DBG ( "%s ioaddr %#hX, addr %s", name, nic->ioaddr, eth_ntoa ( nic->node_addr ) );
 600
 601         mem_start = RCV_LOWER_LIMIT << 8;
 602         if ((mem_end & 0x3F) < 3 || (mem_end & 0x3F) > 29)
 603                 mem_end = RCV_UPPER_LIMIT << 8;
 604         else {
 605                 mem_end = mem_end * 1024 + (RCV_LOWER_LIMIT << 8);
 606                 rcv_ram = mem_end - (RCV_LOWER_LIMIT << 8);
 607         }
 608         printf(", Rx mem %dK, if %s\n", (mem_end - mem_start) >> 10,
 609                 GetBit(read_eeprom(nic->ioaddr,5), ee_BNC_TPE) ? "BNC" : "TP");
 610
 611         eepro_reset(nic);
 612
 613         /* point to NIC specific routines */
 614         nic->nic_op     = &eepro_operations;
 615         return 1;
 616 }
 617
 618 static isa_probe_addr_t eepro_probe_addrs[] = {
 619         0x300, 0x210, 0x240, 0x280, 0x2C0, 0x200, 0x320, 0x340, 0x360,
 620 };
 621
 622 ISA_DRIVER ( eepro_driver, eepro_probe_addrs, eepro_probe1,
 623                      GENERIC_ISAPNP_VENDOR, 0x828a );
 624
 625 DRIVER ( "eepro", nic_driver, isa_driver, eepro_driver,
 626          eepro_probe, eepro_disable );
 627
 628 ISA_ROM ( "eepro", "Intel Etherexpress Pro/10" );