src/drivers/net/ns83820.c

   1 /**************************************************************************
   2 *    ns83820.c: Etherboot device driver for the National Semiconductor 83820
   3 *    Written 2004 by Timothy Legge <tlegge@rogers.com>
   4 *
   5 *    This program is free software; you can redistribute it and/or modify
   6 *    it under the terms of the GNU General Public License as published by
   7 *    the Free Software Foundation; either version 2 of the License, or
   8 *    (at your option) any later version.
   9 *
  10 *    This program is distributed in the hope that it will be useful,
  11 *    but WITHOUT ANY WARRANTY; without even the implied warranty of
  12 *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13 *    GNU General Public License for more details.
  14 *
  15 *    You should have received a copy of the GNU General Public License
  16 *    along with this program; if not, write to the Free Software
  17 *    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  18 *
  19 *    Portions of this code based on:
  20 *       ns83820.c by Benjamin LaHaise with contributions
  21 *               for Linux kernel 2.4.x.
  22 *
  23 *    Linux Driver Version 0.20, 20020610
  24 *
  25 *    This development of this Etherboot driver was funded by:
  26 *
  27 *    NXTV: http://www.nxtv.com/
  28 *
  29 *    REVISION HISTORY:
  30 *    ================
  31 *
  32 *    v1.0       02-16-2004      timlegge        Initial port of Linux driver
  33 *    v1.1       02-19-2004      timlegge        More rohbust transmit and poll
  34 *
  35 *    Indent Options: indent -kr -i8
  36 ***************************************************************************/
  37
  38 /* to get some global routines like printf */
  39 #include "etherboot.h"
  40 /* to get the interface to the body of the program */
  41 #include "nic.h"
  42 /* to get the PCI support functions, if this is a PCI NIC */
  43 #include <gpxe/pci.h>
  44
  45 #if ARCH == ia64                /* Support 64-bit addressing */
  46 #define USE_64BIT_ADDR
  47 #endif
  48
  49 //#define DDEBUG
  50 #ifdef DDEBUG
  51 #define dprintf(x) printf x
  52 #else
  53 #define dprintf(x)
  54 #endif
  55
  56 #define HZ 100
  57
  58 /* Condensed operations for readability. */
  59 #define virt_to_le32desc(addr)  cpu_to_le32(virt_to_bus(addr))
  60 #define le32desc_to_virt(addr)  bus_to_virt(le32_to_cpu(addr))
  61
  62 /* NIC specific static variables go here */
  63
  64 /* Global parameters.  See MODULE_PARM near the bottom. */
  65 // static int ihr = 2;
  66 static int reset_phy = 0;
  67 static int lnksts = 0;          /* CFG_LNKSTS bit polarity */
  68
  69 #if defined(CONFIG_HIGHMEM64G) || defined(__ia64__)
  70 #define USE_64BIT_ADDR  "+"
  71 #endif
  72
  73 #if defined(USE_64BIT_ADDR)
  74 #define TRY_DAC 1
  75 #else
  76 #define TRY_DAC 0
  77 #endif
  78
  79 /* tunables */
  80 #define RX_BUF_SIZE     1500    /* 8192 */
  81
  82 /* Must not exceed ~65000. */
  83 #define NR_RX_DESC      64
  84 #define NR_TX_DESC      1
  85
  86                    /* not tunable *//* Extra 6 bytes for 64 bit alignment (divisable by 8) */
  87 #define REAL_RX_BUF_SIZE (RX_BUF_SIZE + 14 + 6) /* rx/tx mac addr + type */
  88
  89 #define MIN_TX_DESC_FREE        8
  90
  91 /* register defines */
  92 #define CFGCS           0x04
  93
  94 #define CR_TXE          0x00000001
  95 #define CR_TXD          0x00000002
  96 /* Ramit : Here's a tip, don't do a RXD immediately followed by an RXE
  97  * The Receive engine skips one descriptor and moves
  98  * onto the next one!! */
  99 #define CR_RXE          0x00000004
 100 #define CR_RXD          0x00000008
 101 #define CR_TXR          0x00000010
 102 #define CR_RXR          0x00000020
 103 #define CR_SWI          0x00000080
 104 #define CR_RST          0x00000100
 105
 106 #define PTSCR_EEBIST_FAIL       0x00000001
 107 #define PTSCR_EEBIST_EN         0x00000002
 108 #define PTSCR_EELOAD_EN         0x00000004
 109 #define PTSCR_RBIST_FAIL        0x000001b8
 110 #define PTSCR_RBIST_DONE        0x00000200
 111 #define PTSCR_RBIST_EN          0x00000400
 112 #define PTSCR_RBIST_RST         0x00002000
 113
 114 #define MEAR_EEDI               0x00000001
 115 #define MEAR_EEDO               0x00000002
 116 #define MEAR_EECLK              0x00000004
 117 #define MEAR_EESEL              0x00000008
 118 #define MEAR_MDIO               0x00000010
 119 #define MEAR_MDDIR              0x00000020
 120 #define MEAR_MDC                0x00000040
 121
 122 #define ISR_TXDESC3     0x40000000
 123 #define ISR_TXDESC2     0x20000000
 124 #define ISR_TXDESC1     0x10000000
 125 #define ISR_TXDESC0     0x08000000
 126 #define ISR_RXDESC3     0x04000000
 127 #define ISR_RXDESC2     0x02000000
 128 #define ISR_RXDESC1     0x01000000
 129 #define ISR_RXDESC0     0x00800000
 130 #define ISR_TXRCMP      0x00400000
 131 #define ISR_RXRCMP      0x00200000
 132 #define ISR_DPERR       0x00100000
 133 #define ISR_SSERR       0x00080000
 134 #define ISR_RMABT       0x00040000
 135 #define ISR_RTABT       0x00020000
 136 #define ISR_RXSOVR      0x00010000
 137 #define ISR_HIBINT      0x00008000
 138 #define ISR_PHY         0x00004000
 139 #define ISR_PME         0x00002000
 140 #define ISR_SWI         0x00001000
 141 #define ISR_MIB         0x00000800
 142 #define ISR_TXURN       0x00000400
 143 #define ISR_TXIDLE      0x00000200
 144 #define ISR_TXERR       0x00000100
 145 #define ISR_TXDESC      0x00000080
 146 #define ISR_TXOK        0x00000040
 147 #define ISR_RXORN       0x00000020
 148 #define ISR_RXIDLE      0x00000010
 149 #define ISR_RXEARLY     0x00000008
 150 #define ISR_RXERR       0x00000004
 151 #define ISR_RXDESC      0x00000002
 152 #define ISR_RXOK        0x00000001
 153
 154 #define TXCFG_CSI       0x80000000
 155 #define TXCFG_HBI       0x40000000
 156 #define TXCFG_MLB       0x20000000
 157 #define TXCFG_ATP       0x10000000
 158 #define TXCFG_ECRETRY   0x00800000
 159 #define TXCFG_BRST_DIS  0x00080000
 160 #define TXCFG_MXDMA1024 0x00000000
 161 #define TXCFG_MXDMA512  0x00700000
 162 #define TXCFG_MXDMA256  0x00600000
 163 #define TXCFG_MXDMA128  0x00500000
 164 #define TXCFG_MXDMA64   0x00400000
 165 #define TXCFG_MXDMA32   0x00300000
 166 #define TXCFG_MXDMA16   0x00200000
 167 #define TXCFG_MXDMA8    0x00100000
 168
 169 #define CFG_LNKSTS      0x80000000
 170 #define CFG_SPDSTS      0x60000000
 171 #define CFG_SPDSTS1     0x40000000
 172 #define CFG_SPDSTS0     0x20000000
 173 #define CFG_DUPSTS      0x10000000
 174 #define CFG_TBI_EN      0x01000000
 175 #define CFG_MODE_1000   0x00400000
 176 /* Ramit : Dont' ever use AUTO_1000, it never works and is buggy.
 177  * Read the Phy response and then configure the MAC accordingly */
 178 #define CFG_AUTO_1000   0x00200000
 179 #define CFG_PINT_CTL    0x001c0000
 180 #define CFG_PINT_DUPSTS 0x00100000
 181 #define CFG_PINT_LNKSTS 0x00080000
 182 #define CFG_PINT_SPDSTS 0x00040000
 183 #define CFG_TMRTEST     0x00020000
 184 #define CFG_MRM_DIS     0x00010000
 185 #define CFG_MWI_DIS     0x00008000
 186 #define CFG_T64ADDR     0x00004000
 187 #define CFG_PCI64_DET   0x00002000
 188 #define CFG_DATA64_EN   0x00001000
 189 #define CFG_M64ADDR     0x00000800
 190 #define CFG_PHY_RST     0x00000400
 191 #define CFG_PHY_DIS     0x00000200
 192 #define CFG_EXTSTS_EN   0x00000100
 193 #define CFG_REQALG      0x00000080
 194 #define CFG_SB          0x00000040
 195 #define CFG_POW         0x00000020
 196 #define CFG_EXD         0x00000010
 197 #define CFG_PESEL       0x00000008
 198 #define CFG_BROM_DIS    0x00000004
 199 #define CFG_EXT_125     0x00000002
 200 #define CFG_BEM         0x00000001
 201
 202 #define EXTSTS_UDPPKT   0x00200000
 203 #define EXTSTS_TCPPKT   0x00080000
 204 #define EXTSTS_IPPKT    0x00020000
 205
 206 #define SPDSTS_POLARITY (CFG_SPDSTS1 | CFG_SPDSTS0 | CFG_DUPSTS | (lnksts ? CFG_LNKSTS : 0))
 207
 208 #define MIBC_MIBS       0x00000008
 209 #define MIBC_ACLR       0x00000004
 210 #define MIBC_FRZ        0x00000002
 211 #define MIBC_WRN        0x00000001
 212
 213 #define PCR_PSEN        (1 << 31)
 214 #define PCR_PS_MCAST    (1 << 30)
 215 #define PCR_PS_DA       (1 << 29)
 216 #define PCR_STHI_8      (3 << 23)
 217 #define PCR_STLO_4      (1 << 23)
 218 #define PCR_FFHI_8K     (3 << 21)
 219 #define PCR_FFLO_4K     (1 << 21)
 220 #define PCR_PAUSE_CNT   0xFFFE
 221
 222 #define RXCFG_AEP       0x80000000
 223 #define RXCFG_ARP       0x40000000
 224 #define RXCFG_STRIPCRC  0x20000000
 225 #define RXCFG_RX_FD     0x10000000
 226 #define RXCFG_ALP       0x08000000
 227 #define RXCFG_AIRL      0x04000000
 228 #define RXCFG_MXDMA512  0x00700000
 229 #define RXCFG_DRTH      0x0000003e
 230 #define RXCFG_DRTH0     0x00000002
 231
 232 #define RFCR_RFEN       0x80000000
 233 #define RFCR_AAB        0x40000000
 234 #define RFCR_AAM        0x20000000
 235 #define RFCR_AAU        0x10000000
 236 #define RFCR_APM        0x08000000
 237 #define RFCR_APAT       0x07800000
 238 #define RFCR_APAT3      0x04000000
 239 #define RFCR_APAT2      0x02000000
 240 #define RFCR_APAT1      0x01000000
 241 #define RFCR_APAT0      0x00800000
 242 #define RFCR_AARP       0x00400000
 243 #define RFCR_MHEN       0x00200000
 244 #define RFCR_UHEN       0x00100000
 245 #define RFCR_ULM        0x00080000
 246
 247 #define VRCR_RUDPE      0x00000080
 248 #define VRCR_RTCPE      0x00000040
 249 #define VRCR_RIPE       0x00000020
 250 #define VRCR_IPEN       0x00000010
 251 #define VRCR_DUTF       0x00000008
 252 #define VRCR_DVTF       0x00000004
 253 #define VRCR_VTREN      0x00000002
 254 #define VRCR_VTDEN      0x00000001
 255
 256 #define VTCR_PPCHK      0x00000008
 257 #define VTCR_GCHK       0x00000004
 258 #define VTCR_VPPTI      0x00000002
 259 #define VTCR_VGTI       0x00000001
 260
 261 #define CR              0x00
 262 #define CFG             0x04
 263 #define MEAR            0x08
 264 #define PTSCR           0x0c
 265 #define ISR             0x10
 266 #define IMR             0x14
 267 #define IER             0x18
 268 #define IHR             0x1c
 269 #define TXDP            0x20
 270 #define TXDP_HI         0x24
 271 #define TXCFG           0x28
 272 #define GPIOR           0x2c
 273 #define RXDP            0x30
 274 #define RXDP_HI         0x34
 275 #define RXCFG           0x38
 276 #define PQCR            0x3c
 277 #define WCSR            0x40
 278 #define PCR             0x44
 279 #define RFCR            0x48
 280 #define RFDR            0x4c
 281
 282 #define SRR             0x58
 283
 284 #define VRCR            0xbc
 285 #define VTCR            0xc0
 286 #define VDR             0xc4
 287 #define CCSR            0xcc
 288
 289 #define TBICR           0xe0
 290 #define TBISR           0xe4
 291 #define TANAR           0xe8
 292 #define TANLPAR         0xec
 293 #define TANER           0xf0
 294 #define TESR            0xf4
 295
 296 #define TBICR_MR_AN_ENABLE      0x00001000
 297 #define TBICR_MR_RESTART_AN     0x00000200
 298
 299 #define TBISR_MR_LINK_STATUS    0x00000020
 300 #define TBISR_MR_AN_COMPLETE    0x00000004
 301
 302 #define TANAR_PS2               0x00000100
 303 #define TANAR_PS1               0x00000080
 304 #define TANAR_HALF_DUP          0x00000040
 305 #define TANAR_FULL_DUP          0x00000020
 306
 307 #define GPIOR_GP5_OE            0x00000200
 308 #define GPIOR_GP4_OE            0x00000100
 309 #define GPIOR_GP3_OE            0x00000080
 310 #define GPIOR_GP2_OE            0x00000040
 311 #define GPIOR_GP1_OE            0x00000020
 312 #define GPIOR_GP3_OUT           0x00000004
 313 #define GPIOR_GP1_OUT           0x00000001
 314
 315 #define LINK_AUTONEGOTIATE      0x01
 316 #define LINK_DOWN               0x02
 317 #define LINK_UP                 0x04
 318
 319
 320 #define __kick_rx()     writel(CR_RXE, ns->base + CR)
 321
 322 #define kick_rx() do { \
 323         dprintf(("kick_rx: maybe kicking\n")); \
 324                 writel(virt_to_le32desc(&rx_ring[ns->cur_rx]), ns->base + RXDP); \
 325                 if (ns->next_rx == ns->next_empty) \
 326                         printf("uh-oh: next_rx == next_empty???\n"); \
 327                 __kick_rx(); \
 328 } while(0)
 329
 330
 331 #ifdef USE_64BIT_ADDR
 332 #define HW_ADDR_LEN     8
 333 #else
 334 #define HW_ADDR_LEN     4
 335 #endif
 336
 337 #define CMDSTS_OWN      0x80000000
 338 #define CMDSTS_MORE     0x40000000
 339 #define CMDSTS_INTR     0x20000000
 340 #define CMDSTS_ERR      0x10000000
 341 #define CMDSTS_OK       0x08000000
 342 #define CMDSTS_LEN_MASK 0x0000ffff
 343
 344 #define CMDSTS_DEST_MASK        0x01800000
 345 #define CMDSTS_DEST_SELF        0x00800000
 346 #define CMDSTS_DEST_MULTI       0x01000000
 347
 348 #define DESC_SIZE       8       /* Should be cache line sized */
 349
 350 #ifdef USE_64BIT_ADDR
 351 struct ring_desc {
 352         uint64_t link;
 353         uint64_t bufptr;
 354         u32 cmdsts;
 355         u32 extsts;             /* Extended status field */
 356 };
 357 #else
 358 struct ring_desc {
 359         u32 link;
 360         u32 bufptr;
 361         u32 cmdsts;
 362         u32 extsts;             /* Extended status field */
 363 };
 364 #endif
 365
 366 /* Private Storage for the NIC */
 367 struct ns83820_private {
 368         u8 *base;
 369         int up;
 370         long idle;
 371         u32 *next_rx_desc;
 372         u16 next_rx, next_empty;
 373         u32 cur_rx;
 374         u32 *descs;
 375         unsigned ihr;
 376         u32 CFG_cache;
 377         u32 MEAR_cache;
 378         u32 IMR_cache;
 379         int linkstate;
 380         u16 tx_done_idx;
 381         u16 tx_idx;
 382         u16 tx_intr_idx;
 383         u32 phy_descs;
 384         u32 *tx_descs;
 385
 386 } nsx;
 387 static struct ns83820_private *ns;
 388
 389 /* Define the TX and RX Descriptor and Buffers */
 390 struct {
 391         struct ring_desc tx_ring[NR_TX_DESC] __attribute__ ((aligned(8)));
 392         unsigned char txb[NR_TX_DESC * REAL_RX_BUF_SIZE];
 393         struct ring_desc rx_ring[NR_RX_DESC] __attribute__ ((aligned(8)));
 394         unsigned char rxb[NR_RX_DESC * REAL_RX_BUF_SIZE]
 395         __attribute__ ((aligned(8)));
 396 } ns83820_bufs __shared;
 397 #define tx_ring ns83820_bufs.tx_ring
 398 #define rx_ring ns83820_bufs.rx_ring
 399 #define txb ns83820_bufs.txb
 400 #define rxb ns83820_bufs.rxb
 401
 402 static void phy_intr(struct nic *nic __unused)
 403 {
 404         static char *speeds[] =
 405             { "10", "100", "1000", "1000(?)", "1000F" };
 406         u32 cfg, new_cfg;
 407         u32 tbisr, tanar, tanlpar;
 408         int speed, fullduplex, newlinkstate;
 409
 410         cfg = readl(ns->base + CFG) ^ SPDSTS_POLARITY;
 411         if (ns->CFG_cache & CFG_TBI_EN) {
 412                 /* we have an optical transceiver */
 413                 tbisr = readl(ns->base + TBISR);
 414                 tanar = readl(ns->base + TANAR);
 415                 tanlpar = readl(ns->base + TANLPAR);
 416                 dprintf(("phy_intr: tbisr=%hX, tanar=%hX, tanlpar=%hX\n",
 417                          tbisr, tanar, tanlpar));
 418
 419                 if ((fullduplex = (tanlpar & TANAR_FULL_DUP)
 420                      && (tanar & TANAR_FULL_DUP))) {
 421
 422                         /* both of us are full duplex */
 423                         writel(readl(ns->base + TXCFG)
 424                                | TXCFG_CSI | TXCFG_HBI | TXCFG_ATP,
 425                                ns->base + TXCFG);
 426                         writel(readl(ns->base + RXCFG) | RXCFG_RX_FD,
 427                                ns->base + RXCFG);
 428                         /* Light up full duplex LED */
 429                         writel(readl(ns->base + GPIOR) | GPIOR_GP1_OUT,
 430                                ns->base + GPIOR);
 431
 432                 } else if (((tanlpar & TANAR_HALF_DUP)
 433                             && (tanar & TANAR_HALF_DUP))
 434                            || ((tanlpar & TANAR_FULL_DUP)
 435                                && (tanar & TANAR_HALF_DUP))
 436                            || ((tanlpar & TANAR_HALF_DUP)
 437                                && (tanar & TANAR_FULL_DUP))) {
 438
 439                         /* one or both of us are half duplex */
 440                         writel((readl(ns->base + TXCFG)
 441                                 & ~(TXCFG_CSI | TXCFG_HBI)) | TXCFG_ATP,
 442                                ns->base + TXCFG);
 443                         writel(readl(ns->base + RXCFG) & ~RXCFG_RX_FD,
 444                                ns->base + RXCFG);
 445                         /* Turn off full duplex LED */
 446                         writel(readl(ns->base + GPIOR) & ~GPIOR_GP1_OUT,
 447                                ns->base + GPIOR);
 448                 }
 449
 450                 speed = 4;      /* 1000F */
 451
 452         } else {
 453                 /* we have a copper transceiver */
 454                 new_cfg =
 455                     ns->CFG_cache & ~(CFG_SB | CFG_MODE_1000 | CFG_SPDSTS);
 456
 457                 if (cfg & CFG_SPDSTS1)
 458                         new_cfg |= CFG_MODE_1000;
 459                 else
 460                         new_cfg &= ~CFG_MODE_1000;
 461
 462                 speed = ((cfg / CFG_SPDSTS0) & 3);
 463                 fullduplex = (cfg & CFG_DUPSTS);
 464
 465                 if (fullduplex)
 466                         new_cfg |= CFG_SB;
 467
 468                 if ((cfg & CFG_LNKSTS) &&
 469                     ((new_cfg ^ ns->CFG_cache) & CFG_MODE_1000)) {
 470                         writel(new_cfg, ns->base + CFG);
 471                         ns->CFG_cache = new_cfg;
 472                 }
 473
 474                 ns->CFG_cache &= ~CFG_SPDSTS;
 475                 ns->CFG_cache |= cfg & CFG_SPDSTS;
 476         }
 477
 478         newlinkstate = (cfg & CFG_LNKSTS) ? LINK_UP : LINK_DOWN;
 479
 480         if (newlinkstate & LINK_UP && ns->linkstate != newlinkstate) {
 481                 printf("link now %s mbps, %s duplex and up.\n",
 482                        speeds[speed], fullduplex ? "full" : "half");
 483         } else if (newlinkstate & LINK_DOWN
 484                    && ns->linkstate != newlinkstate) {
 485                 printf("link now down.\n");
 486         }
 487         ns->linkstate = newlinkstate;
 488 }
 489 static void ns83820_set_multicast(struct nic *nic __unused);
 490 static void ns83820_setup_rx(struct nic *nic)
 491 {
 492         unsigned i;
 493         ns->idle = 1;
 494         ns->next_rx = 0;
 495         ns->next_rx_desc = ns->descs;
 496         ns->next_empty = 0;
 497         ns->cur_rx = 0;
 498
 499
 500         for (i = 0; i < NR_RX_DESC; i++) {
 501                 rx_ring[i].link = virt_to_le32desc(&rx_ring[i + 1]);
 502                 rx_ring[i].bufptr =
 503                     virt_to_le32desc(&rxb[i * REAL_RX_BUF_SIZE]);
 504                 rx_ring[i].cmdsts = cpu_to_le32(REAL_RX_BUF_SIZE);
 505                 rx_ring[i].extsts = cpu_to_le32(0);
 506         }
 507 //      No need to wrap the ring
 508 //      rx_ring[i].link = virt_to_le32desc(&rx_ring[0]);
 509         writel(0, ns->base + RXDP_HI);
 510         writel(virt_to_le32desc(&rx_ring[0]), ns->base + RXDP);
 511
 512         dprintf(("starting receiver\n"));
 513
 514         writel(0x0001, ns->base + CCSR);
 515         writel(0, ns->base + RFCR);
 516         writel(0x7fc00000, ns->base + RFCR);
 517         writel(0xffc00000, ns->base + RFCR);
 518
 519         ns->up = 1;
 520
 521         phy_intr(nic);
 522
 523         /* Okay, let it rip */
 524         ns->IMR_cache |= ISR_PHY;
 525         ns->IMR_cache |= ISR_RXRCMP;
 526         //dev->IMR_cache |= ISR_RXERR;
 527         //dev->IMR_cache |= ISR_RXOK;
 528         ns->IMR_cache |= ISR_RXORN;
 529         ns->IMR_cache |= ISR_RXSOVR;
 530         ns->IMR_cache |= ISR_RXDESC;
 531         ns->IMR_cache |= ISR_RXIDLE;
 532         ns->IMR_cache |= ISR_TXDESC;
 533         ns->IMR_cache |= ISR_TXIDLE;
 534
 535         // No reason to enable interupts...
 536         // writel(ns->IMR_cache, ns->base + IMR);
 537         // writel(1, ns->base + IER);
 538         ns83820_set_multicast(nic);
 539         kick_rx();
 540 }
 541
 542
 543 static void ns83820_do_reset(struct nic *nic __unused, u32 which)
 544 {
 545         dprintf(("resetting chip...\n"));
 546         writel(which, ns->base + CR);
 547         do {
 548
 549         } while (readl(ns->base + CR) & which);
 550         dprintf(("okay!\n"));
 551 }
 552
 553 static void ns83820_reset(struct nic *nic)
 554 {
 555         unsigned i;
 556         dprintf(("ns83820_reset\n"));
 557
 558         writel(0, ns->base + PQCR);
 559
 560         ns83820_setup_rx(nic);
 561
 562         for (i = 0; i < NR_TX_DESC; i++) {
 563                 tx_ring[i].link = 0;
 564                 tx_ring[i].bufptr = 0;
 565                 tx_ring[i].cmdsts = cpu_to_le32(0);
 566                 tx_ring[i].extsts = cpu_to_le32(0);
 567         }
 568
 569         ns->tx_idx = 0;
 570         ns->tx_done_idx = 0;
 571         writel(0, ns->base + TXDP_HI);
 572         return;
 573 }
 574 static void ns83820_getmac(struct nic *nic __unused, u8 * mac)
 575 {
 576         unsigned i;
 577         for (i = 0; i < 3; i++) {
 578                 u32 data;
 579                 /* Read from the perfect match memory: this is loaded by
 580                  * the chip from the EEPROM via the EELOAD self test.
 581                  */
 582                 writel(i * 2, ns->base + RFCR);
 583                 data = readl(ns->base + RFDR);
 584                 *mac++ = data;
 585                 *mac++ = data >> 8;
 586         }
 587 }
 588
 589 static void ns83820_set_multicast(struct nic *nic __unused)
 590 {
 591         u8 *rfcr = ns->base + RFCR;
 592         u32 and_mask = 0xffffffff;
 593         u32 or_mask = 0;
 594         u32 val;
 595
 596         /* Support Multicast */
 597         and_mask &= ~(RFCR_AAU | RFCR_AAM);
 598         or_mask |= RFCR_AAM;
 599         val = (readl(rfcr) & and_mask) | or_mask;
 600         /* Ramit : RFCR Write Fix doc says RFEN must be 0 modify other bits */
 601         writel(val & ~RFCR_RFEN, rfcr);
 602         writel(val, rfcr);
 603
 604 }
 605 static void ns83820_run_bist(struct nic *nic __unused, const char *name,
 606                              u32 enable, u32 done, u32 fail)
 607 {
 608         int timed_out = 0;
 609         long start;
 610         u32 status;
 611         int loops = 0;
 612
 613         dprintf(("start %s\n", name))
 614
 615             start = currticks();
 616
 617         writel(enable, ns->base + PTSCR);
 618         for (;;) {
 619                 loops++;
 620                 status = readl(ns->base + PTSCR);
 621                 if (!(status & enable))
 622                         break;
 623                 if (status & done)
 624                         break;
 625                 if (status & fail)
 626                         break;
 627                 if ((currticks() - start) >= HZ) {
 628                         timed_out = 1;
 629                         break;
 630                 }
 631         }
 632
 633         if (status & fail)
 634           printf("%s failed! (0x%hX & 0x%hX)\n", name, (unsigned int) status,
 635                  (unsigned int) fail);
 636         else if (timed_out)
 637                 printf("run_bist %s timed out! (%hX)\n", name, (unsigned int) status);
 638         dprintf(("done %s in %d loops\n", name, loops));
 639 }
 640
 641 /*************************************
 642 Check Link
 643 *************************************/
 644 static void ns83820_check_intr(struct nic *nic) {
 645         int i;
 646         u32 isr = readl(ns->base + ISR);
 647         if(ISR_PHY & isr)
 648                 phy_intr(nic);
 649         if(( ISR_RXIDLE | ISR_RXDESC | ISR_RXERR) & isr)
 650                 kick_rx();
 651         for (i = 0; i < NR_RX_DESC; i++) {
 652                 if (rx_ring[i].cmdsts == CMDSTS_OWN) {
 653 //                      rx_ring[i].link = virt_to_le32desc(&rx_ring[i + 1]);
 654                         rx_ring[i].cmdsts = cpu_to_le32(REAL_RX_BUF_SIZE);
 655                 }
 656         }
 657 }
 658 /**************************************************************************
 659 POLL - Wait for a frame
 660 ***************************************************************************/
 661 static int ns83820_poll(struct nic *nic, int retrieve)
 662 {
 663         /* return true if there's an ethernet packet ready to read */
 664         /* nic->packet should contain data on return */
 665         /* nic->packetlen should contain length of data */
 666         u32 cmdsts;
 667         int entry = ns->cur_rx;
 668
 669         ns83820_check_intr(nic);
 670
 671         cmdsts = le32_to_cpu(rx_ring[entry].cmdsts);
 672
 673         if ( ! ( (CMDSTS_OWN & (cmdsts)) && (cmdsts != (CMDSTS_OWN)) ) )
 674           return 0;
 675
 676         if ( ! retrieve ) return 1;
 677
 678         if (! (CMDSTS_OK & cmdsts) )
 679           return 0;
 680
 681         nic->packetlen = cmdsts & 0xffff;
 682         memcpy(nic->packet,
 683                rxb + (entry * REAL_RX_BUF_SIZE),
 684                nic->packetlen);
 685         //                      rx_ring[entry].link = 0;
 686         rx_ring[entry].cmdsts = cpu_to_le32(CMDSTS_OWN);
 687
 688         ns->cur_rx = ++ns->cur_rx % NR_RX_DESC;
 689
 690         if (ns->cur_rx == 0)    /* We have wrapped the ring */
 691           kick_rx();
 692
 693         return 1;
 694 }
 695
 696 static inline void kick_tx(struct nic *nic __unused)
 697 {
 698         dprintf(("kick_tx\n"));
 699         writel(CR_TXE, ns->base + CR);
 700 }
 701
 702 /**************************************************************************
 703 TRANSMIT - Transmit a frame
 704 ***************************************************************************/
 705 static void ns83820_transmit(struct nic *nic, const char *d,    /* Destination */
 706                              unsigned int t,    /* Type */
 707                              unsigned int s,    /* size */
 708                              const char *p)
 709 {                               /* Packet */
 710         /* send the packet to destination */
 711
 712         u16 nstype;
 713         u32 cmdsts, extsts;
 714         int cur_tx = 0;
 715         u32 isr = readl(ns->base + ISR);
 716         if (ISR_TXIDLE & isr)
 717                 kick_tx(nic);
 718         /* point to the current txb incase multiple tx_rings are used */
 719         memcpy(txb, d, ETH_ALEN);
 720         memcpy(txb + ETH_ALEN, nic->node_addr, ETH_ALEN);
 721         nstype = htons((u16) t);
 722         memcpy(txb + 2 * ETH_ALEN, (u8 *) & nstype, 2);
 723         memcpy(txb + ETH_HLEN, p, s);
 724         s += ETH_HLEN;
 725         s &= 0x0FFF;
 726         while (s < ETH_ZLEN)
 727                 txb[s++] = '\0';
 728
 729         /* Setup the transmit descriptor */
 730         extsts = 0;
 731         extsts |= EXTSTS_UDPPKT;
 732
 733         tx_ring[cur_tx].bufptr = virt_to_le32desc(&txb);
 734         tx_ring[cur_tx].extsts = cpu_to_le32(extsts);
 735
 736         cmdsts = cpu_to_le32(0);
 737         cmdsts |= cpu_to_le32(CMDSTS_OWN | s);
 738         tx_ring[cur_tx].cmdsts = cpu_to_le32(cmdsts);
 739
 740         writel(virt_to_le32desc(&tx_ring[0]), ns->base + TXDP);
 741         kick_tx(nic);
 742 }
 743
 744 /**************************************************************************
 745 DISABLE - Turn off ethernet interface
 746 ***************************************************************************/
 747 static void ns83820_disable ( struct nic *nic ) {
 748
 749         /* put the card in its initial state */
 750         /* This function serves 3 purposes.
 751          * This disables DMA and interrupts so we don't receive
 752          *  unexpected packets or interrupts from the card after
 753          *  etherboot has finished.
 754          * This frees resources so etherboot may use
 755          *  this driver on another interface
 756          * This allows etherboot to reinitialize the interface
 757          *  if something is something goes wrong.
 758          */
 759         /* disable interrupts */
 760         writel(0, ns->base + IMR);
 761         writel(0, ns->base + IER);
 762         readl(ns->base + IER);
 763
 764         ns->up = 0;
 765
 766         ns83820_do_reset(nic, CR_RST);
 767
 768         ns->IMR_cache &=
 769             ~(ISR_RXOK | ISR_RXDESC | ISR_RXERR | ISR_RXEARLY |
 770               ISR_RXIDLE);
 771         writel(ns->IMR_cache, ns->base + IMR);
 772
 773         /* touch the pci bus... */
 774         readl(ns->base + IMR);
 775
 776         /* assumes the transmitter is already disabled and reset */
 777         writel(0, ns->base + RXDP_HI);
 778         writel(0, ns->base + RXDP);
 779 }
 780
 781 /**************************************************************************
 782 IRQ - Enable, Disable, or Force interrupts
 783 ***************************************************************************/
 784 static void ns83820_irq(struct nic *nic __unused, irq_action_t action __unused)
 785 {
 786   switch ( action ) {
 787   case DISABLE :
 788     break;
 789   case ENABLE :
 790     break;
 791   case FORCE :
 792     break;
 793   }
 794 }
 795
 796 static struct nic_operations ns83820_operations = {
 797         .connect        = dummy_connect,
 798         .poll           = ns83820_poll,
 799         .transmit       = ns83820_transmit,
 800         .irq            = ns83820_irq,
 801
 802 };
 803
 804 static struct pci_device_id ns83820_nics[] = {
 805         PCI_ROM(0x100b, 0x0022, "ns83820", "National Semiconductor 83820"),
 806 };
 807
 808 PCI_DRIVER ( ns83820_driver, ns83820_nics, PCI_NO_CLASS );
 809
 810 /**************************************************************************
 811 PROBE - Look for an adapter, this routine's visible to the outside
 812 ***************************************************************************/
 813
 814 #define board_found 1
 815 #define valid_link 0
 816 static int ns83820_probe ( struct nic *nic, struct pci_device *pci ) {
 817
 818         long addr;
 819         int using_dac = 0;
 820
 821         if (pci->ioaddr == 0)
 822                 return 0;
 823
 824         printf("ns83820.c: Found %s, vendor=0x%hX, device=0x%hX\n",
 825                pci->driver_name, pci->vendor, pci->device);
 826
 827         /* point to private storage */
 828         ns = &nsx;
 829
 830         adjust_pci_device(pci);
 831
 832         addr = pci_bar_start(pci, PCI_BASE_ADDRESS_1);
 833
 834         ns->base = ioremap(addr, (1UL << 12));
 835
 836         if (!ns->base)
 837                 return 0;
 838
 839         nic->irqno  = 0;
 840         pci_fill_nic ( nic, pci );
 841         nic->ioaddr = pci->ioaddr & ~3;
 842
 843         /* disable interrupts */
 844         writel(0, ns->base + IMR);
 845         writel(0, ns->base + IER);
 846         readl(ns->base + IER);
 847
 848         ns->IMR_cache = 0;
 849
 850         ns83820_do_reset(nic, CR_RST);
 851
 852         /* Must reset the ram bist before running it */
 853         writel(PTSCR_RBIST_RST, ns->base + PTSCR);
 854         ns83820_run_bist(nic, "sram bist", PTSCR_RBIST_EN,
 855                          PTSCR_RBIST_DONE, PTSCR_RBIST_FAIL);
 856         ns83820_run_bist(nic, "eeprom bist", PTSCR_EEBIST_EN, 0,
 857                          PTSCR_EEBIST_FAIL);
 858         ns83820_run_bist(nic, "eeprom load", PTSCR_EELOAD_EN, 0, 0);
 859
 860         /* I love config registers */
 861         ns->CFG_cache = readl(ns->base + CFG);
 862
 863         if ((ns->CFG_cache & CFG_PCI64_DET)) {
 864                 printf("%s: detected 64 bit PCI data bus.\n", pci->driver_name);
 865                 /*dev->CFG_cache |= CFG_DATA64_EN; */
 866                 if (!(ns->CFG_cache & CFG_DATA64_EN))
 867                         printf
 868                             ("%s: EEPROM did not enable 64 bit bus.  Disabled.\n",
 869                              pci->driver_name);
 870         } else
 871                 ns->CFG_cache &= ~(CFG_DATA64_EN);
 872
 873         ns->CFG_cache &= (CFG_TBI_EN | CFG_MRM_DIS | CFG_MWI_DIS |
 874                           CFG_T64ADDR | CFG_DATA64_EN | CFG_EXT_125 |
 875                           CFG_M64ADDR);
 876         ns->CFG_cache |=
 877             CFG_PINT_DUPSTS | CFG_PINT_LNKSTS | CFG_PINT_SPDSTS |
 878             CFG_EXTSTS_EN | CFG_EXD | CFG_PESEL;
 879         ns->CFG_cache |= CFG_REQALG;
 880         ns->CFG_cache |= CFG_POW;
 881         ns->CFG_cache |= CFG_TMRTEST;
 882
 883         /* When compiled with 64 bit addressing, we must always enable
 884          * the 64 bit descriptor format.
 885          */
 886 #ifdef USE_64BIT_ADDR
 887         ns->CFG_cache |= CFG_M64ADDR;
 888 #endif
 889
 890 //FIXME: Enable section on dac or remove this
 891         if (using_dac)
 892                 ns->CFG_cache |= CFG_T64ADDR;
 893
 894         /* Big endian mode does not seem to do what the docs suggest */
 895         ns->CFG_cache &= ~CFG_BEM;
 896
 897         /* setup optical transceiver if we have one */
 898         if (ns->CFG_cache & CFG_TBI_EN) {
 899                 dprintf(("%s: enabling optical transceiver\n", pci->driver_name));
 900                 writel(readl(ns->base + GPIOR) | 0x3e8, ns->base + GPIOR);
 901
 902                 /* setup auto negotiation feature advertisement */
 903                 writel(readl(ns->base + TANAR)
 904                        | TANAR_HALF_DUP | TANAR_FULL_DUP,
 905                        ns->base + TANAR);
 906
 907                 /* start auto negotiation */
 908                 writel(TBICR_MR_AN_ENABLE | TBICR_MR_RESTART_AN,
 909                        ns->base + TBICR);
 910                 writel(TBICR_MR_AN_ENABLE, ns->base + TBICR);
 911                 ns->linkstate = LINK_AUTONEGOTIATE;
 912
 913                 ns->CFG_cache |= CFG_MODE_1000;
 914         }
 915         writel(ns->CFG_cache, ns->base + CFG);
 916         dprintf(("CFG: %hX\n", ns->CFG_cache));
 917
 918         /* FIXME: reset_phy is defaulted to 0, should we reset anyway? */
 919         if (reset_phy) {
 920                 dprintf(("%s: resetting phy\n", pci->driver_name));
 921                 writel(ns->CFG_cache | CFG_PHY_RST, ns->base + CFG);
 922                 writel(ns->CFG_cache, ns->base + CFG);
 923         }
 924 #if 0                           /* Huh?  This sets the PCI latency register.  Should be done via
 925                                  * the PCI layer.  FIXME.
 926                                  */
 927         if (readl(dev->base + SRR))
 928                 writel(readl(dev->base + 0x20c) | 0xfe00,
 929                        dev->base + 0x20c);
 930 #endif
 931
 932         /* Note!  The DMA burst size interacts with packet
 933          * transmission, such that the largest packet that
 934          * can be transmitted is 8192 - FLTH - burst size.
 935          * If only the transmit fifo was larger...
 936          */
 937         /* Ramit : 1024 DMA is not a good idea, it ends up banging
 938          * some DELL and COMPAQ SMP systems */
 939         writel(TXCFG_CSI | TXCFG_HBI | TXCFG_ATP | TXCFG_MXDMA512
 940                | ((1600 / 32) * 0x100), ns->base + TXCFG);
 941
 942         /* Set Rx to full duplex, don't accept runt, errored, long or length
 943          * range errored packets.  Use 512 byte DMA.
 944          */
 945         /* Ramit : 1024 DMA is not a good idea, it ends up banging
 946          * some DELL and COMPAQ SMP systems
 947          * Turn on ALP, only we are accpeting Jumbo Packets */
 948         writel(RXCFG_AEP | RXCFG_ARP | RXCFG_AIRL | RXCFG_RX_FD
 949                | RXCFG_STRIPCRC
 950                //| RXCFG_ALP
 951                | (RXCFG_MXDMA512) | 0, ns->base + RXCFG);
 952
 953         /* Disable priority queueing */
 954         writel(0, ns->base + PQCR);
 955
 956         /* Enable IP checksum validation and detetion of VLAN headers.
 957          * Note: do not set the reject options as at least the 0x102
 958          * revision of the chip does not properly accept IP fragments
 959          * at least for UDP.
 960          */
 961         /* Ramit : Be sure to turn on RXCFG_ARP if VLAN's are enabled, since
 962          * the MAC it calculates the packetsize AFTER stripping the VLAN
 963          * header, and if a VLAN Tagged packet of 64 bytes is received (like
 964          * a ping with a VLAN header) then the card, strips the 4 byte VLAN
 965          * tag and then checks the packet size, so if RXCFG_ARP is not enabled,
 966          * it discrards it!.  These guys......
 967          */
 968         writel(VRCR_IPEN | VRCR_VTDEN, ns->base + VRCR);
 969
 970         /* Enable per-packet TCP/UDP/IP checksumming */
 971         writel(VTCR_PPCHK, ns->base + VTCR);
 972
 973         /* Ramit : Enable async and sync pause frames */
 974 //      writel(0, ns->base + PCR);
 975         writel((PCR_PS_MCAST | PCR_PS_DA | PCR_PSEN | PCR_FFLO_4K |
 976                 PCR_FFHI_8K | PCR_STLO_4 | PCR_STHI_8 | PCR_PAUSE_CNT),
 977                ns->base + PCR);
 978
 979         /* Disable Wake On Lan */
 980         writel(0, ns->base + WCSR);
 981
 982         ns83820_getmac(nic, nic->node_addr);
 983
 984         if (using_dac) {
 985                 dprintf(("%s: using 64 bit addressing.\n", pci->driver_name));
 986         }
 987
 988         dprintf(("%s: DP83820 %d.%d: %! io=0x%hX\n",
 989                  pci->driver_name,
 990                  (unsigned) readl(ns->base + SRR) >> 8,
 991                  (unsigned) readl(ns->base + SRR) & 0xff,
 992                  nic->node_addr, pci->ioaddr));
 993
 994 #ifdef PHY_CODE_IS_FINISHED
 995         ns83820_probe_phy(dev);
 996 #endif
 997
 998         ns83820_reset(nic);
 999         /* point to NIC specific routines */
1000         nic->nic_op     = &ns83820_operations;
1001         return 1;
1002 }
1003
1004 DRIVER ( "NS83820/PCI", nic_driver, pci_driver, ns83820_driver,
1005          ns83820_probe, ns83820_disable );