?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Fixed receive instability by not enabling interrupts. duh.
[gpxe.git] / src / drivers / net / e1000 / e1000.c
blob08528512bb695c0685e2e5b03f3a97af01ac6dd9
1 /*******************************************************************************
2
3 Intel PRO/1000 Linux driver
4 Copyright(c) 1999 - 2006 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27 *******************************************************************************/
28
29 #include "e1000.h"
30
31 /**
32 * e1000_get_hw_control - get control of the h/w from f/w
33 * @adapter: address of board private structure
34 *
35 * e1000_get_hw_control sets {CTRL_EXT|FWSM}:DRV_LOAD bit.
36 * For ASF and Pass Through versions of f/w this means that
37 * the driver is loaded. For AMT version (only with 82573)
38 * of the f/w this means that the network i/f is open.
39 *
40 **/
41 static void
42 e1000_get_hw_control(struct e1000_adapter *adapter)
43 {
44 uint32_t ctrl_ext;
45 uint32_t swsm;
46
47 DBG ( "e1000_get_hw_control\n" );
48
49 /* Let firmware know the driver has taken over */
50 switch (adapter->hw.mac_type) {
51 case e1000_82573:
52 swsm = E1000_READ_REG(&adapter->hw, SWSM);
53 E1000_WRITE_REG(&adapter->hw, SWSM,
54 swsm | E1000_SWSM_DRV_LOAD);
55 break;
56 case e1000_82571:
57 case e1000_82572:
58 case e1000_80003es2lan:
59 case e1000_ich8lan:
60 ctrl_ext = E1000_READ_REG(&adapter->hw, CTRL_EXT);
61 E1000_WRITE_REG(&adapter->hw, CTRL_EXT,
62 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
63 break;
64 default:
65 break;
66 }
67 }
68
69 /**
70 * e1000_irq_enable - Enable default interrupt generation settings
71 * @adapter: board private structure
72 **/
73 static void
74 e1000_irq_enable ( struct e1000_adapter *adapter )
75 {
76 E1000_WRITE_REG ( &adapter->hw, IMS, E1000_IMS_RXDMT0 |
77 E1000_IMS_RXSEQ );
78 E1000_WRITE_FLUSH ( &adapter->hw );
79 }
80
81 /**
82 * e1000_irq_disable - Mask off interrupt generation on the NIC
83 * @adapter: board private structure
84 **/
85 static void
86 e1000_irq_disable ( struct e1000_adapter *adapter )
87 {
88 E1000_WRITE_REG ( &adapter->hw, IMC, ~0 );
89 E1000_WRITE_FLUSH ( &adapter->hw );
90 }
91
92 /**
93 * e1000_irq_force - trigger interrupt
94 * @adapter: board private structure
95 **/
96 static void
97 e1000_irq_force ( struct e1000_adapter *adapter )
98 {
99 E1000_WRITE_REG ( &adapter->hw, ICS, E1000_ICS_RXDMT0 );
100 E1000_WRITE_FLUSH ( &adapter->hw );
101 }
102
103 /**
104 * e1000_sw_init - Initialize general software structures (struct e1000_adapter)
105 * @adapter: board private structure to initialize
106 *
107 * e1000_sw_init initializes the Adapter private data structure.
108 * Fields are initialized based on PCI device information and
109 * OS network device settings (MTU size).
110 **/
111 static int
112 e1000_sw_init ( struct e1000_adapter *adapter )
113 {
114 struct e1000_hw *hw = &adapter->hw;
115 struct pci_device *pdev = adapter->pdev;
116
117 /* PCI config space info */
118
119 hw->vendor_id = pdev->vendor;
120 hw->device_id = pdev->device;
121
122 pci_read_config_word ( pdev, PCI_COMMAND, &hw->pci_cmd_word );
123
124 /* Disable Flow Control */
125 hw->fc = E1000_FC_NONE;
126
127 adapter->eeprom_wol = 0;
128 adapter->wol = adapter->eeprom_wol;
129 adapter->en_mng_pt = 0;
130 adapter->rx_int_delay = 0;
131 adapter->rx_abs_int_delay = 0;
132
133 adapter->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE;
134 adapter->rx_ps_bsize0 = E1000_RXBUFFER_128;
135 hw->max_frame_size = MAXIMUM_ETHERNET_VLAN_SIZE +
136 ENET_HEADER_SIZE + ETHERNET_FCS_SIZE;
137 hw->min_frame_size = MINIMUM_ETHERNET_FRAME_SIZE;
138
139 /* identify the MAC */
140
141 if ( e1000_set_mac_type ( hw ) ) {
142 DBG ( "Unknown MAC Type\n" );
143 return -EIO;
144 }
145
146 switch ( hw->mac_type ) {
147 default:
148 break;
149 case e1000_82541:
150 case e1000_82547:
151 case e1000_82541_rev_2:
152 case e1000_82547_rev_2:
153 hw->phy_init_script = 1;
154 break;
155 }
156
157 e1000_set_media_type ( hw );
158
159 hw->autoneg = TRUE;
160 hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT;
161 hw->wait_autoneg_complete = TRUE;
162
163 hw->tbi_compatibility_en = TRUE;
164 hw->adaptive_ifs = TRUE;
165
166 /* Copper options */
167
168 if ( hw->media_type == e1000_media_type_copper ) {
169 hw->mdix = AUTO_ALL_MODES;
170 hw->disable_polarity_correction = FALSE;
171 hw->master_slave = E1000_MASTER_SLAVE;
172 }
173
174 e1000_irq_disable ( adapter );
175
176 return 0;
177 }
178
179 /**
180 * e1000_setup_tx_resources - allocate Tx resources (Descriptors)
181 * @adapter: board private structure
182 * @txdr: tx descriptor ring (for a specific queue) to setup
183 *
184 * Return 0 on success, negative on failure
185 **/
186 static int
187 e1000_setup_tx_resources ( struct e1000_adapter *adapter )
188 {
189 DBG ( "e1000_setup_tx_resources\n" );
190
191 /* Allocate transmit descriptor ring memory.
192 It must not cross a 64K boundary because of hardware errata #23
193 so we use malloc_dma() requesting a 128 byte block that is
194 128 byte aligned. This should guarantee that the memory
195 allocated will not cross a 64K boundary, because 128 is an
196 even multiple of 65536 ( 65536 / 128 == 512 ), so all possible
197 allocations of 128 bytes on a 128 byte boundary will not
198 cross 64K bytes.
199 */
200
201 adapter->tx_base =
202 malloc_dma ( adapter->tx_ring_size, adapter->tx_ring_size );
203
204 if ( ! adapter->tx_base ) {
205 return -ENOMEM;
206 }
207
208 memset ( adapter->tx_base, 0, adapter->tx_ring_size );
209
210 DBG ( "adapter->tx_base = %#08lx\n", virt_to_bus ( adapter->tx_base ) );
211
212 return 0;
213 }
214
215 static void
216 e1000_free_tx_resources ( struct e1000_adapter *adapter )
217 {
218 DBG ( "e1000_free_tx_resources\n" );
219
220 free_dma ( adapter->tx_base, adapter->tx_ring_size );
221 }
222
223 /**
224 * e1000_configure_tx - Configure 8254x Transmit Unit after Reset
225 * @adapter: board private structure
226 *
227 * Configure the Tx unit of the MAC after a reset.
228 **/
229 static void
230 e1000_configure_tx ( struct e1000_adapter *adapter )
231 {
232 struct e1000_hw *hw = &adapter->hw;
233 uint32_t tctl;
234
235 #if 0
236 uint32 tipg, tarc;
237 uint32_t ipgr1, ipgr2;
238 #endif
239
240 DBG ( "e1000_configure_tx\n" );
241
242 E1000_WRITE_REG ( hw, TDBAH, 0 );
243 E1000_WRITE_REG ( hw, TDBAL, virt_to_bus ( adapter->tx_base ) );
244 E1000_WRITE_REG ( hw, TDLEN, adapter->tx_ring_size );
245
246 DBG ( "TDBAL: %#08lx\n", E1000_READ_REG ( hw, TDBAL ) );
247 DBG ( "TDLEN: %ld\n", E1000_READ_REG ( hw, TDLEN ) );
248
249 /* Setup the HW Tx Head and Tail descriptor pointers */
250 E1000_WRITE_REG ( hw, TDH, 0 );
251 E1000_WRITE_REG ( hw, TDT, 0 );
252
253 adapter->tx_head = 0;
254 adapter->tx_tail = 0;
255 adapter->tx_fill_ctr = 0;
256
257 #if 0
258 /* Set the default values for the Tx Inter Packet Gap timer */
259 if (adapter->hw.mac_type <= e1000_82547_rev_2 &&
260 (hw->media_type == e1000_media_type_fiber ||
261 hw->media_type == e1000_media_type_internal_serdes))
262 tipg = DEFAULT_82543_TIPG_IPGT_FIBER;
263 else
264 tipg = DEFAULT_82543_TIPG_IPGT_COPPER;
265
266 switch (hw->mac_type) {
267 case e1000_82542_rev2_0:
268 case e1000_82542_rev2_1:
269 tipg = DEFAULT_82542_TIPG_IPGT;
270 ipgr1 = DEFAULT_82542_TIPG_IPGR1;
271 ipgr2 = DEFAULT_82542_TIPG_IPGR2;
272 break;
273 case e1000_80003es2lan:
274 ipgr1 = DEFAULT_82543_TIPG_IPGR1;
275 ipgr2 = DEFAULT_80003ES2LAN_TIPG_IPGR2;
276 break;
277 default:
278 ipgr1 = DEFAULT_82543_TIPG_IPGR1;
279 ipgr2 = DEFAULT_82543_TIPG_IPGR2;
280 break;
281 }
282 tipg |= ipgr1 << E1000_TIPG_IPGR1_SHIFT;
283 tipg |= ipgr2 << E1000_TIPG_IPGR2_SHIFT;
284 E1000_WRITE_REG ( hw, TIPG, tipg );
285
286 /* Set the Tx Interrupt Delay register */
287
288 E1000_WRITE_REG (hw, TIDV, adapter->tx_int_delay);
289 if (hw->mac_type >= e1000_82540)
290 E1000_WRITE_REG(hw, TADV, adapter->tx_abs_int_delay);
291
292 /* Program the Transmit Control Register */
293
294 tctl = E1000_READ_REG ( hw, TCTL );
295 tctl &= ~E1000_TCTL_CT;
296 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
297 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
298
299 if (hw->mac_type == e1000_82571 || hw->mac_type == e1000_82572) {
300 tarc = E1000_READ_REG(hw, TARC0);
301 /* set the speed mode bit, we'll clear it if we're not at
302 * gigabit link later */
303 tarc |= (1 << 21);
304 E1000_WRITE_REG(hw, TARC0, tarc);
305 } else if (hw->mac_type == e1000_80003es2lan) {
306 tarc = E1000_READ_REG(hw, TARC0);
307 tarc |= 1;
308 E1000_WRITE_REG(hw, TARC0, tarc);
309 tarc = E1000_READ_REG(hw, TARC1);
310 tarc |= 1;
311 E1000_WRITE_REG(hw, TARC1, tarc);
312 }
313 #endif
314
315 e1000_config_collision_dist ( hw );
316
317 tctl = E1000_TCTL_PSP | E1000_TCTL_EN |
318 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT) |
319 (E1000_HDX_COLLISION_DISTANCE << E1000_COLD_SHIFT);
320
321 #if 0
322 /* Setup Transmit Descriptor Settings for eop descriptor */
323 adapter->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_IFCS;
324
325 /* only set IDE if we are delaying interrupts using the timers */
326 if (adapter->tx_int_delay)
327 adapter->txd_cmd |= E1000_TXD_CMD_IDE;
328
329 if (hw->mac_type < e1000_82543)
330 adapter->txd_cmd |= E1000_TXD_CMD_RPS;
331 else
332 adapter->txd_cmd |= E1000_TXD_CMD_RS;
333
334 /* Cache if we're 82544 running in PCI-X because we'll
335 * need this to apply a workaround later in the send path. */
336 if (hw->mac_type == e1000_82544 &&
337 hw->bus_type == e1000_bus_type_pcix)
338 adapter->pcix_82544 = 1;
339 #endif
340
341 E1000_WRITE_REG ( hw, TCTL, tctl );
342 }
343
344 /**
345 * e1000_setup_rx_resources - allocate Rx resources (Descriptors)
346 * @adapter: board private structure
347 * @rxdr: rx descriptor ring (for a specific queue) to setup
348 *
349 * Returns 0 on success, negative on failure
350 **/
351 static int
352 e1000_setup_rx_resources ( struct e1000_adapter *adapter )
353 {
354 int i, j;
355 struct e1000_rx_desc *rx_curr_desc;
356
357 DBG ( "e1000_setup_rx_resources\n" );
358
359 /* Allocate receive descriptor ring memory.
360 It must not cross a 64K boundary because of hardware errata
361 */
362
363 adapter->rx_base =
364 malloc_dma ( adapter->rx_ring_size, adapter->rx_ring_size );
365
366 if ( ! adapter->rx_base ) {
367 return -ENOMEM;
368 }
369 memset ( adapter->rx_base, 0, adapter->rx_ring_size );
370
371 for ( i = 0; i < NUM_RX_DESC; i++ ) {
372
373 adapter->rx_iobuf[i] = alloc_iob ( MAXIMUM_ETHERNET_VLAN_SIZE );
374
375 /* If unable to allocate all iobufs, free any that
376 * were successfully allocated, and return an error
377 */
378 if ( ! adapter->rx_iobuf[i] ) {
379 for ( j = 0; j < i; j++ ) {
380 free_iob ( adapter->rx_iobuf[j] );
381 }
382 return -ENOMEM;
383 }
384
385 rx_curr_desc = ( void * ) ( adapter->rx_base ) +
386 ( i * sizeof ( *adapter->rx_base ) );
387
388 rx_curr_desc->buffer_addr = virt_to_bus ( adapter->rx_iobuf[i]->data );
389
390 DBG ( "i = %d rx_curr_desc->buffer_addr = %#16llx\n",
391 i, rx_curr_desc->buffer_addr );
392
393 }
394 return 0;
395 }
396
397 static void
398 e1000_free_rx_resources ( struct e1000_adapter *adapter )
399 {
400 int i;
401
402 DBG ( "e1000_free_rx_resources\n" );
403
404 free_dma ( adapter->rx_base, adapter->rx_ring_size );
405
406 for ( i = 0; i < NUM_RX_DESC; i++ ) {
407 free_iob ( adapter->rx_iobuf[i] );
408 }
409 }
410
411 /**
412 * e1000_configure_rx - Configure 8254x Receive Unit after Reset
413 * @adapter: board private structure
414 *
415 * Configure the Rx unit of the MAC after a reset.
416 **/
417 static void
418 e1000_configure_rx ( struct e1000_adapter *adapter )
419 {
420 struct e1000_hw *hw = &adapter->hw;
421 uint32_t rctl;
422
423 DBG ( "e1000_configure_rx\n" );
424
425 /* disable receives while setting up the descriptors */
426 rctl = E1000_READ_REG ( hw, RCTL );
427 E1000_WRITE_REG ( hw, RCTL, rctl & ~E1000_RCTL_EN );
428
429 adapter->rx_tail = 0;
430
431 /* Setup the HW Rx Head and Tail Descriptor Pointers and
432 * the Base and Length of the Rx Descriptor Ring */
433
434 E1000_WRITE_REG ( hw, RDBAL, virt_to_bus ( adapter->rx_base ) );
435 E1000_WRITE_REG ( hw, RDBAH, 0 );
436 E1000_WRITE_REG ( hw, RDLEN, adapter->rx_ring_size );
437
438 E1000_WRITE_REG ( hw, RDH, 0 );
439 E1000_WRITE_REG ( hw, RDT, NUM_TX_DESC );
440
441 /* Enable Receives */
442 rctl = ( E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_SZ_2048 |
443 E1000_RCTL_MPE
444 );
445
446 E1000_WRITE_REG ( hw, RCTL, rctl );
447 E1000_WRITE_FLUSH ( hw );
448
449 DBG ( "RDBAL: %#08lx\n", E1000_READ_REG ( hw, RDBAL ) );
450 DBG ( "RDLEN: %ld\n", E1000_READ_REG ( hw, RDLEN ) );
451 DBG ( "RCTL: %#08lx\n", E1000_READ_REG ( hw, RCTL ) );
452 }
453
454 /**
455 * e1000_reset - Put e1000 NIC in known initial state
456 *
457 * @v adapter e1000 private structure
458 **/
459 static void
460 e1000_reset ( struct e1000_adapter *adapter )
461 {
462 uint32_t pba = 0;
463 uint16_t fc_high_water_mark = E1000_FC_HIGH_DIFF;
464
465 DBG ( "e1000_reset\n" );
466
467 switch (adapter->hw.mac_type) {
468 case e1000_82542_rev2_0:
469 case e1000_82542_rev2_1:
470 case e1000_82543:
471 case e1000_82544:
472 case e1000_82540:
473 case e1000_82541:
474 case e1000_82541_rev_2:
475 pba = E1000_PBA_48K;
476 break;
477 case e1000_82545:
478 case e1000_82545_rev_3:
479 case e1000_82546:
480 case e1000_82546_rev_3:
481 pba = E1000_PBA_48K;
482 break;
483 case e1000_82547:
484 case e1000_82547_rev_2:
485 pba = E1000_PBA_30K;
486 break;
487 case e1000_82571:
488 case e1000_82572:
489 case e1000_80003es2lan:
490 pba = E1000_PBA_38K;
491 break;
492 case e1000_82573:
493 pba = E1000_PBA_20K;
494 break;
495 case e1000_ich8lan:
496 pba = E1000_PBA_8K;
497 case e1000_undefined:
498 case e1000_num_macs:
499 break;
500 }
501
502 E1000_WRITE_REG ( &adapter->hw, PBA, pba );
503
504 /* flow control settings */
505 /* Set the FC high water mark to 90% of the FIFO size.
506 * Required to clear last 3 LSB */
507 fc_high_water_mark = ((pba * 9216)/10) & 0xFFF8;
508 /* We can't use 90% on small FIFOs because the remainder
509 * would be less than 1 full frame. In this case, we size
510 * it to allow at least a full frame above the high water
511 * mark. */
512 if (pba < E1000_PBA_16K)
513 fc_high_water_mark = (pba * 1024) - 1600;
514
515 adapter->hw.fc_high_water = fc_high_water_mark;
516 adapter->hw.fc_low_water = fc_high_water_mark - 8;
517 if (adapter->hw.mac_type == e1000_80003es2lan)
518 adapter->hw.fc_pause_time = 0xFFFF;
519 else
520 adapter->hw.fc_pause_time = E1000_FC_PAUSE_TIME;
521 adapter->hw.fc_send_xon = 1;
522 adapter->hw.fc = adapter->hw.original_fc;
523 /* Allow time for pending master requests to run */
524
525 e1000_reset_hw ( &adapter->hw );
526
527 if ( adapter->hw.mac_type >= e1000_82544 )
528 E1000_WRITE_REG ( &adapter->hw, WUC, 0 );
529
530 if ( e1000_init_hw ( &adapter->hw ) )
531 DBG ( "Hardware Error\n" );
532
533 /* if (adapter->hwflags & HWFLAGS_PHY_PWR_BIT) { */
534 if (adapter->hw.mac_type >= e1000_82544 &&
535 adapter->hw.mac_type <= e1000_82547_rev_2 &&
536 adapter->hw.autoneg == 1 &&
537 adapter->hw.autoneg_advertised == ADVERTISE_1000_FULL) {
538 uint32_t ctrl = E1000_READ_REG(&adapter->hw, CTRL);
539 /* clear phy power management bit if we are in gig only mode,
540 * which if enabled will attempt negotiation to 100Mb, which
541 * can cause a loss of link at power off or driver unload */
542 ctrl &= ~E1000_CTRL_SWDPIN3;
543 E1000_WRITE_REG(&adapter->hw, CTRL, ctrl);
544 }
545
546 e1000_phy_get_info ( &adapter->hw, &adapter->phy_info );
547
548 if (!adapter->smart_power_down &&
549 (adapter->hw.mac_type == e1000_82571 ||
550 adapter->hw.mac_type == e1000_82572)) {
551 uint16_t phy_data = 0;
552 /* speed up time to link by disabling smart power down, ignore
553 * the return value of this function because there is nothing
554 * different we would do if it failed */
555 e1000_read_phy_reg(&adapter->hw, IGP02E1000_PHY_POWER_MGMT,
556 &phy_data);
557 phy_data &= ~IGP02E1000_PM_SPD;
558 e1000_write_phy_reg(&adapter->hw, IGP02E1000_PHY_POWER_MGMT,
559 phy_data);
560 }
561 }
562
563 /** Functions that implement the gPXE driver API **/
564
565 /**
566 * e1000_close - Disables a network interface
567 *
568 * @v netdev network interface device structure
569 *
570 **/
571 static void
572 e1000_close ( struct net_device *netdev )
573 {
574 struct e1000_adapter *adapter = netdev_priv ( netdev );
575 struct e1000_hw *hw = &adapter->hw;
576 uint32_t rctl;
577 uint32_t icr;
578
579 DBG ( "e1000_close\n" );
580
581 /* Acknowledge interrupts */
582 icr = E1000_READ_REG ( hw, ICR );
583
584 e1000_irq_disable ( adapter );
585
586 /* disable receives */
587 rctl = E1000_READ_REG ( hw, RCTL );
588 E1000_WRITE_REG ( hw, RCTL, rctl & ~E1000_RCTL_EN );
589 E1000_WRITE_FLUSH ( hw );
590
591 e1000_reset_hw ( hw );
592
593 e1000_free_tx_resources ( adapter );
594 e1000_free_rx_resources ( adapter );
595 }
596
597 /**
598 * e1000_transmit - Transmit a packet
599 *
600 * @v netdev Network device
601 * @v iobuf I/O buffer
602 *
603 * @ret rc Return status code
604 */
605 static int
606 e1000_transmit ( struct net_device *netdev, struct io_buffer *iobuf )
607 {
608 struct e1000_adapter *adapter = netdev_priv( netdev );
609 struct e1000_hw *hw = &adapter->hw;
610 uint32_t tx_curr = adapter->tx_tail;
611 struct e1000_tx_desc *tx_curr_desc;
612
613 DBG ("e1000_transmit\n");
614
615 if ( adapter->tx_fill_ctr == NUM_TX_DESC ) {
616 DBG ("TX overflow\n");
617 return -ENOBUFS;
618 }
619
620 /* Save pointer to iobuf we have been given to transmit,
621 netdev_tx_complete() will need it later
622 */
623 adapter->tx_iobuf[tx_curr] = iobuf;
624
625 tx_curr_desc = ( void * ) ( adapter->tx_base ) +
626 ( tx_curr * sizeof ( *adapter->tx_base ) );
627
628 DBG ( "tx_curr_desc = %#08lx\n", virt_to_bus ( tx_curr_desc ) );
629 DBG ( "tx_curr_desc + 16 = %#08lx\n", virt_to_bus ( tx_curr_desc ) + 16 );
630 DBG ( "iobuf->data = %#08lx\n", virt_to_bus ( iobuf->data ) );
631
632 /* Add the packet to TX ring
633 */
634 tx_curr_desc->buffer_addr =
635 virt_to_bus ( iobuf->data );
636 tx_curr_desc->lower.data =
637 E1000_TXD_CMD_RPS | E1000_TXD_CMD_EOP |
638 E1000_TXD_CMD_IFCS | iob_len ( iobuf );
639 tx_curr_desc->upper.data = 0;
640
641 DBG ( "TX fill: %ld tx_curr: %ld addr: %#08lx len: %d\n", adapter->tx_fill_ctr,
642 tx_curr, virt_to_bus ( iobuf->data ), iob_len ( iobuf ) );
643
644 /* Point to next free descriptor */
645 adapter->tx_tail = ( adapter->tx_tail + 1 ) % NUM_TX_DESC;
646 adapter->tx_fill_ctr++;
647
648 /* Write new tail to NIC, making packet available for transmit
649 */
650 E1000_WRITE_REG ( hw, TDT, adapter->tx_tail );
651
652 #if 0
653 while ( ! ( tx_curr_desc->upper.data & E1000_TXD_STAT_DD ) ) {
654 udelay ( 10 ); /* give the nic a chance to write to the register */
655 }
656
657 DBG ( "Leaving XMIT\n" );
658 #endif
659
660 return 0;
661 }
662
663 /**
664 * e1000_poll - Poll for received packets
665 *
666 * @v netdev Network device
667 */
668 static void
669 e1000_poll ( struct net_device *netdev )
670 {
671 struct e1000_adapter *adapter = netdev_priv( netdev );
672 struct e1000_hw *hw = &adapter->hw;
673
674 uint32_t icr;
675 uint32_t tx_status;
676 uint32_t rx_status;
677 uint32_t rx_len;
678 uint32_t rx_err;
679 struct io_buffer *rx_iob;
680 struct e1000_tx_desc *tx_curr_desc;
681 struct e1000_rx_desc *rx_curr_desc;
682 uint32_t i;
683 uint64_t tmp_buffer_addr;
684
685 #if 0
686 DBG ( "e1000_poll\n" );
687 #endif
688
689 /* Acknowledge interrupts */
690 icr = E1000_READ_REG ( hw, ICR );
691 if ( ! icr )
692 return;
693
694 DBG ( "e1000_poll: intr_status = %#08lx\n", icr );
695
696 /* Check status of transmitted packets
697 */
698 while ( ( i = adapter->tx_head ) != adapter->tx_tail ) {
699
700 tx_curr_desc = ( void * ) ( adapter->tx_base ) +
701 ( i * sizeof ( *adapter->tx_base ) );
702
703 tx_status = tx_curr_desc->upper.data;
704
705 #if 0
706 DBG ( "tx_curr_desc = %#08lx status = %#08lx\n",
707 virt_to_bus ( tx_curr_desc ), tx_status );
708 #endif
709
710 /* if the packet at tx_head is not owned by hardware it is for us */
711 if ( ! ( tx_status & E1000_TXD_STAT_DD ) )
712 break;
713
714 DBG ( "Sent packet. tx_head: %ld tx_tail: %ld tx_status: %#08lx\n",
715 adapter->tx_head, adapter->tx_tail, tx_status );
716
717 if ( tx_status & ( E1000_TXD_STAT_EC | E1000_TXD_STAT_LC |
718 E1000_TXD_STAT_TU ) ) {
719 netdev_tx_complete_err ( netdev, adapter->tx_iobuf[i], -EINVAL );
720 DBG ( "Error transmitting packet, tx_status: %#08lx\n",
721 tx_status );
722 } else {
723 netdev_tx_complete ( netdev, adapter->tx_iobuf[i] );
724 DBG ( "Success transmitting packet, tx_status: %#08lx\n",
725 tx_status );
726 }
727
728 /* Decrement count of used descriptors, clear this descriptor
729 */
730 adapter->tx_fill_ctr--;
731 memset ( tx_curr_desc, 0, sizeof ( *tx_curr_desc ) );
732
733 adapter->tx_head = ( adapter->tx_head + 1 ) % NUM_TX_DESC;
734 }
735
736 /* Process received packets
737 */
738 while ( 1 ) {
739
740 i = adapter->rx_tail;;
741
742 rx_curr_desc = ( void * ) ( adapter->rx_base ) +
743 ( i * sizeof ( *adapter->rx_base ) );
744 rx_status = rx_curr_desc->status;
745
746 // DBG ( "Before DD Check RX_status: %#08lx\n", rx_status );
747
748 if ( ! ( rx_status & E1000_RXD_STAT_DD ) )
749 break;
750
751 DBG ( "RCTL = %#08lx\n", E1000_READ_REG ( &adapter->hw, RCTL ) );
752
753 rx_len = rx_curr_desc->length;
754
755 DBG ( "Received packet, rx_tail: %ld rx_status: %#08lx rx_len: %ld\n",
756 i, rx_status, rx_len );
757
758 rx_err = rx_curr_desc->errors;
759
760 if ( rx_err & E1000_RXD_ERR_FRAME_ERR_MASK ) {
761
762 netdev_rx_err ( netdev, NULL, -EINVAL );
763 DBG ( "e1000_poll: Corrupted packet received!"
764 " rx_err: %#08lx\n", rx_err );
765 } else {
766
767 /* If unable allocate space for this packet,
768 * try again next poll
769 */
770 rx_iob = alloc_iob ( rx_len );
771 if ( ! rx_iob )
772 break;
773
774 memcpy ( iob_put ( rx_iob, rx_len ),
775 adapter->rx_iobuf[i]->data, rx_len );
776
777 /* Add this packet to the receive queue.
778 */
779 netdev_rx ( netdev, rx_iob );
780 }
781
782 tmp_buffer_addr = rx_curr_desc->buffer_addr;
783 memset ( rx_curr_desc, 0, sizeof ( *rx_curr_desc ) );
784 rx_curr_desc->buffer_addr = tmp_buffer_addr;
785
786 E1000_WRITE_REG ( hw, RDT, adapter->rx_tail );
787
788 adapter->rx_tail = ( adapter->rx_tail + 1 ) % NUM_RX_DESC;
789 }
790 }
791
792 /**
793 * e1000_irq - enable or Disable interrupts
794 *
795 * @v adapter e1000 adapter
796 * @v action requested interrupt action
797 **/
798 static void
799 e1000_irq ( struct net_device *netdev, int enable )
800 {
801 struct e1000_adapter *adapter = netdev_priv(netdev);
802
803 DBG ( "e1000_irq\n" );
804
805 switch ( enable ) {
806 case 0 :
807 e1000_irq_enable ( adapter );
808 break;
809 case 1 :
810 e1000_irq_disable ( adapter );
811 break;
812 case 2 :
813 e1000_irq_force ( adapter );
814 break;
815 }
816 }
817
818 static struct net_device_operations e1000_operations;
819
820 /**
821 * e1000_probe - Initial configuration of e1000 NIC
822 *
823 * @v pci PCI device
824 * @v id PCI IDs
825 *
826 * @ret rc Return status code
827 **/
828 static int
829 e1000_probe ( struct pci_device *pdev,
830 const struct pci_device_id *id __unused )
831 {
832 int i, err;
833 struct net_device *netdev;
834 struct e1000_adapter *adapter;
835 unsigned long mmio_start, mmio_len;
836 unsigned long flash_start, flash_len;
837
838 DBG ( "e1000_probe\n" );
839
840 err = -ENOMEM;
841
842 /* Allocate net device ( also allocates memory for netdev->priv
843 and makes netdev-priv point to it ) */
844 netdev = alloc_etherdev ( sizeof ( struct e1000_adapter ) );
845 if ( ! netdev )
846 goto err_alloc_etherdev;
847
848 /* Associate e1000-specific network operations operations with
849 * generic network device layer */
850 netdev_init ( netdev, &e1000_operations );
851
852 /* Associate this network device with given PCI device */
853 pci_set_drvdata ( pdev, netdev );
854 netdev->dev = &pdev->dev;
855
856 /* Initialize driver private storage */
857 adapter = netdev_priv ( netdev );
858 memset ( adapter, 0, ( sizeof ( *adapter ) ) );
859
860 adapter->hw.io_base = pdev->ioaddr;
861 adapter->ioaddr = pdev->ioaddr;
862 adapter->irqno = pdev->irq;
863 adapter->netdev = netdev;
864 adapter->pdev = pdev;
865 adapter->hw.back = adapter;
866
867 adapter->tx_ring_size = sizeof ( *adapter->tx_base ) * NUM_TX_DESC;
868 adapter->rx_ring_size = sizeof ( *adapter->rx_base ) * NUM_RX_DESC;
869
870 mmio_start = pci_bar_start ( pdev, PCI_BASE_ADDRESS_0 );
871 mmio_len = pci_bar_size ( pdev, PCI_BASE_ADDRESS_0 );
872
873 DBG ( "mmio_start: %#08lx\n", mmio_start );
874 DBG ( "mmio_len: %#08lx\n", mmio_len );
875
876 /* Fix up PCI device */
877 adjust_pci_device ( pdev );
878
879 err = -EIO;
880
881 adapter->hw.hw_addr = ioremap ( mmio_start, mmio_len );
882 DBG ( "adapter->hw.hw_addr: %p\n", adapter->hw.hw_addr );
883
884 if ( ! adapter->hw.hw_addr )
885 goto err_ioremap;
886
887 /* setup the private structure */
888 if ( ( err = e1000_sw_init ( adapter ) ) )
889 goto err_sw_init;
890
891 DBG ( "adapter->hw.mac_type: %#08x\n", adapter->hw.mac_type );
892
893 /* Flash BAR mapping must happen after e1000_sw_init
894 * because it depends on mac_type
895 */
896 if ( ( adapter->hw.mac_type == e1000_ich8lan ) && ( pdev->ioaddr ) ) {
897 flash_start = pci_bar_start ( pdev, 1 );
898 flash_len = pci_bar_size ( pdev, 1 );
899 adapter->hw.flash_address = ioremap ( flash_start, flash_len );
900 if ( ! adapter->hw.flash_address )
901 goto err_flashmap;
902 }
903
904 /* initialize eeprom parameters */
905 if ( e1000_init_eeprom_params ( &adapter->hw ) ) {
906 DBG ( "EEPROM initialization failed\n" );
907 goto err_eeprom;
908 }
909
910 /* before reading the EEPROM, reset the controller to
911 * put the device in a known good starting state
912 */
913 err = e1000_reset_hw ( &adapter->hw );
914 if ( err < 0 ) {
915 DBG ( "Hardware Initialization Failed\n" );
916 goto err_reset;
917 }
918
919 /* make sure the EEPROM is good */
920 if ( e1000_validate_eeprom_checksum( &adapter->hw ) < 0 ) {
921 DBG ( "The EEPROM Checksum Is Not Valid\n" );
922 goto err_eeprom;
923 }
924
925 /* copy the MAC address out of the EEPROM */
926 if ( e1000_read_mac_addr ( &adapter->hw ) )
927 DBG ( "EEPROM Read Error\n" );
928
929 memcpy ( netdev->ll_addr, adapter->hw.mac_addr, ETH_ALEN );
930
931 /* print bus type/speed/width info */
932 {
933 struct e1000_hw *hw = &adapter->hw;
934 DBG ( "(PCI%s:%s:%s) ",
935 ((hw->bus_type == e1000_bus_type_pcix) ? "-X" :
936 (hw->bus_type == e1000_bus_type_pci_express ? " Express":"")),
937 ((hw->bus_speed == e1000_bus_speed_2500) ? "2.5Gb/s" :
938 (hw->bus_speed == e1000_bus_speed_133) ? "133MHz" :
939 (hw->bus_speed == e1000_bus_speed_120) ? "120MHz" :
940 (hw->bus_speed == e1000_bus_speed_100) ? "100MHz" :
941 (hw->bus_speed == e1000_bus_speed_66) ? "66MHz" : "33MHz"),
942 ((hw->bus_width == e1000_bus_width_64) ? "64-bit" :
943 (hw->bus_width == e1000_bus_width_pciex_4) ? "Width x4" :
944 (hw->bus_width == e1000_bus_width_pciex_1) ? "Width x1" :
945 "32-bit"));
946 }
947 for (i = 0; i < 6; i++)
948 DBG ("%02x%s", netdev->ll_addr[i], i == 5 ? "\n" : ":");
949
950 /* reset the hardware with the new settings */
951 e1000_reset ( adapter );
952
953 e1000_get_hw_control ( adapter );
954
955 if ( ( err = register_netdev ( netdev ) ) != 0)
956 goto err_register;
957
958 DBG ( "e1000_probe succeeded!\n" );
959
960 /* No errors, return success */
961 return 0;
962
963 /* Error return paths */
964 err_reset:
965 err_register:
966 err_eeprom:
967 if ( ! e1000_check_phy_reset_block ( &adapter->hw ) )
968 e1000_phy_hw_reset ( &adapter->hw );
969 if ( adapter->hw.flash_address )
970 iounmap ( adapter->hw.flash_address );
971 err_flashmap:
972 err_sw_init:
973 iounmap ( adapter->hw.hw_addr );
974 err_ioremap:
975 netdev_put ( netdev );
976 err_alloc_etherdev:
977 return err;
978 }
979
980 /**
981 * e1000_remove - Device Removal Routine
982 *
983 * @v pdev PCI device information struct
984 *
985 **/
986 static void
987 e1000_remove ( struct pci_device *pdev )
988 {
989 struct net_device *netdev = pci_get_drvdata ( pdev );
990 struct e1000_adapter *adapter = netdev_priv ( netdev );
991
992 DBG ( "e1000_remove\n" );
993
994 if ( adapter->hw.flash_address )
995 iounmap ( adapter->hw.flash_address );
996 if ( adapter->hw.hw_addr )
997 iounmap ( adapter->hw.hw_addr );
998
999 unregister_netdev ( netdev );
1000 e1000_reset_hw ( &adapter->hw );
1001 netdev_nullify ( netdev );
1002 netdev_put ( netdev );
1003 }
1004
1005 /**
1006 * e1000_open - Called when a network interface is made active
1007 *
1008 * @v netdev network interface device structure
1009 * @ret rc Return status code, 0 on success, negative value on failure
1010 *
1011 **/
1012 static int
1013 e1000_open ( struct net_device *netdev )
1014 {
1015 struct e1000_adapter *adapter = netdev_priv(netdev);
1016 int err;
1017
1018 DBG ( "e1000_open\n" );
1019
1020 /* allocate transmit descriptors */
1021 err = e1000_setup_tx_resources ( adapter );
1022 if (err) {
1023 DBG ( "Error setting up TX resources!\n" );
1024 goto err_setup_tx;
1025 }
1026
1027 /* allocate receive descriptors */
1028 err = e1000_setup_rx_resources ( adapter );
1029 if (err) {
1030 DBG ( "Error setting up RX resources!\n" );
1031 goto err_setup_rx;
1032 }
1033
1034 e1000_configure_tx ( adapter );
1035
1036 e1000_configure_rx ( adapter );
1037
1038 DBG ( "RXDCTL: %#08lx\n", E1000_READ_REG ( &adapter->hw, RXDCTL ) );
1039
1040 return 0;
1041
1042 err_setup_rx:
1043 e1000_free_tx_resources ( adapter );
1044 err_setup_tx:
1045 e1000_reset ( adapter );
1046
1047 return err;
1048 }
1049
1050 /** e1000 net device operations */
1051 static struct net_device_operations e1000_operations = {
1052 .open = e1000_open,
1053 .close = e1000_close,
1054 .transmit = e1000_transmit,
1055 .poll = e1000_poll,
1056 .irq = e1000_irq,
1057 };
1058
1059 int32_t
1060 e1000_read_pcie_cap_reg(struct e1000_hw *hw, uint32_t reg, uint16_t *value)
1061 {
1062 struct e1000_adapter *adapter = hw->back;
1063 uint16_t cap_offset;
1064
1065 #define PCI_CAP_ID_EXP 0x10 /* PCI Express */
1066 cap_offset = pci_find_capability(adapter->pdev, PCI_CAP_ID_EXP);
1067 if (!cap_offset)
1068 return -E1000_ERR_CONFIG;
1069
1070 pci_read_config_word(adapter->pdev, cap_offset + reg, value);
1071
1072 return 0;
1073 }
1074
1075 void
1076 e1000_pci_clear_mwi ( struct e1000_hw *hw )
1077 {
1078 struct e1000_adapter *adapter = hw->back;
1079
1080 pci_write_config_word ( adapter->pdev, PCI_COMMAND,
1081 hw->pci_cmd_word & ~PCI_COMMAND_INVALIDATE );
1082 }
1083
1084 void
1085 e1000_pci_set_mwi ( struct e1000_hw *hw )
1086 {
1087 struct e1000_adapter *adapter = hw->back;
1088
1089 pci_write_config_word ( adapter->pdev, PCI_COMMAND, hw->pci_cmd_word );
1090 }
1091
1092 void
1093 e1000_read_pci_cfg ( struct e1000_hw *hw, uint32_t reg, uint16_t *value )
1094 {
1095 struct e1000_adapter *adapter = hw->back;
1096
1097 pci_read_config_word ( adapter->pdev, reg, value );
1098 }
1099
1100 void
1101 e1000_write_pci_cfg ( struct e1000_hw *hw, uint32_t reg, uint16_t *value )
1102 {
1103 struct e1000_adapter *adapter = hw->back;
1104
1105 pci_write_config_word ( adapter->pdev, reg, *value );
1106 }
1107
1108 void
1109 e1000_io_write ( struct e1000_hw *hw __unused, unsigned long port, uint32_t value )
1110 {
1111 outl ( value, port );
1112 }
1113
1114 static struct pci_device_id e1000_nics[] = {
1115 PCI_ROM(0x8086, 0x1000, "e1000-0x1000", "E1000-0x1000"),
1116 PCI_ROM(0x8086, 0x1001, "e1000-0x1001", "E1000-0x1001"),
1117 PCI_ROM(0x8086, 0x1004, "e1000-0x1004", "E1000-0x1004"),
1118 PCI_ROM(0x8086, 0x1008, "e1000-0x1008", "E1000-0x1008"),
1119 PCI_ROM(0x8086, 0x1009, "e1000-0x1009", "E1000-0x1009"),
1120 PCI_ROM(0x8086, 0x100C, "e1000-0x100C", "E1000-0x100C"),
1121 PCI_ROM(0x8086, 0x100D, "e1000-0x100D", "E1000-0x100D"),
1122 PCI_ROM(0x8086, 0x100E, "e1000-0x100E", "E1000-0x100E"),
1123 PCI_ROM(0x8086, 0x100F, "e1000-0x100F", "E1000-0x100F"),
1124 PCI_ROM(0x8086, 0x1010, "e1000-0x1010", "E1000-0x1010"),
1125 PCI_ROM(0x8086, 0x1011, "e1000-0x1011", "E1000-0x1011"),
1126 PCI_ROM(0x8086, 0x1012, "e1000-0x1012", "E1000-0x1012"),
1127 PCI_ROM(0x8086, 0x1013, "e1000-0x1013", "E1000-0x1013"),
1128 PCI_ROM(0x8086, 0x1014, "e1000-0x1014", "E1000-0x1014"),
1129 PCI_ROM(0x8086, 0x1015, "e1000-0x1015", "E1000-0x1015"),
1130 PCI_ROM(0x8086, 0x1016, "e1000-0x1016", "E1000-0x1016"),
1131 PCI_ROM(0x8086, 0x1017, "e1000-0x1017", "E1000-0x1017"),
1132 PCI_ROM(0x8086, 0x1018, "e1000-0x1018", "E1000-0x1018"),
1133 PCI_ROM(0x8086, 0x1019, "e1000-0x1019", "E1000-0x1019"),
1134 PCI_ROM(0x8086, 0x101A, "e1000-0x101A", "E1000-0x101A"),
1135 PCI_ROM(0x8086, 0x101D, "e1000-0x101D", "E1000-0x101D"),
1136 PCI_ROM(0x8086, 0x101E, "e1000-0x101E", "E1000-0x101E"),
1137 PCI_ROM(0x8086, 0x1026, "e1000-0x1026", "E1000-0x1026"),
1138 PCI_ROM(0x8086, 0x1027, "e1000-0x1027", "E1000-0x1027"),
1139 PCI_ROM(0x8086, 0x1028, "e1000-0x1028", "E1000-0x1028"),
1140 PCI_ROM(0x8086, 0x1049, "e1000-0x1049", "E1000-0x1049"),
1141 PCI_ROM(0x8086, 0x104A, "e1000-0x104A", "E1000-0x104A"),
1142 PCI_ROM(0x8086, 0x104B, "e1000-0x104B", "E1000-0x104B"),
1143 PCI_ROM(0x8086, 0x104C, "e1000-0x104C", "E1000-0x104C"),
1144 PCI_ROM(0x8086, 0x104D, "e1000-0x104D", "E1000-0x104D"),
1145 PCI_ROM(0x8086, 0x105E, "e1000-0x105E", "E1000-0x105E"),
1146 PCI_ROM(0x8086, 0x105F, "e1000-0x105F", "E1000-0x105F"),
1147 PCI_ROM(0x8086, 0x1060, "e1000-0x1060", "E1000-0x1060"),
1148 PCI_ROM(0x8086, 0x1075, "e1000-0x1075", "E1000-0x1075"),
1149 PCI_ROM(0x8086, 0x1076, "e1000-0x1076", "E1000-0x1076"),
1150 PCI_ROM(0x8086, 0x1077, "e1000-0x1077", "E1000-0x1077"),
1151 PCI_ROM(0x8086, 0x1078, "e1000-0x1078", "E1000-0x1078"),
1152 PCI_ROM(0x8086, 0x1079, "e1000-0x1079", "E1000-0x1079"),
1153 PCI_ROM(0x8086, 0x107A, "e1000-0x107A", "E1000-0x107A"),
1154 PCI_ROM(0x8086, 0x107B, "e1000-0x107B", "E1000-0x107B"),
1155 PCI_ROM(0x8086, 0x107C, "e1000-0x107C", "E1000-0x107C"),
1156 PCI_ROM(0x8086, 0x107D, "e1000-0x107D", "E1000-0x107D"),
1157 PCI_ROM(0x8086, 0x107E, "e1000-0x107E", "E1000-0x107E"),
1158 PCI_ROM(0x8086, 0x107F, "e1000-0x107F", "E1000-0x107F"),
1159 PCI_ROM(0x8086, 0x108A, "e1000-0x108A", "E1000-0x108A"),
1160 PCI_ROM(0x8086, 0x108B, "e1000-0x108B", "E1000-0x108B"),
1161 PCI_ROM(0x8086, 0x108C, "e1000-0x108C", "E1000-0x108C"),
1162 PCI_ROM(0x8086, 0x1096, "e1000-0x1096", "E1000-0x1096"),
1163 PCI_ROM(0x8086, 0x1098, "e1000-0x1098", "E1000-0x1098"),
1164 PCI_ROM(0x8086, 0x1099, "e1000-0x1099", "E1000-0x1099"),
1165 PCI_ROM(0x8086, 0x109A, "e1000-0x109A", "E1000-0x109A"),
1166 PCI_ROM(0x8086, 0x10A4, "e1000-0x10A4", "E1000-0x10A4"),
1167 PCI_ROM(0x8086, 0x10A5, "e1000-0x10A5", "E1000-0x10A5"),
1168 PCI_ROM(0x8086, 0x10B5, "e1000-0x10B5", "E1000-0x10B5"),
1169 PCI_ROM(0x8086, 0x10B9, "e1000-0x10B9", "E1000-0x10B9"),
1170 PCI_ROM(0x8086, 0x10BA, "e1000-0x10BA", "E1000-0x10BA"),
1171 PCI_ROM(0x8086, 0x10BB, "e1000-0x10BB", "E1000-0x10BB"),
1172 PCI_ROM(0x8086, 0x10BC, "e1000-0x10BC", "E1000-0x10BC"),
1173 PCI_ROM(0x8086, 0x10C4, "e1000-0x10C4", "E1000-0x10C4"),
1174 PCI_ROM(0x8086, 0x10C5, "e1000-0x10C5", "E1000-0x10C5"),
1175 PCI_ROM(0x8086, 0x10D9, "e1000-0x10D9", "E1000-0x10D9"),
1176 PCI_ROM(0x8086, 0x10DA, "e1000-0x10DA", "E1000-0x10DA"),
1177 };
1178
1179 struct pci_driver e1000_driver __pci_driver = {
1180 .ids = e1000_nics,
1181 .id_count = (sizeof (e1000_nics) / sizeof (e1000_nics[0])),
1182 .probe = e1000_probe,
1183 .remove = e1000_remove,
1184 };
1185
1186 /*
1187 * Local variables:
1188 * c-basic-offset: 8
1189 * c-indent-level: 8
1190 * tab-width: 8
1191 * End:
1192 */
gPXE - free pxe roms