src/drivers/net/igb/igb.h

   1 /*******************************************************************************
   2
   3   Intel(R) Gigabit Ethernet Linux driver
   4   Copyright(c) 2007-2009 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25
  26 *******************************************************************************/
  27
  28 FILE_LICENCE ( GPL2_ONLY );
  29
  30 /* Linux PRO/1000 Ethernet Driver main header file */
  31
  32 #ifndef _IGB_H_
  33 #define _IGB_H_
  34
  35 #include "igb_api.h"
  36
  37 extern int igb_probe ( struct pci_device *pdev, const struct pci_device_id *ent);
  38 extern void igb_remove ( struct pci_device *pdev );
  39
  40 struct igb_adapter;
  41
  42 /* Interrupt defines */
  43 #define IGB_START_ITR                    648 /* ~6000 ints/sec */
  44
  45 /* Interrupt modes, as used by the IntMode paramter */
  46 #define IGB_INT_MODE_LEGACY                0
  47 #define IGB_INT_MODE_MSI                   1
  48 #define IGB_INT_MODE_MSIX                  2
  49
  50 #define HW_PERF
  51 /* TX/RX descriptor defines */
  52 #define IGB_DEFAULT_TXD                  256
  53 #define IGB_MIN_TXD                       80
  54 #define IGB_MAX_TXD                     4096
  55
  56 #define IGB_DEFAULT_RXD                  256
  57 #define IGB_MIN_RXD                       80
  58 #define IGB_MAX_RXD                     4096
  59
  60 #define IGB_MIN_ITR_USECS                 10 /* 100k irq/sec */
  61 #define IGB_MAX_ITR_USECS               8191 /* 120  irq/sec */
  62
  63 #define NON_Q_VECTORS                      1
  64 #define MAX_Q_VECTORS                      8
  65
  66 /* Transmit and receive queues */
  67 #define IGB_MAX_RX_QUEUES                  (adapter->vfs_allocated_count ? 2 : \
  68                                            (hw->mac.type > e1000_82575 ? 8 : 4))
  69 #define IGB_ABS_MAX_TX_QUEUES              8
  70 #define IGB_MAX_TX_QUEUES                  IGB_MAX_RX_QUEUES
  71
  72 #define IGB_MAX_VF_MC_ENTRIES              30
  73 #define IGB_MAX_VF_FUNCTIONS               8
  74 #define IGB_MAX_VFTA_ENTRIES               128
  75 #define IGB_MAX_UTA_ENTRIES                128
  76 #define MAX_EMULATION_MAC_ADDRS            16
  77 #define OUI_LEN                            3
  78
  79 struct vf_data_storage {
  80         unsigned char vf_mac_addresses[ETH_ALEN];
  81         u16 vf_mc_hashes[IGB_MAX_VF_MC_ENTRIES];
  82         u16 num_vf_mc_hashes;
  83         u16 default_vf_vlan_id;
  84         u16 vlans_enabled;
  85         unsigned char em_mac_addresses[MAX_EMULATION_MAC_ADDRS * ETH_ALEN];
  86         u32 uta_table_copy[IGB_MAX_UTA_ENTRIES];
  87         u32 flags;
  88         unsigned long last_nack;
  89 };
  90
  91 #define IGB_VF_FLAG_CTS            0x00000001 /* VF is clear to send data */
  92 #define IGB_VF_FLAG_UNI_PROMISC    0x00000002 /* VF has unicast promisc */
  93 #define IGB_VF_FLAG_MULTI_PROMISC  0x00000004 /* VF has multicast promisc */
  94
  95 /* RX descriptor control thresholds.
  96  * PTHRESH - MAC will consider prefetch if it has fewer than this number of
  97  *           descriptors available in its onboard memory.
  98  *           Setting this to 0 disables RX descriptor prefetch.
  99  * HTHRESH - MAC will only prefetch if there are at least this many descriptors
 100  *           available in host memory.
 101  *           If PTHRESH is 0, this should also be 0.
 102  * WTHRESH - RX descriptor writeback threshold - MAC will delay writing back
 103  *           descriptors until either it has this many to write back, or the
 104  *           ITR timer expires.
 105  */
 106 #define IGB_RX_PTHRESH                    (hw->mac.type <= e1000_82576 ? 16 : 8)
 107 #define IGB_RX_HTHRESH                     8
 108 #define IGB_RX_WTHRESH                     1
 109 #define IGB_TX_PTHRESH                     8
 110 #define IGB_TX_HTHRESH                     1
 111 #define IGB_TX_WTHRESH                     ((hw->mac.type == e1000_82576 && \
 112                                              adapter->msix_entries) ? 0 : 16)
 113
 114 /* this is the size past which hardware will drop packets when setting LPE=0 */
 115 #define MAXIMUM_ETHERNET_VLAN_SIZE 1522
 116
 117 /* Supported Rx Buffer Sizes */
 118 #define IGB_RXBUFFER_128   128    /* Used for packet split */
 119 #define IGB_RXBUFFER_256   256    /* Used for packet split */
 120 #define IGB_RXBUFFER_512   512
 121 #define IGB_RXBUFFER_1024  1024
 122 #define IGB_RXBUFFER_2048  2048
 123 #define IGB_RXBUFFER_4096  4096
 124 #define IGB_RXBUFFER_8192  8192
 125 #define IGB_RXBUFFER_16384 16384
 126
 127 /* Packet Buffer allocations */
 128 #define IGB_PBA_BYTES_SHIFT 0xA
 129 #define IGB_TX_HEAD_ADDR_SHIFT 7
 130 #define IGB_PBA_TX_MASK 0xFFFF0000
 131
 132 #define IGB_FC_PAUSE_TIME 0x0680 /* 858 usec */
 133
 134 /* How many Tx Descriptors do we need to call netif_wake_queue ? */
 135 #define IGB_TX_QUEUE_WAKE       32
 136 /* How many Rx Buffers do we bundle into one write to the hardware ? */
 137 #define IGB_RX_BUFFER_WRITE     16      /* Must be power of 2 */
 138
 139 #define AUTO_ALL_MODES            0
 140 #define IGB_EEPROM_APME         0x0400
 141
 142 #ifndef IGB_MASTER_SLAVE
 143 /* Switch to override PHY master/slave setting */
 144 #define IGB_MASTER_SLAVE        e1000_ms_hw_default
 145 #endif
 146
 147 #define IGB_MNG_VLAN_NONE -1
 148
 149 /* wrapper around a pointer to a socket buffer,
 150  * so a DMA handle can be stored along with the buffer */
 151 struct igb_buffer {
 152         struct sk_buff *skb;
 153         dma_addr_t dma;
 154         dma_addr_t page_dma;
 155         union {
 156                 /* TX */
 157                 struct {
 158                         unsigned long time_stamp;
 159                         u16 length;
 160                         u16 next_to_watch;
 161                 };
 162
 163 #ifndef CONFIG_IGB_DISABLE_PACKET_SPLIT
 164                 /* RX */
 165                 struct {
 166                         unsigned long page_offset;
 167                         struct page *page;
 168                 };
 169 #endif
 170         };
 171 };
 172
 173 struct igb_queue_stats {
 174         u64 packets;
 175         u64 bytes;
 176 };
 177
 178 struct igb_q_vector {
 179         struct igb_adapter *adapter; /* backlink */
 180         struct igb_ring *rx_ring;
 181         struct igb_ring *tx_ring;
 182 #if 0
 183         struct napi_struct napi;
 184 #endif
 185         u32 eims_value;
 186         u16 cpu;
 187
 188         u16 itr_val;
 189         u8 set_itr;
 190         u8 itr_shift;
 191         void __iomem *itr_register;
 192
 193 #if 0
 194         char name[IFNAMSIZ + 9];
 195 #endif
 196 #ifndef HAVE_NETDEV_NAPI_LIST
 197         struct net_device poll_dev;
 198 #endif
 199 };
 200
 201 struct igb_ring {
 202         struct igb_q_vector *q_vector; /* backlink to q_vector */
 203         struct pci_dev *pdev;          /* pci device for dma mapping */
 204         dma_addr_t dma;                /* phys address of the ring */
 205         void *desc;                    /* descriptor ring memory */
 206         unsigned int size;             /* length of desc. ring in bytes */
 207         u16 count;                     /* number of desc. in the ring */
 208         u16 next_to_use;
 209         u16 next_to_clean;
 210         u8 queue_index;
 211         u8 reg_idx;
 212         void __iomem *head;
 213         void __iomem *tail;
 214         struct igb_buffer *buffer_info; /* array of buffer info structs */
 215
 216         unsigned int total_bytes;
 217         unsigned int total_packets;
 218
 219         struct igb_queue_stats stats;
 220
 221         union {
 222                 /* TX */
 223                 struct {
 224                         unsigned int restart_queue;
 225                         u32 ctx_idx;
 226                         bool detect_tx_hung;
 227                 };
 228                 /* RX */
 229                 struct {
 230                         u64 hw_csum_err;
 231                         u64 hw_csum_good;
 232                         u32 rx_buffer_len;
 233                         u16 rx_ps_hdr_size;
 234                         bool rx_csum;
 235 #ifdef IGB_LRO
 236                         struct net_lro_mgr lro_mgr;
 237                         bool lro_used;
 238 #endif
 239                 };
 240         };
 241 };
 242
 243
 244 #define IGB_ADVTXD_DCMD (E1000_ADVTXD_DCMD_EOP | E1000_ADVTXD_DCMD_RS)
 245
 246 #define IGB_DESC_UNUSED(R) \
 247         ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
 248         (R)->next_to_clean - (R)->next_to_use - 1)
 249
 250 #define E1000_RX_DESC_ADV(R, i)     \
 251         (&(((union e1000_adv_rx_desc *)((R).desc))[i]))
 252 #define E1000_TX_DESC_ADV(R, i)     \
 253         (&(((union e1000_adv_tx_desc *)((R).desc))[i]))
 254 #define E1000_TX_CTXTDESC_ADV(R, i)         \
 255         (&(((struct e1000_adv_tx_context_desc *)((R).desc))[i]))
 256 #define E1000_GET_DESC(R, i, type)      (&(((struct type *)((R).desc))[i]))
 257 #define E1000_TX_DESC(R, i)             E1000_GET_DESC(R, i, e1000_tx_desc)
 258 #define E1000_RX_DESC(R, i)             E1000_GET_DESC(R, i, e1000_rx_desc)
 259
 260 #define MAX_MSIX_COUNT 10
 261 /* board specific private data structure */
 262
 263 /* board specific private data structure */
 264 struct igb_adapter {
 265
 266         /* OS defined structs */
 267         struct net_device *netdev;
 268         struct pci_device *pdev;
 269         struct net_device_stats net_stats;
 270
 271         /* structs defined in e1000_hw.h */
 272         struct e1000_hw hw;
 273
 274         struct e1000_phy_info phy_info;
 275
 276         u32 min_frame_size;
 277         u32 max_frame_size;
 278
 279         u32 wol;
 280         u32 pba;
 281         u32 max_hw_frame_size;
 282
 283         bool fc_autoneg;
 284
 285         unsigned int flags;
 286         unsigned int flags2;
 287
 288 #define NUM_TX_DESC     8
 289 #define NUM_RX_DESC     8
 290
 291         struct io_buffer *tx_iobuf[NUM_TX_DESC];
 292         struct io_buffer *rx_iobuf[NUM_RX_DESC];
 293
 294         struct e1000_tx_desc *tx_base;
 295         struct e1000_rx_desc *rx_base;
 296
 297         uint32_t tx_ring_size;
 298         uint32_t rx_ring_size;
 299
 300         uint32_t tx_head;
 301         uint32_t tx_tail;
 302         uint32_t tx_fill_ctr;
 303
 304         uint32_t rx_curr;
 305
 306         uint32_t ioaddr;
 307         uint32_t irqno;
 308
 309         uint32_t tx_int_delay;
 310         uint32_t tx_abs_int_delay;
 311         uint32_t txd_cmd;
 312 };
 313
 314 #define IGB_FLAG_HAS_MSI           (1 << 0)
 315 #define IGB_FLAG_MSI_ENABLE        (1 << 1)
 316 #define IGB_FLAG_DCA_ENABLED       (1 << 3)
 317 #define IGB_FLAG_LLI_PUSH          (1 << 4)
 318 #define IGB_FLAG_IN_NETPOLL        (1 << 5)
 319 #define IGB_FLAG_QUAD_PORT_A       (1 << 6)
 320 #define IGB_FLAG_QUEUE_PAIRS       (1 << 7)
 321
 322 #define IGB_82576_TSYNC_SHIFT 19
 323
 324 #endif /* _IGB_H_ */