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[igb] Remove __BIG_ENDIAN conditional
[gpxe.git] / src / drivers / net / phantom / phantom.c
blob41cad18882417f05b3977eb2e1d4d4cdc79facac
1 /*
2 * Copyright (C) 2008 Michael Brown <mbrown@fensystems.co.uk>.
3 * Copyright (C) 2008 NetXen, Inc.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation; either version 2 of the
8 * License, or any later version.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
18 */
19
20 FILE_LICENCE ( GPL2_OR_LATER );
21
22 #include <stdint.h>
23 #include <stdlib.h>
24 #include <string.h>
25 #include <unistd.h>
26 #include <errno.h>
27 #include <assert.h>
28 #include <byteswap.h>
29 #include <gpxe/pci.h>
30 #include <gpxe/io.h>
31 #include <gpxe/malloc.h>
32 #include <gpxe/iobuf.h>
33 #include <gpxe/netdevice.h>
34 #include <gpxe/if_ether.h>
35 #include <gpxe/ethernet.h>
36 #include <gpxe/spi.h>
37 #include <gpxe/settings.h>
38 #include "phantom.h"
39
40 /**
41 * @file
42 *
43 * NetXen Phantom NICs
44 *
45 */
46
47 /** Maximum number of ports */
48 #define PHN_MAX_NUM_PORTS 8
49
50 /** Maximum time to wait for command PEG to initialise
51 *
52 * BUGxxxx
53 *
54 * The command PEG will currently report initialisation complete only
55 * when at least one PHY has detected a link (so that the global PHY
56 * clock can be set to 10G/1G as appropriate). This can take a very,
57 * very long time.
58 *
59 * A future firmware revision should decouple PHY initialisation from
60 * firmware initialisation, at which point the command PEG will report
61 * initialisation complete much earlier, and this timeout can be
62 * reduced.
63 */
64 #define PHN_CMDPEG_INIT_TIMEOUT_SEC 50
65
66 /** Maximum time to wait for receive PEG to initialise */
67 #define PHN_RCVPEG_INIT_TIMEOUT_SEC 2
68
69 /** Maximum time to wait for firmware to accept a command */
70 #define PHN_ISSUE_CMD_TIMEOUT_MS 2000
71
72 /** Maximum time to wait for test memory */
73 #define PHN_TEST_MEM_TIMEOUT_MS 100
74
75 /** Maximum time to wait for CLP command to be issued */
76 #define PHN_CLP_CMD_TIMEOUT_MS 500
77
78 /** Link state poll frequency
79 *
80 * The link state will be checked once in every N calls to poll().
81 */
82 #define PHN_LINK_POLL_FREQUENCY 4096
83
84 /** Number of RX descriptors */
85 #define PHN_NUM_RDS 32
86
87 /** RX maximum fill level. Must be strictly less than PHN_NUM_RDS. */
88 #define PHN_RDS_MAX_FILL 16
89
90 /** RX buffer size */
91 #define PHN_RX_BUFSIZE ( 32 /* max LL padding added by card */ + \
92 ETH_FRAME_LEN )
93
94 /** Number of RX status descriptors */
95 #define PHN_NUM_SDS 32
96
97 /** Number of TX descriptors */
98 #define PHN_NUM_CDS 8
99
100 /** A Phantom descriptor ring set */
101 struct phantom_descriptor_rings {
102 /** RX descriptors */
103 struct phantom_rds rds[PHN_NUM_RDS];
104 /** RX status descriptors */
105 struct phantom_sds sds[PHN_NUM_SDS];
106 /** TX descriptors */
107 union phantom_cds cds[PHN_NUM_CDS];
108 /** TX consumer index */
109 volatile uint32_t cmd_cons;
110 };
111
112 /** RX context creation request and response buffers */
113 struct phantom_create_rx_ctx_rqrsp {
114 struct {
115 struct nx_hostrq_rx_ctx_s rx_ctx;
116 struct nx_hostrq_rds_ring_s rds;
117 struct nx_hostrq_sds_ring_s sds;
118 } __unm_dma_aligned hostrq;
119 struct {
120 struct nx_cardrsp_rx_ctx_s rx_ctx;
121 struct nx_cardrsp_rds_ring_s rds;
122 struct nx_cardrsp_sds_ring_s sds;
123 } __unm_dma_aligned cardrsp;
124 };
125
126 /** TX context creation request and response buffers */
127 struct phantom_create_tx_ctx_rqrsp {
128 struct {
129 struct nx_hostrq_tx_ctx_s tx_ctx;
130 } __unm_dma_aligned hostrq;
131 struct {
132 struct nx_cardrsp_tx_ctx_s tx_ctx;
133 } __unm_dma_aligned cardrsp;
134 };
135
136 /** A Phantom NIC */
137 struct phantom_nic {
138 /** BAR 0 */
139 void *bar0;
140 /** Current CRB window */
141 unsigned long crb_window;
142 /** CRB window access method */
143 unsigned long ( *crb_access ) ( struct phantom_nic *phantom,
144 unsigned long reg );
145
146
147 /** Port number */
148 unsigned int port;
149
150
151 /** RX context ID */
152 uint16_t rx_context_id;
153 /** RX descriptor producer CRB offset */
154 unsigned long rds_producer_crb;
155 /** RX status descriptor consumer CRB offset */
156 unsigned long sds_consumer_crb;
157 /** RX interrupt mask CRB offset */
158 unsigned long sds_irq_mask_crb;
159 /** RX interrupts enabled */
160 unsigned int sds_irq_enabled;
161
162 /** RX producer index */
163 unsigned int rds_producer_idx;
164 /** RX consumer index */
165 unsigned int rds_consumer_idx;
166 /** RX status consumer index */
167 unsigned int sds_consumer_idx;
168 /** RX I/O buffers */
169 struct io_buffer *rds_iobuf[PHN_RDS_MAX_FILL];
170
171
172 /** TX context ID */
173 uint16_t tx_context_id;
174 /** TX descriptor producer CRB offset */
175 unsigned long cds_producer_crb;
176
177 /** TX producer index */
178 unsigned int cds_producer_idx;
179 /** TX consumer index */
180 unsigned int cds_consumer_idx;
181 /** TX I/O buffers */
182 struct io_buffer *cds_iobuf[PHN_NUM_CDS];
183
184
185 /** Descriptor rings */
186 struct phantom_descriptor_rings *desc;
187
188
189 /** Last known link state */
190 uint32_t link_state;
191 /** Link state poll timer */
192 unsigned long link_poll_timer;
193
194
195 /** Non-volatile settings */
196 struct settings settings;
197 };
198
199 /** Interrupt mask registers */
200 static const unsigned long phantom_irq_mask_reg[PHN_MAX_NUM_PORTS] = {
201 UNM_PCIE_IRQ_MASK_F0,
202 UNM_PCIE_IRQ_MASK_F1,
203 UNM_PCIE_IRQ_MASK_F2,
204 UNM_PCIE_IRQ_MASK_F3,
205 UNM_PCIE_IRQ_MASK_F4,
206 UNM_PCIE_IRQ_MASK_F5,
207 UNM_PCIE_IRQ_MASK_F6,
208 UNM_PCIE_IRQ_MASK_F7,
209 };
210
211 /** Interrupt status registers */
212 static const unsigned long phantom_irq_status_reg[PHN_MAX_NUM_PORTS] = {
213 UNM_PCIE_IRQ_STATUS_F0,
214 UNM_PCIE_IRQ_STATUS_F1,
215 UNM_PCIE_IRQ_STATUS_F2,
216 UNM_PCIE_IRQ_STATUS_F3,
217 UNM_PCIE_IRQ_STATUS_F4,
218 UNM_PCIE_IRQ_STATUS_F5,
219 UNM_PCIE_IRQ_STATUS_F6,
220 UNM_PCIE_IRQ_STATUS_F7,
221 };
222
223 /***************************************************************************
224 *
225 * CRB register access
226 *
227 */
228
229 /**
230 * Prepare for access to CRB register via 128MB BAR
231 *
232 * @v phantom Phantom NIC
233 * @v reg Register offset within abstract address space
234 * @ret offset Register offset within PCI BAR0
235 */
236 static unsigned long phantom_crb_access_128m ( struct phantom_nic *phantom,
237 unsigned long reg ) {
238 unsigned long offset = ( 0x6000000 + ( reg & 0x1ffffff ) );
239 uint32_t window = ( reg & 0x2000000 );
240 uint32_t verify_window;
241
242 if ( phantom->crb_window != window ) {
243
244 /* Write to the CRB window register */
245 writel ( window, phantom->bar0 + UNM_128M_CRB_WINDOW );
246
247 /* Ensure that the write has reached the card */
248 verify_window = readl ( phantom->bar0 + UNM_128M_CRB_WINDOW );
249 assert ( verify_window == window );
250
251 /* Record new window */
252 phantom->crb_window = window;
253 }
254
255 return offset;
256 }
257
258 /**
259 * Prepare for access to CRB register via 32MB BAR
260 *
261 * @v phantom Phantom NIC
262 * @v reg Register offset within abstract address space
263 * @ret offset Register offset within PCI BAR0
264 */
265 static unsigned long phantom_crb_access_32m ( struct phantom_nic *phantom,
266 unsigned long reg ) {
267 unsigned long offset = ( reg & 0x1ffffff );
268 uint32_t window = ( reg & 0x2000000 );
269 uint32_t verify_window;
270
271 if ( phantom->crb_window != window ) {
272
273 /* Write to the CRB window register */
274 writel ( window, phantom->bar0 + UNM_32M_CRB_WINDOW );
275
276 /* Ensure that the write has reached the card */
277 verify_window = readl ( phantom->bar0 + UNM_32M_CRB_WINDOW );
278 assert ( verify_window == window );
279
280 /* Record new window */
281 phantom->crb_window = window;
282 }
283
284 return offset;
285 }
286
287 /**
288 * Prepare for access to CRB register via 2MB BAR
289 *
290 * @v phantom Phantom NIC
291 * @v reg Register offset within abstract address space
292 * @ret offset Register offset within PCI BAR0
293 */
294 static unsigned long phantom_crb_access_2m ( struct phantom_nic *phantom,
295 unsigned long reg ) {
296 static const struct {
297 uint8_t block;
298 uint16_t window_hi;
299 } reg_window_hi[] = {
300 { UNM_CRB_BLK_PCIE, 0x773 },
301 { UNM_CRB_BLK_CAM, 0x416 },
302 { UNM_CRB_BLK_ROMUSB, 0x421 },
303 { UNM_CRB_BLK_TEST, 0x295 },
304 { UNM_CRB_BLK_PEG_0, 0x340 },
305 { UNM_CRB_BLK_PEG_1, 0x341 },
306 { UNM_CRB_BLK_PEG_2, 0x342 },
307 { UNM_CRB_BLK_PEG_3, 0x343 },
308 { UNM_CRB_BLK_PEG_4, 0x34b },
309 };
310 unsigned int block = UNM_CRB_BLK ( reg );
311 unsigned long offset = UNM_CRB_OFFSET ( reg );
312 uint32_t window;
313 uint32_t verify_window;
314 unsigned int i;
315
316 for ( i = 0 ; i < ( sizeof ( reg_window_hi ) /
317 sizeof ( reg_window_hi[0] ) ) ; i++ ) {
318
319 if ( reg_window_hi[i].block != block )
320 continue;
321
322 window = ( ( reg_window_hi[i].window_hi << 20 ) |
323 ( offset & 0x000f0000 ) );
324
325 if ( phantom->crb_window != window ) {
326
327 /* Write to the CRB window register */
328 writel ( window, phantom->bar0 + UNM_2M_CRB_WINDOW );
329
330 /* Ensure that the write has reached the card */
331 verify_window = readl ( phantom->bar0 +
332 UNM_2M_CRB_WINDOW );
333 assert ( verify_window == window );
334
335 /* Record new window */
336 phantom->crb_window = window;
337 }
338
339 return ( 0x1e0000 + ( offset & 0xffff ) );
340 }
341
342 assert ( 0 );
343 return 0;
344 }
345
346 /**
347 * Read from Phantom CRB register
348 *
349 * @v phantom Phantom NIC
350 * @v reg Register offset within abstract address space
351 * @ret value Register value
352 */
353 static uint32_t phantom_readl ( struct phantom_nic *phantom,
354 unsigned long reg ) {
355 unsigned long offset;
356
357 offset = phantom->crb_access ( phantom, reg );
358 return readl ( phantom->bar0 + offset );
359 }
360
361 /**
362 * Write to Phantom CRB register
363 *
364 * @v phantom Phantom NIC
365 * @v value Register value
366 * @v reg Register offset within abstract address space
367 */
368 static void phantom_writel ( struct phantom_nic *phantom, uint32_t value,
369 unsigned long reg ) {
370 unsigned long offset;
371
372 offset = phantom->crb_access ( phantom, reg );
373 writel ( value, phantom->bar0 + offset );
374 }
375
376 /**
377 * Write to Phantom CRB HI/LO register pair
378 *
379 * @v phantom Phantom NIC
380 * @v value Register value
381 * @v lo_offset LO register offset within CRB
382 * @v hi_offset HI register offset within CRB
383 */
384 static inline void phantom_write_hilo ( struct phantom_nic *phantom,
385 uint64_t value,
386 unsigned long lo_offset,
387 unsigned long hi_offset ) {
388 uint32_t lo = ( value & 0xffffffffUL );
389 uint32_t hi = ( value >> 32 );
390
391 phantom_writel ( phantom, lo, lo_offset );
392 phantom_writel ( phantom, hi, hi_offset );
393 }
394
395 /***************************************************************************
396 *
397 * Firmware message buffer access (for debug)
398 *
399 */
400
401 /**
402 * Read from Phantom test memory
403 *
404 * @v phantom Phantom NIC
405 * @v offset Offset within test memory
406 * @v buf 8-byte buffer to fill
407 * @ret rc Return status code
408 */
409 static int phantom_read_test_mem_block ( struct phantom_nic *phantom,
410 unsigned long offset,
411 uint32_t buf[2] ) {
412 unsigned int retries;
413 uint32_t test_control;
414
415 phantom_write_hilo ( phantom, offset, UNM_TEST_ADDR_LO,
416 UNM_TEST_ADDR_HI );
417 phantom_writel ( phantom, UNM_TEST_CONTROL_ENABLE, UNM_TEST_CONTROL );
418 phantom_writel ( phantom,
419 ( UNM_TEST_CONTROL_ENABLE | UNM_TEST_CONTROL_START ),
420 UNM_TEST_CONTROL );
421
422 for ( retries = 0 ; retries < PHN_TEST_MEM_TIMEOUT_MS ; retries++ ) {
423 test_control = phantom_readl ( phantom, UNM_TEST_CONTROL );
424 if ( ( test_control & UNM_TEST_CONTROL_BUSY ) == 0 ) {
425 buf[0] = phantom_readl ( phantom, UNM_TEST_RDDATA_LO );
426 buf[1] = phantom_readl ( phantom, UNM_TEST_RDDATA_HI );
427 return 0;
428 }
429 mdelay ( 1 );
430 }
431
432 DBGC ( phantom, "Phantom %p timed out waiting for test memory\n",
433 phantom );
434 return -ETIMEDOUT;
435 }
436
437 /**
438 * Read single byte from Phantom test memory
439 *
440 * @v phantom Phantom NIC
441 * @v offset Offset within test memory
442 * @ret byte Byte read, or negative error
443 */
444 static int phantom_read_test_mem ( struct phantom_nic *phantom,
445 unsigned long offset ) {
446 static union {
447 uint8_t bytes[8];
448 uint32_t dwords[2];
449 } cache;
450 static unsigned long cache_offset = -1UL;
451 unsigned long sub_offset;
452 int rc;
453
454 sub_offset = ( offset & ( sizeof ( cache ) - 1 ) );
455 offset = ( offset & ~( sizeof ( cache ) - 1 ) );
456
457 if ( cache_offset != offset ) {
458 if ( ( rc = phantom_read_test_mem_block ( phantom, offset,
459 cache.dwords )) !=0 )
460 return rc;
461 cache_offset = offset;
462 }
463
464 return cache.bytes[sub_offset];
465 }
466
467 /**
468 * Dump Phantom firmware dmesg log
469 *
470 * @v phantom Phantom NIC
471 * @v log Log number
472 * @v max_lines Maximum number of lines to show, or -1 to show all
473 * @ret rc Return status code
474 */
475 static int phantom_dmesg ( struct phantom_nic *phantom, unsigned int log,
476 unsigned int max_lines ) {
477 uint32_t head;
478 uint32_t tail;
479 uint32_t len;
480 uint32_t sig;
481 uint32_t offset;
482 int byte;
483
484 /* Optimise out for non-debug builds */
485 if ( ! DBG_LOG )
486 return 0;
487
488 /* Locate log */
489 head = phantom_readl ( phantom, UNM_CAM_RAM_DMESG_HEAD ( log ) );
490 len = phantom_readl ( phantom, UNM_CAM_RAM_DMESG_LEN ( log ) );
491 tail = phantom_readl ( phantom, UNM_CAM_RAM_DMESG_TAIL ( log ) );
492 sig = phantom_readl ( phantom, UNM_CAM_RAM_DMESG_SIG ( log ) );
493 DBGC ( phantom, "Phantom %p firmware dmesg buffer %d (%08x-%08x)\n",
494 phantom, log, head, tail );
495 assert ( ( head & 0x07 ) == 0 );
496 if ( sig != UNM_CAM_RAM_DMESG_SIG_MAGIC ) {
497 DBGC ( phantom, "Warning: bad signature %08x (want %08lx)\n",
498 sig, UNM_CAM_RAM_DMESG_SIG_MAGIC );
499 }
500
501 /* Locate start of last (max_lines) lines */
502 for ( offset = tail ; offset > head ; offset-- ) {
503 if ( ( byte = phantom_read_test_mem ( phantom,
504 ( offset - 1 ) ) ) < 0 )
505 return byte;
506 if ( ( byte == '\n' ) && ( max_lines-- == 0 ) )
507 break;
508 }
509
510 /* Print lines */
511 for ( ; offset < tail ; offset++ ) {
512 if ( ( byte = phantom_read_test_mem ( phantom, offset ) ) < 0 )
513 return byte;
514 DBG ( "%c", byte );
515 }
516 DBG ( "\n" );
517 return 0;
518 }
519
520 /**
521 * Dump Phantom firmware dmesg logs
522 *
523 * @v phantom Phantom NIC
524 * @v max_lines Maximum number of lines to show, or -1 to show all
525 */
526 static void __attribute__ (( unused ))
527 phantom_dmesg_all ( struct phantom_nic *phantom, unsigned int max_lines ) {
528 unsigned int i;
529
530 for ( i = 0 ; i < UNM_CAM_RAM_NUM_DMESG_BUFFERS ; i++ )
531 phantom_dmesg ( phantom, i, max_lines );
532 }
533
534 /***************************************************************************
535 *
536 * Firmware interface
537 *
538 */
539
540 /**
541 * Wait for firmware to accept command
542 *
543 * @v phantom Phantom NIC
544 * @ret rc Return status code
545 */
546 static int phantom_wait_for_cmd ( struct phantom_nic *phantom ) {
547 unsigned int retries;
548 uint32_t cdrp;
549
550 for ( retries = 0 ; retries < PHN_ISSUE_CMD_TIMEOUT_MS ; retries++ ) {
551 mdelay ( 1 );
552 cdrp = phantom_readl ( phantom, UNM_NIC_REG_NX_CDRP );
553 if ( NX_CDRP_IS_RSP ( cdrp ) ) {
554 switch ( NX_CDRP_FORM_RSP ( cdrp ) ) {
555 case NX_CDRP_RSP_OK:
556 return 0;
557 case NX_CDRP_RSP_FAIL:
558 return -EIO;
559 case NX_CDRP_RSP_TIMEOUT:
560 return -ETIMEDOUT;
561 default:
562 return -EPROTO;
563 }
564 }
565 }
566
567 DBGC ( phantom, "Phantom %p timed out waiting for firmware to accept "
568 "command\n", phantom );
569 return -ETIMEDOUT;
570 }
571
572 /**
573 * Issue command to firmware
574 *
575 * @v phantom Phantom NIC
576 * @v command Firmware command
577 * @v arg1 Argument 1
578 * @v arg2 Argument 2
579 * @v arg3 Argument 3
580 * @ret rc Return status code
581 */
582 static int phantom_issue_cmd ( struct phantom_nic *phantom,
583 uint32_t command, uint32_t arg1, uint32_t arg2,
584 uint32_t arg3 ) {
585 uint32_t signature;
586 int rc;
587
588 /* Issue command */
589 signature = NX_CDRP_SIGNATURE_MAKE ( phantom->port,
590 NXHAL_VERSION );
591 DBGC2 ( phantom, "Phantom %p issuing command %08x (%08x, %08x, "
592 "%08x)\n", phantom, command, arg1, arg2, arg3 );
593 phantom_writel ( phantom, signature, UNM_NIC_REG_NX_SIGN );
594 phantom_writel ( phantom, arg1, UNM_NIC_REG_NX_ARG1 );
595 phantom_writel ( phantom, arg2, UNM_NIC_REG_NX_ARG2 );
596 phantom_writel ( phantom, arg3, UNM_NIC_REG_NX_ARG3 );
597 phantom_writel ( phantom, NX_CDRP_FORM_CMD ( command ),
598 UNM_NIC_REG_NX_CDRP );
599
600 /* Wait for command to be accepted */
601 if ( ( rc = phantom_wait_for_cmd ( phantom ) ) != 0 ) {
602 DBGC ( phantom, "Phantom %p could not issue command: %s\n",
603 phantom, strerror ( rc ) );
604 return rc;
605 }
606
607 return 0;
608 }
609
610 /**
611 * Issue buffer-format command to firmware
612 *
613 * @v phantom Phantom NIC
614 * @v command Firmware command
615 * @v buffer Buffer to pass to firmware
616 * @v len Length of buffer
617 * @ret rc Return status code
618 */
619 static int phantom_issue_buf_cmd ( struct phantom_nic *phantom,
620 uint32_t command, void *buffer,
621 size_t len ) {
622 uint64_t physaddr;
623
624 physaddr = virt_to_bus ( buffer );
625 return phantom_issue_cmd ( phantom, command, ( physaddr >> 32 ),
626 ( physaddr & 0xffffffffUL ), len );
627 }
628
629 /**
630 * Create Phantom RX context
631 *
632 * @v phantom Phantom NIC
633 * @ret rc Return status code
634 */
635 static int phantom_create_rx_ctx ( struct phantom_nic *phantom ) {
636 struct phantom_create_rx_ctx_rqrsp *buf;
637 int rc;
638
639 /* Allocate context creation buffer */
640 buf = malloc_dma ( sizeof ( *buf ), UNM_DMA_BUFFER_ALIGN );
641 if ( ! buf ) {
642 rc = -ENOMEM;
643 goto out;
644 }
645 memset ( buf, 0, sizeof ( *buf ) );
646
647 /* Prepare request */
648 buf->hostrq.rx_ctx.host_rsp_dma_addr =
649 cpu_to_le64 ( virt_to_bus ( &buf->cardrsp ) );
650 buf->hostrq.rx_ctx.capabilities[0] =
651 cpu_to_le32 ( NX_CAP0_LEGACY_CONTEXT | NX_CAP0_LEGACY_MN );
652 buf->hostrq.rx_ctx.host_int_crb_mode =
653 cpu_to_le32 ( NX_HOST_INT_CRB_MODE_SHARED );
654 buf->hostrq.rx_ctx.host_rds_crb_mode =
655 cpu_to_le32 ( NX_HOST_RDS_CRB_MODE_UNIQUE );
656 buf->hostrq.rx_ctx.rds_ring_offset = cpu_to_le32 ( 0 );
657 buf->hostrq.rx_ctx.sds_ring_offset =
658 cpu_to_le32 ( sizeof ( buf->hostrq.rds ) );
659 buf->hostrq.rx_ctx.num_rds_rings = cpu_to_le16 ( 1 );
660 buf->hostrq.rx_ctx.num_sds_rings = cpu_to_le16 ( 1 );
661 buf->hostrq.rds.host_phys_addr =
662 cpu_to_le64 ( virt_to_bus ( phantom->desc->rds ) );
663 buf->hostrq.rds.buff_size = cpu_to_le64 ( PHN_RX_BUFSIZE );
664 buf->hostrq.rds.ring_size = cpu_to_le32 ( PHN_NUM_RDS );
665 buf->hostrq.rds.ring_kind = cpu_to_le32 ( NX_RDS_RING_TYPE_NORMAL );
666 buf->hostrq.sds.host_phys_addr =
667 cpu_to_le64 ( virt_to_bus ( phantom->desc->sds ) );
668 buf->hostrq.sds.ring_size = cpu_to_le32 ( PHN_NUM_SDS );
669
670 DBGC ( phantom, "Phantom %p creating RX context\n", phantom );
671 DBGC2_HDA ( phantom, virt_to_bus ( &buf->hostrq ),
672 &buf->hostrq, sizeof ( buf->hostrq ) );
673
674 /* Issue request */
675 if ( ( rc = phantom_issue_buf_cmd ( phantom,
676 NX_CDRP_CMD_CREATE_RX_CTX,
677 &buf->hostrq,
678 sizeof ( buf->hostrq ) ) ) != 0 ) {
679 DBGC ( phantom, "Phantom %p could not create RX context: "
680 "%s\n", phantom, strerror ( rc ) );
681 DBGC ( phantom, "Request:\n" );
682 DBGC_HDA ( phantom, virt_to_bus ( &buf->hostrq ),
683 &buf->hostrq, sizeof ( buf->hostrq ) );
684 DBGC ( phantom, "Response:\n" );
685 DBGC_HDA ( phantom, virt_to_bus ( &buf->cardrsp ),
686 &buf->cardrsp, sizeof ( buf->cardrsp ) );
687 goto out;
688 }
689
690 /* Retrieve context parameters */
691 phantom->rx_context_id =
692 le16_to_cpu ( buf->cardrsp.rx_ctx.context_id );
693 phantom->rds_producer_crb =
694 ( UNM_CAM_RAM +
695 le32_to_cpu ( buf->cardrsp.rds.host_producer_crb ) );
696 phantom->sds_consumer_crb =
697 ( UNM_CAM_RAM +
698 le32_to_cpu ( buf->cardrsp.sds.host_consumer_crb ) );
699 phantom->sds_irq_mask_crb =
700 ( UNM_CAM_RAM +
701 le32_to_cpu ( buf->cardrsp.sds.interrupt_crb ) );
702
703 DBGC ( phantom, "Phantom %p created RX context (id %04x, port phys "
704 "%02x virt %02x)\n", phantom, phantom->rx_context_id,
705 buf->cardrsp.rx_ctx.phys_port, buf->cardrsp.rx_ctx.virt_port );
706 DBGC2_HDA ( phantom, virt_to_bus ( &buf->cardrsp ),
707 &buf->cardrsp, sizeof ( buf->cardrsp ) );
708 DBGC ( phantom, "Phantom %p RDS producer CRB is %08lx\n",
709 phantom, phantom->rds_producer_crb );
710 DBGC ( phantom, "Phantom %p SDS consumer CRB is %08lx\n",
711 phantom, phantom->sds_consumer_crb );
712 DBGC ( phantom, "Phantom %p SDS interrupt mask CRB is %08lx\n",
713 phantom, phantom->sds_irq_mask_crb );
714
715 out:
716 free_dma ( buf, sizeof ( *buf ) );
717 return rc;
718 }
719
720 /**
721 * Destroy Phantom RX context
722 *
723 * @v phantom Phantom NIC
724 * @ret rc Return status code
725 */
726 static void phantom_destroy_rx_ctx ( struct phantom_nic *phantom ) {
727 int rc;
728
729 DBGC ( phantom, "Phantom %p destroying RX context (id %04x)\n",
730 phantom, phantom->rx_context_id );
731
732 /* Issue request */
733 if ( ( rc = phantom_issue_cmd ( phantom,
734 NX_CDRP_CMD_DESTROY_RX_CTX,
735 phantom->rx_context_id,
736 NX_DESTROY_CTX_RESET, 0 ) ) != 0 ) {
737 DBGC ( phantom, "Phantom %p could not destroy RX context: "
738 "%s\n", phantom, strerror ( rc ) );
739 /* We're probably screwed */
740 return;
741 }
742
743 /* Clear context parameters */
744 phantom->rx_context_id = 0;
745 phantom->rds_producer_crb = 0;
746 phantom->sds_consumer_crb = 0;
747
748 /* Reset software counters */
749 phantom->rds_producer_idx = 0;
750 phantom->rds_consumer_idx = 0;
751 phantom->sds_consumer_idx = 0;
752 }
753
754 /**
755 * Create Phantom TX context
756 *
757 * @v phantom Phantom NIC
758 * @ret rc Return status code
759 */
760 static int phantom_create_tx_ctx ( struct phantom_nic *phantom ) {
761 struct phantom_create_tx_ctx_rqrsp *buf;
762 int rc;
763
764 /* Allocate context creation buffer */
765 buf = malloc_dma ( sizeof ( *buf ), UNM_DMA_BUFFER_ALIGN );
766 if ( ! buf ) {
767 rc = -ENOMEM;
768 goto out;
769 }
770 memset ( buf, 0, sizeof ( *buf ) );
771
772 /* Prepare request */
773 buf->hostrq.tx_ctx.host_rsp_dma_addr =
774 cpu_to_le64 ( virt_to_bus ( &buf->cardrsp ) );
775 buf->hostrq.tx_ctx.cmd_cons_dma_addr =
776 cpu_to_le64 ( virt_to_bus ( &phantom->desc->cmd_cons ) );
777 buf->hostrq.tx_ctx.capabilities[0] =
778 cpu_to_le32 ( NX_CAP0_LEGACY_CONTEXT | NX_CAP0_LEGACY_MN );
779 buf->hostrq.tx_ctx.host_int_crb_mode =
780 cpu_to_le32 ( NX_HOST_INT_CRB_MODE_SHARED );
781 buf->hostrq.tx_ctx.cds_ring.host_phys_addr =
782 cpu_to_le64 ( virt_to_bus ( phantom->desc->cds ) );
783 buf->hostrq.tx_ctx.cds_ring.ring_size = cpu_to_le32 ( PHN_NUM_CDS );
784
785 DBGC ( phantom, "Phantom %p creating TX context\n", phantom );
786 DBGC2_HDA ( phantom, virt_to_bus ( &buf->hostrq ),
787 &buf->hostrq, sizeof ( buf->hostrq ) );
788
789 /* Issue request */
790 if ( ( rc = phantom_issue_buf_cmd ( phantom,
791 NX_CDRP_CMD_CREATE_TX_CTX,
792 &buf->hostrq,
793 sizeof ( buf->hostrq ) ) ) != 0 ) {
794 DBGC ( phantom, "Phantom %p could not create TX context: "
795 "%s\n", phantom, strerror ( rc ) );
796 DBGC ( phantom, "Request:\n" );
797 DBGC_HDA ( phantom, virt_to_bus ( &buf->hostrq ),
798 &buf->hostrq, sizeof ( buf->hostrq ) );
799 DBGC ( phantom, "Response:\n" );
800 DBGC_HDA ( phantom, virt_to_bus ( &buf->cardrsp ),
801 &buf->cardrsp, sizeof ( buf->cardrsp ) );
802 goto out;
803 }
804
805 /* Retrieve context parameters */
806 phantom->tx_context_id =
807 le16_to_cpu ( buf->cardrsp.tx_ctx.context_id );
808 phantom->cds_producer_crb =
809 ( UNM_CAM_RAM +
810 le32_to_cpu(buf->cardrsp.tx_ctx.cds_ring.host_producer_crb));
811
812 DBGC ( phantom, "Phantom %p created TX context (id %04x, port phys "
813 "%02x virt %02x)\n", phantom, phantom->tx_context_id,
814 buf->cardrsp.tx_ctx.phys_port, buf->cardrsp.tx_ctx.virt_port );
815 DBGC2_HDA ( phantom, virt_to_bus ( &buf->cardrsp ),
816 &buf->cardrsp, sizeof ( buf->cardrsp ) );
817 DBGC ( phantom, "Phantom %p CDS producer CRB is %08lx\n",
818 phantom, phantom->cds_producer_crb );
819
820 out:
821 free_dma ( buf, sizeof ( *buf ) );
822 return rc;
823 }
824
825 /**
826 * Destroy Phantom TX context
827 *
828 * @v phantom Phantom NIC
829 * @ret rc Return status code
830 */
831 static void phantom_destroy_tx_ctx ( struct phantom_nic *phantom ) {
832 int rc;
833
834 DBGC ( phantom, "Phantom %p destroying TX context (id %04x)\n",
835 phantom, phantom->tx_context_id );
836
837 /* Issue request */
838 if ( ( rc = phantom_issue_cmd ( phantom,
839 NX_CDRP_CMD_DESTROY_TX_CTX,
840 phantom->tx_context_id,
841 NX_DESTROY_CTX_RESET, 0 ) ) != 0 ) {
842 DBGC ( phantom, "Phantom %p could not destroy TX context: "
843 "%s\n", phantom, strerror ( rc ) );
844 /* We're probably screwed */
845 return;
846 }
847
848 /* Clear context parameters */
849 phantom->tx_context_id = 0;
850 phantom->cds_producer_crb = 0;
851
852 /* Reset software counters */
853 phantom->cds_producer_idx = 0;
854 phantom->cds_consumer_idx = 0;
855 }
856
857 /***************************************************************************
858 *
859 * Descriptor ring management
860 *
861 */
862
863 /**
864 * Allocate Phantom RX descriptor
865 *
866 * @v phantom Phantom NIC
867 * @ret index RX descriptor index, or negative error
868 */
869 static int phantom_alloc_rds ( struct phantom_nic *phantom ) {
870 unsigned int rds_producer_idx;
871 unsigned int next_rds_producer_idx;
872
873 /* Check for space in the ring. RX descriptors are consumed
874 * out of order, but they are *read* by the hardware in strict
875 * order. We maintain a pessimistic consumer index, which is
876 * guaranteed never to be an overestimate of the number of
877 * descriptors read by the hardware.
878 */
879 rds_producer_idx = phantom->rds_producer_idx;
880 next_rds_producer_idx = ( ( rds_producer_idx + 1 ) % PHN_NUM_RDS );
881 if ( next_rds_producer_idx == phantom->rds_consumer_idx ) {
882 DBGC ( phantom, "Phantom %p RDS ring full (index %d not "
883 "consumed)\n", phantom, next_rds_producer_idx );
884 return -ENOBUFS;
885 }
886
887 return rds_producer_idx;
888 }
889
890 /**
891 * Post Phantom RX descriptor
892 *
893 * @v phantom Phantom NIC
894 * @v rds RX descriptor
895 */
896 static void phantom_post_rds ( struct phantom_nic *phantom,
897 struct phantom_rds *rds ) {
898 unsigned int rds_producer_idx;
899 unsigned int next_rds_producer_idx;
900 struct phantom_rds *entry;
901
902 /* Copy descriptor to ring */
903 rds_producer_idx = phantom->rds_producer_idx;
904 entry = &phantom->desc->rds[rds_producer_idx];
905 memcpy ( entry, rds, sizeof ( *entry ) );
906 DBGC2 ( phantom, "Phantom %p posting RDS %ld (slot %d):\n",
907 phantom, NX_GET ( rds, handle ), rds_producer_idx );
908 DBGC2_HDA ( phantom, virt_to_bus ( entry ), entry, sizeof ( *entry ) );
909
910 /* Update producer index */
911 next_rds_producer_idx = ( ( rds_producer_idx + 1 ) % PHN_NUM_RDS );
912 phantom->rds_producer_idx = next_rds_producer_idx;
913 wmb();
914 phantom_writel ( phantom, phantom->rds_producer_idx,
915 phantom->rds_producer_crb );
916 }
917
918 /**
919 * Allocate Phantom TX descriptor
920 *
921 * @v phantom Phantom NIC
922 * @ret index TX descriptor index, or negative error
923 */
924 static int phantom_alloc_cds ( struct phantom_nic *phantom ) {
925 unsigned int cds_producer_idx;
926 unsigned int next_cds_producer_idx;
927
928 /* Check for space in the ring. TX descriptors are consumed
929 * in strict order, so we just check for a collision against
930 * the consumer index.
931 */
932 cds_producer_idx = phantom->cds_producer_idx;
933 next_cds_producer_idx = ( ( cds_producer_idx + 1 ) % PHN_NUM_CDS );
934 if ( next_cds_producer_idx == phantom->cds_consumer_idx ) {
935 DBGC ( phantom, "Phantom %p CDS ring full (index %d not "
936 "consumed)\n", phantom, next_cds_producer_idx );
937 return -ENOBUFS;
938 }
939
940 return cds_producer_idx;
941 }
942
943 /**
944 * Post Phantom TX descriptor
945 *
946 * @v phantom Phantom NIC
947 * @v cds TX descriptor
948 */
949 static void phantom_post_cds ( struct phantom_nic *phantom,
950 union phantom_cds *cds ) {
951 unsigned int cds_producer_idx;
952 unsigned int next_cds_producer_idx;
953 union phantom_cds *entry;
954
955 /* Copy descriptor to ring */
956 cds_producer_idx = phantom->cds_producer_idx;
957 entry = &phantom->desc->cds[cds_producer_idx];
958 memcpy ( entry, cds, sizeof ( *entry ) );
959 DBGC2 ( phantom, "Phantom %p posting CDS %d:\n",
960 phantom, cds_producer_idx );
961 DBGC2_HDA ( phantom, virt_to_bus ( entry ), entry, sizeof ( *entry ) );
962
963 /* Update producer index */
964 next_cds_producer_idx = ( ( cds_producer_idx + 1 ) % PHN_NUM_CDS );
965 phantom->cds_producer_idx = next_cds_producer_idx;
966 wmb();
967 phantom_writel ( phantom, phantom->cds_producer_idx,
968 phantom->cds_producer_crb );
969 }
970
971 /***************************************************************************
972 *
973 * MAC address management
974 *
975 */
976
977 /**
978 * Add/remove MAC address
979 *
980 * @v phantom Phantom NIC
981 * @v ll_addr MAC address to add or remove
982 * @v opcode MAC request opcode
983 * @ret rc Return status code
984 */
985 static int phantom_update_macaddr ( struct phantom_nic *phantom,
986 const uint8_t *ll_addr,
987 unsigned int opcode ) {
988 union phantom_cds cds;
989 int index;
990
991 /* Get descriptor ring entry */
992 index = phantom_alloc_cds ( phantom );
993 if ( index < 0 )
994 return index;
995
996 /* Fill descriptor ring entry */
997 memset ( &cds, 0, sizeof ( cds ) );
998 NX_FILL_1 ( &cds, 0,
999 nic_request.common.opcode, UNM_NIC_REQUEST );
1000 NX_FILL_2 ( &cds, 1,
1001 nic_request.header.opcode, UNM_MAC_EVENT,
1002 nic_request.header.context_id, phantom->port );
1003 NX_FILL_7 ( &cds, 2,
1004 nic_request.body.mac_request.opcode, opcode,
1005 nic_request.body.mac_request.mac_addr_0, ll_addr[0],
1006 nic_request.body.mac_request.mac_addr_1, ll_addr[1],
1007 nic_request.body.mac_request.mac_addr_2, ll_addr[2],
1008 nic_request.body.mac_request.mac_addr_3, ll_addr[3],
1009 nic_request.body.mac_request.mac_addr_4, ll_addr[4],
1010 nic_request.body.mac_request.mac_addr_5, ll_addr[5] );
1011
1012 /* Post descriptor */
1013 phantom_post_cds ( phantom, &cds );
1014
1015 return 0;
1016 }
1017
1018 /**
1019 * Add MAC address
1020 *
1021 * @v phantom Phantom NIC
1022 * @v ll_addr MAC address to add or remove
1023 * @ret rc Return status code
1024 */
1025 static inline int phantom_add_macaddr ( struct phantom_nic *phantom,
1026 const uint8_t *ll_addr ) {
1027
1028 DBGC ( phantom, "Phantom %p adding MAC address %s\n",
1029 phantom, eth_ntoa ( ll_addr ) );
1030
1031 return phantom_update_macaddr ( phantom, ll_addr, UNM_MAC_ADD );
1032 }
1033
1034 /**
1035 * Remove MAC address
1036 *
1037 * @v phantom Phantom NIC
1038 * @v ll_addr MAC address to add or remove
1039 * @ret rc Return status code
1040 */
1041 static inline int phantom_del_macaddr ( struct phantom_nic *phantom,
1042 const uint8_t *ll_addr ) {
1043
1044 DBGC ( phantom, "Phantom %p removing MAC address %s\n",
1045 phantom, eth_ntoa ( ll_addr ) );
1046
1047 return phantom_update_macaddr ( phantom, ll_addr, UNM_MAC_DEL );
1048 }
1049
1050 /***************************************************************************
1051 *
1052 * Link state detection
1053 *
1054 */
1055
1056 /**
1057 * Poll link state
1058 *
1059 * @v netdev Network device
1060 */
1061 static void phantom_poll_link_state ( struct net_device *netdev ) {
1062 struct phantom_nic *phantom = netdev_priv ( netdev );
1063 uint32_t xg_state_p3;
1064 unsigned int link;
1065
1066 /* Read link state */
1067 xg_state_p3 = phantom_readl ( phantom, UNM_NIC_REG_XG_STATE_P3 );
1068
1069 /* If there is no change, do nothing */
1070 if ( phantom->link_state == xg_state_p3 )
1071 return;
1072
1073 /* Record new link state */
1074 DBGC ( phantom, "Phantom %p new link state %08x (was %08x)\n",
1075 phantom, xg_state_p3, phantom->link_state );
1076 phantom->link_state = xg_state_p3;
1077
1078 /* Indicate link state to gPXE */
1079 link = UNM_NIC_REG_XG_STATE_P3_LINK ( phantom->port,
1080 phantom->link_state );
1081 switch ( link ) {
1082 case UNM_NIC_REG_XG_STATE_P3_LINK_UP:
1083 DBGC ( phantom, "Phantom %p link is up\n", phantom );
1084 netdev_link_up ( netdev );
1085 break;
1086 case UNM_NIC_REG_XG_STATE_P3_LINK_DOWN:
1087 DBGC ( phantom, "Phantom %p link is down\n", phantom );
1088 netdev_link_down ( netdev );
1089 break;
1090 default:
1091 DBGC ( phantom, "Phantom %p bad link state %d\n",
1092 phantom, link );
1093 break;
1094 }
1095 }
1096
1097 /***************************************************************************
1098 *
1099 * Main driver body
1100 *
1101 */
1102
1103 /**
1104 * Refill descriptor ring
1105 *
1106 * @v netdev Net device
1107 */
1108 static void phantom_refill_rx_ring ( struct net_device *netdev ) {
1109 struct phantom_nic *phantom = netdev_priv ( netdev );
1110 struct io_buffer *iobuf;
1111 struct phantom_rds rds;
1112 unsigned int handle;
1113 int index;
1114
1115 for ( handle = 0 ; handle < PHN_RDS_MAX_FILL ; handle++ ) {
1116
1117 /* Skip this index if the descriptor has not yet been
1118 * consumed.
1119 */
1120 if ( phantom->rds_iobuf[handle] != NULL )
1121 continue;
1122
1123 /* Allocate descriptor ring entry */
1124 index = phantom_alloc_rds ( phantom );
1125 assert ( PHN_RDS_MAX_FILL < PHN_NUM_RDS );
1126 assert ( index >= 0 ); /* Guaranteed by MAX_FILL < NUM_RDS ) */
1127
1128 /* Try to allocate an I/O buffer */
1129 iobuf = alloc_iob ( PHN_RX_BUFSIZE );
1130 if ( ! iobuf ) {
1131 /* Failure is non-fatal; we will retry later */
1132 netdev_rx_err ( netdev, NULL, -ENOMEM );
1133 break;
1134 }
1135
1136 /* Fill descriptor ring entry */
1137 memset ( &rds, 0, sizeof ( rds ) );
1138 NX_FILL_2 ( &rds, 0,
1139 handle, handle,
1140 length, iob_len ( iobuf ) );
1141 NX_FILL_1 ( &rds, 1,
1142 dma_addr, virt_to_bus ( iobuf->data ) );
1143
1144 /* Record I/O buffer */
1145 assert ( phantom->rds_iobuf[handle] == NULL );
1146 phantom->rds_iobuf[handle] = iobuf;
1147
1148 /* Post descriptor */
1149 phantom_post_rds ( phantom, &rds );
1150 }
1151 }
1152
1153 /**
1154 * Open NIC
1155 *
1156 * @v netdev Net device
1157 * @ret rc Return status code
1158 */
1159 static int phantom_open ( struct net_device *netdev ) {
1160 struct phantom_nic *phantom = netdev_priv ( netdev );
1161 int rc;
1162
1163 /* Allocate and zero descriptor rings */
1164 phantom->desc = malloc_dma ( sizeof ( *(phantom->desc) ),
1165 UNM_DMA_BUFFER_ALIGN );
1166 if ( ! phantom->desc ) {
1167 rc = -ENOMEM;
1168 goto err_alloc_desc;
1169 }
1170 memset ( phantom->desc, 0, sizeof ( *(phantom->desc) ) );
1171
1172 /* Create RX context */
1173 if ( ( rc = phantom_create_rx_ctx ( phantom ) ) != 0 )
1174 goto err_create_rx_ctx;
1175
1176 /* Create TX context */
1177 if ( ( rc = phantom_create_tx_ctx ( phantom ) ) != 0 )
1178 goto err_create_tx_ctx;
1179
1180 /* Fill the RX descriptor ring */
1181 phantom_refill_rx_ring ( netdev );
1182
1183 /* Add MAC addresses
1184 *
1185 * BUG5583
1186 *
1187 * We would like to be able to enable receiving all multicast
1188 * packets (or, failing that, promiscuous mode), but the
1189 * firmware doesn't currently support this.
1190 */
1191 if ( ( rc = phantom_add_macaddr ( phantom,
1192 netdev->ll_broadcast ) ) != 0 )
1193 goto err_add_macaddr_broadcast;
1194 if ( ( rc = phantom_add_macaddr ( phantom,
1195 netdev->ll_addr ) ) != 0 )
1196 goto err_add_macaddr_unicast;
1197
1198 return 0;
1199
1200 phantom_del_macaddr ( phantom, netdev->ll_addr );
1201 err_add_macaddr_unicast:
1202 phantom_del_macaddr ( phantom, netdev->ll_broadcast );
1203 err_add_macaddr_broadcast:
1204 phantom_destroy_tx_ctx ( phantom );
1205 err_create_tx_ctx:
1206 phantom_destroy_rx_ctx ( phantom );
1207 err_create_rx_ctx:
1208 free_dma ( phantom->desc, sizeof ( *(phantom->desc) ) );
1209 phantom->desc = NULL;
1210 err_alloc_desc:
1211 return rc;
1212 }
1213
1214 /**
1215 * Close NIC
1216 *
1217 * @v netdev Net device
1218 */
1219 static void phantom_close ( struct net_device *netdev ) {
1220 struct phantom_nic *phantom = netdev_priv ( netdev );
1221 struct io_buffer *iobuf;
1222 unsigned int i;
1223
1224 /* Shut down the port */
1225 phantom_del_macaddr ( phantom, netdev->ll_addr );
1226 phantom_del_macaddr ( phantom, netdev->ll_broadcast );
1227 phantom_destroy_tx_ctx ( phantom );
1228 phantom_destroy_rx_ctx ( phantom );
1229 free_dma ( phantom->desc, sizeof ( *(phantom->desc) ) );
1230 phantom->desc = NULL;
1231
1232 /* Flush any uncompleted descriptors */
1233 for ( i = 0 ; i < PHN_RDS_MAX_FILL ; i++ ) {
1234 iobuf = phantom->rds_iobuf[i];
1235 if ( iobuf ) {
1236 free_iob ( iobuf );
1237 phantom->rds_iobuf[i] = NULL;
1238 }
1239 }
1240 for ( i = 0 ; i < PHN_NUM_CDS ; i++ ) {
1241 iobuf = phantom->cds_iobuf[i];
1242 if ( iobuf ) {
1243 netdev_tx_complete_err ( netdev, iobuf, -ECANCELED );
1244 phantom->cds_iobuf[i] = NULL;
1245 }
1246 }
1247 }
1248
1249 /**
1250 * Transmit packet
1251 *
1252 * @v netdev Network device
1253 * @v iobuf I/O buffer
1254 * @ret rc Return status code
1255 */
1256 static int phantom_transmit ( struct net_device *netdev,
1257 struct io_buffer *iobuf ) {
1258 struct phantom_nic *phantom = netdev_priv ( netdev );
1259 union phantom_cds cds;
1260 int index;
1261
1262 /* Get descriptor ring entry */
1263 index = phantom_alloc_cds ( phantom );
1264 if ( index < 0 )
1265 return index;
1266
1267 /* Fill descriptor ring entry */
1268 memset ( &cds, 0, sizeof ( cds ) );
1269 NX_FILL_3 ( &cds, 0,
1270 tx.opcode, UNM_TX_ETHER_PKT,
1271 tx.num_buffers, 1,
1272 tx.length, iob_len ( iobuf ) );
1273 NX_FILL_2 ( &cds, 2,
1274 tx.port, phantom->port,
1275 tx.context_id, phantom->port );
1276 NX_FILL_1 ( &cds, 4,
1277 tx.buffer1_dma_addr, virt_to_bus ( iobuf->data ) );
1278 NX_FILL_1 ( &cds, 5,
1279 tx.buffer1_length, iob_len ( iobuf ) );
1280
1281 /* Record I/O buffer */
1282 assert ( phantom->cds_iobuf[index] == NULL );
1283 phantom->cds_iobuf[index] = iobuf;
1284
1285 /* Post descriptor */
1286 phantom_post_cds ( phantom, &cds );
1287
1288 return 0;
1289 }
1290
1291 /**
1292 * Poll for received packets
1293 *
1294 * @v netdev Network device
1295 */
1296 static void phantom_poll ( struct net_device *netdev ) {
1297 struct phantom_nic *phantom = netdev_priv ( netdev );
1298 struct io_buffer *iobuf;
1299 unsigned int irq_vector;
1300 unsigned int irq_state;
1301 unsigned int cds_consumer_idx;
1302 unsigned int raw_new_cds_consumer_idx;
1303 unsigned int new_cds_consumer_idx;
1304 unsigned int rds_consumer_idx;
1305 unsigned int sds_consumer_idx;
1306 struct phantom_sds *sds;
1307 unsigned int sds_handle;
1308 unsigned int sds_opcode;
1309
1310 /* Occasionally poll the link state */
1311 if ( phantom->link_poll_timer-- == 0 ) {
1312 phantom_poll_link_state ( netdev );
1313 /* Reset the link poll timer */
1314 phantom->link_poll_timer = PHN_LINK_POLL_FREQUENCY;
1315 }
1316
1317 /* Check for interrupts */
1318 if ( phantom->sds_irq_enabled ) {
1319
1320 /* Do nothing unless an interrupt is asserted */
1321 irq_vector = phantom_readl ( phantom, UNM_PCIE_IRQ_VECTOR );
1322 if ( ! ( irq_vector & UNM_PCIE_IRQ_VECTOR_BIT( phantom->port )))
1323 return;
1324
1325 /* Do nothing unless interrupt state machine has stabilised */
1326 irq_state = phantom_readl ( phantom, UNM_PCIE_IRQ_STATE );
1327 if ( ! UNM_PCIE_IRQ_STATE_TRIGGERED ( irq_state ) )
1328 return;
1329
1330 /* Acknowledge interrupt */
1331 phantom_writel ( phantom, UNM_PCIE_IRQ_STATUS_MAGIC,
1332 phantom_irq_status_reg[phantom->port] );
1333 phantom_readl ( phantom, UNM_PCIE_IRQ_VECTOR );
1334 }
1335
1336 /* Check for TX completions */
1337 cds_consumer_idx = phantom->cds_consumer_idx;
1338 raw_new_cds_consumer_idx = phantom->desc->cmd_cons;
1339 new_cds_consumer_idx = le32_to_cpu ( raw_new_cds_consumer_idx );
1340 while ( cds_consumer_idx != new_cds_consumer_idx ) {
1341 DBGC2 ( phantom, "Phantom %p CDS %d complete\n",
1342 phantom, cds_consumer_idx );
1343 /* Completions may be for commands other than TX, so
1344 * there may not always be an associated I/O buffer.
1345 */
1346 if ( ( iobuf = phantom->cds_iobuf[cds_consumer_idx] ) ) {
1347 netdev_tx_complete ( netdev, iobuf );
1348 phantom->cds_iobuf[cds_consumer_idx] = NULL;
1349 }
1350 cds_consumer_idx = ( ( cds_consumer_idx + 1 ) % PHN_NUM_CDS );
1351 phantom->cds_consumer_idx = cds_consumer_idx;
1352 }
1353
1354 /* Check for received packets */
1355 rds_consumer_idx = phantom->rds_consumer_idx;
1356 sds_consumer_idx = phantom->sds_consumer_idx;
1357 while ( 1 ) {
1358 sds = &phantom->desc->sds[sds_consumer_idx];
1359 if ( NX_GET ( sds, owner ) == 0 )
1360 break;
1361
1362 DBGC2 ( phantom, "Phantom %p SDS %d status:\n",
1363 phantom, sds_consumer_idx );
1364 DBGC2_HDA ( phantom, virt_to_bus ( sds ), sds, sizeof (*sds) );
1365
1366 /* Check received opcode */
1367 sds_opcode = NX_GET ( sds, opcode );
1368 if ( ( sds_opcode == UNM_RXPKT_DESC ) ||
1369 ( sds_opcode == UNM_SYN_OFFLOAD ) ) {
1370
1371 /* Sanity check: ensure that all of the SDS
1372 * descriptor has been written.
1373 */
1374 if ( NX_GET ( sds, total_length ) == 0 ) {
1375 DBGC ( phantom, "Phantom %p SDS %d "
1376 "incomplete; deferring\n",
1377 phantom, sds_consumer_idx );
1378 /* Leave for next poll() */
1379 break;
1380 }
1381
1382 /* Process received packet */
1383 sds_handle = NX_GET ( sds, handle );
1384 iobuf = phantom->rds_iobuf[sds_handle];
1385 assert ( iobuf != NULL );
1386 iob_put ( iobuf, NX_GET ( sds, total_length ) );
1387 iob_pull ( iobuf, NX_GET ( sds, pkt_offset ) );
1388 DBGC2 ( phantom, "Phantom %p RDS %d complete\n",
1389 phantom, sds_handle );
1390 netdev_rx ( netdev, iobuf );
1391 phantom->rds_iobuf[sds_handle] = NULL;
1392
1393 /* Update RDS consumer counter. This is a
1394 * lower bound for the number of descriptors
1395 * that have been read by the hardware, since
1396 * the hardware must have read at least one
1397 * descriptor for each completion that we
1398 * receive.
1399 */
1400 rds_consumer_idx =
1401 ( ( rds_consumer_idx + 1 ) % PHN_NUM_RDS );
1402 phantom->rds_consumer_idx = rds_consumer_idx;
1403
1404 } else {
1405
1406 DBGC ( phantom, "Phantom %p unexpected SDS opcode "
1407 "%02x\n", phantom, sds_opcode );
1408 DBGC_HDA ( phantom, virt_to_bus ( sds ),
1409 sds, sizeof ( *sds ) );
1410 }
1411
1412 /* Clear status descriptor */
1413 memset ( sds, 0, sizeof ( *sds ) );
1414
1415 /* Update SDS consumer index */
1416 sds_consumer_idx = ( ( sds_consumer_idx + 1 ) % PHN_NUM_SDS );
1417 phantom->sds_consumer_idx = sds_consumer_idx;
1418 wmb();
1419 phantom_writel ( phantom, phantom->sds_consumer_idx,
1420 phantom->sds_consumer_crb );
1421 }
1422
1423 /* Refill the RX descriptor ring */
1424 phantom_refill_rx_ring ( netdev );
1425 }
1426
1427 /**
1428 * Enable/disable interrupts
1429 *
1430 * @v netdev Network device
1431 * @v enable Interrupts should be enabled
1432 */
1433 static void phantom_irq ( struct net_device *netdev, int enable ) {
1434 struct phantom_nic *phantom = netdev_priv ( netdev );
1435
1436 phantom_writel ( phantom, ( enable ? 1 : 0 ),
1437 phantom->sds_irq_mask_crb );
1438 phantom_writel ( phantom, UNM_PCIE_IRQ_MASK_MAGIC,
1439 phantom_irq_mask_reg[phantom->port] );
1440 phantom->sds_irq_enabled = enable;
1441 }
1442
1443 /** Phantom net device operations */
1444 static struct net_device_operations phantom_operations = {
1445 .open = phantom_open,
1446 .close = phantom_close,
1447 .transmit = phantom_transmit,
1448 .poll = phantom_poll,
1449 .irq = phantom_irq,
1450 };
1451
1452 /***************************************************************************
1453 *
1454 * CLP settings
1455 *
1456 */
1457
1458 /** Phantom CLP settings tag magic */
1459 #define PHN_CLP_TAG_MAGIC 0xc19c1900UL
1460
1461 /** Phantom CLP settings tag magic mask */
1462 #define PHN_CLP_TAG_MAGIC_MASK 0xffffff00UL
1463
1464 /** Phantom CLP data
1465 *
1466 */
1467 union phantom_clp_data {
1468 /** Data bytes
1469 *
1470 * This field is right-aligned; if only N bytes are present
1471 * then bytes[0]..bytes[7-N] should be zero, and the data
1472 * should be in bytes[7-N+1] to bytes[7];
1473 */
1474 uint8_t bytes[8];
1475 /** Dwords for the CLP interface */
1476 struct {
1477 /** High dword, in network byte order */
1478 uint32_t hi;
1479 /** Low dword, in network byte order */
1480 uint32_t lo;
1481 } dwords;
1482 };
1483 #define PHN_CLP_BLKSIZE ( sizeof ( union phantom_clp_data ) )
1484
1485 /**
1486 * Wait for Phantom CLP command to complete
1487 *
1488 * @v phantom Phantom NIC
1489 * @ret rc Return status code
1490 */
1491 static int phantom_clp_wait ( struct phantom_nic *phantom ) {
1492 unsigned int retries;
1493 uint32_t status;
1494
1495 for ( retries = 0 ; retries < PHN_CLP_CMD_TIMEOUT_MS ; retries++ ) {
1496 status = phantom_readl ( phantom, UNM_CAM_RAM_CLP_STATUS );
1497 if ( status & UNM_CAM_RAM_CLP_STATUS_DONE )
1498 return 0;
1499 mdelay ( 1 );
1500 }
1501
1502 DBGC ( phantom, "Phantom %p timed out waiting for CLP command\n",
1503 phantom );
1504 return -ETIMEDOUT;
1505 }
1506
1507 /**
1508 * Issue Phantom CLP command
1509 *
1510 * @v phantom Phantom NIC
1511 * @v port Virtual port number
1512 * @v opcode Opcode
1513 * @v data_in Data in, or NULL
1514 * @v data_out Data out, or NULL
1515 * @v offset Offset within data
1516 * @v len Data buffer length
1517 * @ret len Total transfer length (for reads), or negative error
1518 */
1519 static int phantom_clp_cmd ( struct phantom_nic *phantom, unsigned int port,
1520 unsigned int opcode, const void *data_in,
1521 void *data_out, size_t offset, size_t len ) {
1522 union phantom_clp_data data;
1523 unsigned int index = ( offset / sizeof ( data ) );
1524 unsigned int last = 0;
1525 size_t in_frag_len;
1526 uint8_t *in_frag;
1527 uint32_t command;
1528 uint32_t status;
1529 size_t read_len;
1530 unsigned int error;
1531 size_t out_frag_len;
1532 uint8_t *out_frag;
1533 int rc;
1534
1535 /* Sanity checks */
1536 assert ( ( offset % sizeof ( data ) ) == 0 );
1537 if ( len > 255 ) {
1538 DBGC ( phantom, "Phantom %p invalid CLP length %zd\n",
1539 phantom, len );
1540 return -EINVAL;
1541 }
1542
1543 /* Check that CLP interface is ready */
1544 if ( ( rc = phantom_clp_wait ( phantom ) ) != 0 )
1545 return rc;
1546
1547 /* Copy data in */
1548 memset ( &data, 0, sizeof ( data ) );
1549 if ( data_in ) {
1550 assert ( offset < len );
1551 in_frag_len = ( len - offset );
1552 if ( in_frag_len > sizeof ( data ) ) {
1553 in_frag_len = sizeof ( data );
1554 } else {
1555 last = 1;
1556 }
1557 in_frag = &data.bytes[ sizeof ( data ) - in_frag_len ];
1558 memcpy ( in_frag, ( data_in + offset ), in_frag_len );
1559 phantom_writel ( phantom, be32_to_cpu ( data.dwords.lo ),
1560 UNM_CAM_RAM_CLP_DATA_LO );
1561 phantom_writel ( phantom, be32_to_cpu ( data.dwords.hi ),
1562 UNM_CAM_RAM_CLP_DATA_HI );
1563 }
1564
1565 /* Issue CLP command */
1566 command = ( ( index << 24 ) | ( ( data_in ? len : 0 ) << 16 ) |
1567 ( port << 8 ) | ( last << 7 ) | ( opcode << 0 ) );
1568 phantom_writel ( phantom, command, UNM_CAM_RAM_CLP_COMMAND );
1569 mb();
1570 phantom_writel ( phantom, UNM_CAM_RAM_CLP_STATUS_START,
1571 UNM_CAM_RAM_CLP_STATUS );
1572
1573 /* Wait for command to complete */
1574 if ( ( rc = phantom_clp_wait ( phantom ) ) != 0 )
1575 return rc;
1576
1577 /* Get command status */
1578 status = phantom_readl ( phantom, UNM_CAM_RAM_CLP_STATUS );
1579 read_len = ( ( status >> 16 ) & 0xff );
1580 error = ( ( status >> 8 ) & 0xff );
1581 if ( error ) {
1582 DBGC ( phantom, "Phantom %p CLP command error %02x\n",
1583 phantom, error );
1584 return -EIO;
1585 }
1586
1587 /* Copy data out */
1588 if ( data_out ) {
1589 data.dwords.lo = cpu_to_be32 ( phantom_readl ( phantom,
1590 UNM_CAM_RAM_CLP_DATA_LO ) );
1591 data.dwords.hi = cpu_to_be32 ( phantom_readl ( phantom,
1592 UNM_CAM_RAM_CLP_DATA_HI ) );
1593 out_frag_len = ( read_len - offset );
1594 if ( out_frag_len > sizeof ( data ) )
1595 out_frag_len = sizeof ( data );
1596 out_frag = &data.bytes[ sizeof ( data ) - out_frag_len ];
1597 if ( out_frag_len > ( len - offset ) )
1598 out_frag_len = ( len - offset );
1599 memcpy ( ( data_out + offset ), out_frag, out_frag_len );
1600 }
1601
1602 return read_len;
1603 }
1604
1605 /**
1606 * Store Phantom CLP setting
1607 *
1608 * @v phantom Phantom NIC
1609 * @v port Virtual port number
1610 * @v setting Setting number
1611 * @v data Data buffer
1612 * @v len Length of data buffer
1613 * @ret rc Return status code
1614 */
1615 static int phantom_clp_store ( struct phantom_nic *phantom, unsigned int port,
1616 unsigned int setting, const void *data,
1617 size_t len ) {
1618 unsigned int opcode = setting;
1619 size_t offset;
1620 int rc;
1621
1622 for ( offset = 0 ; offset < len ; offset += PHN_CLP_BLKSIZE ) {
1623 if ( ( rc = phantom_clp_cmd ( phantom, port, opcode, data,
1624 NULL, offset, len ) ) < 0 )
1625 return rc;
1626 }
1627 return 0;
1628 }
1629
1630 /**
1631 * Fetch Phantom CLP setting
1632 *
1633 * @v phantom Phantom NIC
1634 * @v port Virtual port number
1635 * @v setting Setting number
1636 * @v data Data buffer
1637 * @v len Length of data buffer
1638 * @ret len Length of setting, or negative error
1639 */
1640 static int phantom_clp_fetch ( struct phantom_nic *phantom, unsigned int port,
1641 unsigned int setting, void *data, size_t len ) {
1642 unsigned int opcode = ( setting + 1 );
1643 size_t offset = 0;
1644 int read_len;
1645
1646 while ( 1 ) {
1647 read_len = phantom_clp_cmd ( phantom, port, opcode, NULL,
1648 data, offset, len );
1649 if ( read_len < 0 )
1650 return read_len;
1651 offset += PHN_CLP_BLKSIZE;
1652 if ( offset >= ( unsigned ) read_len )
1653 break;
1654 if ( offset >= len )
1655 break;
1656 }
1657 return read_len;
1658 }
1659
1660 /** A Phantom CLP setting */
1661 struct phantom_clp_setting {
1662 /** gPXE setting */
1663 struct setting *setting;
1664 /** Setting number */
1665 unsigned int clp_setting;
1666 };
1667
1668 /** Phantom CLP settings */
1669 static struct phantom_clp_setting clp_settings[] = {
1670 { &mac_setting, 0x01 },
1671 };
1672
1673 /**
1674 * Find Phantom CLP setting
1675 *
1676 * @v setting gPXE setting
1677 * @v clp_setting Setting number, or 0 if not found
1678 */
1679 static unsigned int
1680 phantom_clp_setting ( struct phantom_nic *phantom, struct setting *setting ) {
1681 struct phantom_clp_setting *clp_setting;
1682 unsigned int i;
1683
1684 /* Search the list of explicitly-defined settings */
1685 for ( i = 0 ; i < ( sizeof ( clp_settings ) /
1686 sizeof ( clp_settings[0] ) ) ; i++ ) {
1687 clp_setting = &clp_settings[i];
1688 if ( setting_cmp ( setting, clp_setting->setting ) == 0 )
1689 return clp_setting->clp_setting;
1690 }
1691
1692 /* Allow for use of numbered settings */
1693 if ( ( setting->tag & PHN_CLP_TAG_MAGIC_MASK ) == PHN_CLP_TAG_MAGIC )
1694 return ( setting->tag & ~PHN_CLP_TAG_MAGIC_MASK );
1695
1696 DBGC2 ( phantom, "Phantom %p has no \"%s\" setting\n",
1697 phantom, setting->name );
1698
1699 return 0;
1700 }
1701
1702 /**
1703 * Store Phantom CLP setting
1704 *
1705 * @v settings Settings block
1706 * @v setting Setting to store
1707 * @v data Setting data, or NULL to clear setting
1708 * @v len Length of setting data
1709 * @ret rc Return status code
1710 */
1711 static int phantom_store_setting ( struct settings *settings,
1712 struct setting *setting,
1713 const void *data, size_t len ) {
1714 struct phantom_nic *phantom =
1715 container_of ( settings, struct phantom_nic, settings );
1716 unsigned int clp_setting;
1717 int rc;
1718
1719 /* Find Phantom setting equivalent to gPXE setting */
1720 clp_setting = phantom_clp_setting ( phantom, setting );
1721 if ( ! clp_setting )
1722 return -ENOTSUP;
1723
1724 /* Store setting */
1725 if ( ( rc = phantom_clp_store ( phantom, phantom->port,
1726 clp_setting, data, len ) ) != 0 ) {
1727 DBGC ( phantom, "Phantom %p could not store setting \"%s\": "
1728 "%s\n", phantom, setting->name, strerror ( rc ) );
1729 return rc;
1730 }
1731
1732 return 0;
1733 }
1734
1735 /**
1736 * Fetch Phantom CLP setting
1737 *
1738 * @v settings Settings block
1739 * @v setting Setting to fetch
1740 * @v data Buffer to fill with setting data
1741 * @v len Length of buffer
1742 * @ret len Length of setting data, or negative error
1743 */
1744 static int phantom_fetch_setting ( struct settings *settings,
1745 struct setting *setting,
1746 void *data, size_t len ) {
1747 struct phantom_nic *phantom =
1748 container_of ( settings, struct phantom_nic, settings );
1749 unsigned int clp_setting;
1750 int read_len;
1751 int rc;
1752
1753 /* Find Phantom setting equivalent to gPXE setting */
1754 clp_setting = phantom_clp_setting ( phantom, setting );
1755 if ( ! clp_setting )
1756 return -ENOTSUP;
1757
1758 /* Fetch setting */
1759 if ( ( read_len = phantom_clp_fetch ( phantom, phantom->port,
1760 clp_setting, data, len ) ) < 0 ){
1761 rc = read_len;
1762 DBGC ( phantom, "Phantom %p could not fetch setting \"%s\": "
1763 "%s\n", phantom, setting->name, strerror ( rc ) );
1764 return rc;
1765 }
1766
1767 return read_len;
1768 }
1769
1770 /** Phantom CLP settings operations */
1771 static struct settings_operations phantom_settings_operations = {
1772 .store = phantom_store_setting,
1773 .fetch = phantom_fetch_setting,
1774 };
1775
1776 /***************************************************************************
1777 *
1778 * Initialisation
1779 *
1780 */
1781
1782 /**
1783 * Map Phantom CRB window
1784 *
1785 * @v phantom Phantom NIC
1786 * @ret rc Return status code
1787 */
1788 static int phantom_map_crb ( struct phantom_nic *phantom,
1789 struct pci_device *pci ) {
1790 unsigned long bar0_start;
1791 unsigned long bar0_size;
1792
1793 bar0_start = pci_bar_start ( pci, PCI_BASE_ADDRESS_0 );
1794 bar0_size = pci_bar_size ( pci, PCI_BASE_ADDRESS_0 );
1795 DBGC ( phantom, "Phantom %p is PCI %02x:%02x.%x with BAR0 at "
1796 "%08lx+%lx\n", phantom, pci->bus, PCI_SLOT ( pci->devfn ),
1797 PCI_FUNC ( pci->devfn ), bar0_start, bar0_size );
1798
1799 if ( ! bar0_start ) {
1800 DBGC ( phantom, "Phantom %p BAR not assigned; ignoring\n",
1801 phantom );
1802 return -EINVAL;
1803 }
1804
1805 switch ( bar0_size ) {
1806 case ( 128 * 1024 * 1024 ) :
1807 DBGC ( phantom, "Phantom %p has 128MB BAR\n", phantom );
1808 phantom->crb_access = phantom_crb_access_128m;
1809 break;
1810 case ( 32 * 1024 * 1024 ) :
1811 DBGC ( phantom, "Phantom %p has 32MB BAR\n", phantom );
1812 phantom->crb_access = phantom_crb_access_32m;
1813 break;
1814 case ( 2 * 1024 * 1024 ) :
1815 DBGC ( phantom, "Phantom %p has 2MB BAR\n", phantom );
1816 phantom->crb_access = phantom_crb_access_2m;
1817 break;
1818 default:
1819 DBGC ( phantom, "Phantom %p has bad BAR size\n", phantom );
1820 return -EINVAL;
1821 }
1822
1823 phantom->bar0 = ioremap ( bar0_start, bar0_size );
1824 if ( ! phantom->bar0 ) {
1825 DBGC ( phantom, "Phantom %p could not map BAR0\n", phantom );
1826 return -EIO;
1827 }
1828
1829 /* Mark current CRB window as invalid, so that the first
1830 * read/write will set the current window.
1831 */
1832 phantom->crb_window = -1UL;
1833
1834 return 0;
1835 }
1836
1837 /**
1838 * Unhalt all PEGs
1839 *
1840 * @v phantom Phantom NIC
1841 */
1842 static void phantom_unhalt_pegs ( struct phantom_nic *phantom ) {
1843 uint32_t halt_status;
1844
1845 halt_status = phantom_readl ( phantom, UNM_PEG_0_HALT_STATUS );
1846 phantom_writel ( phantom, halt_status, UNM_PEG_0_HALT_STATUS );
1847 halt_status = phantom_readl ( phantom, UNM_PEG_1_HALT_STATUS );
1848 phantom_writel ( phantom, halt_status, UNM_PEG_1_HALT_STATUS );
1849 halt_status = phantom_readl ( phantom, UNM_PEG_2_HALT_STATUS );
1850 phantom_writel ( phantom, halt_status, UNM_PEG_2_HALT_STATUS );
1851 halt_status = phantom_readl ( phantom, UNM_PEG_3_HALT_STATUS );
1852 phantom_writel ( phantom, halt_status, UNM_PEG_3_HALT_STATUS );
1853 halt_status = phantom_readl ( phantom, UNM_PEG_4_HALT_STATUS );
1854 phantom_writel ( phantom, halt_status, UNM_PEG_4_HALT_STATUS );
1855 }
1856
1857 /**
1858 * Initialise the Phantom command PEG
1859 *
1860 * @v phantom Phantom NIC
1861 * @ret rc Return status code
1862 */
1863 static int phantom_init_cmdpeg ( struct phantom_nic *phantom ) {
1864 uint32_t cold_boot;
1865 uint32_t sw_reset;
1866 unsigned int retries;
1867 uint32_t cmdpeg_state;
1868 uint32_t last_cmdpeg_state = 0;
1869
1870 /* Check for a previous initialisation. This could have
1871 * happened if, for example, the BIOS used the UNDI API to
1872 * drive the NIC prior to a full PXE boot.
1873 */
1874 cmdpeg_state = phantom_readl ( phantom, UNM_NIC_REG_CMDPEG_STATE );
1875 if ( cmdpeg_state == UNM_NIC_REG_CMDPEG_STATE_INITIALIZE_ACK ) {
1876 DBGC ( phantom, "Phantom %p command PEG already initialized\n",
1877 phantom );
1878 /* Unhalt the PEGs. Previous firmware (e.g. BOFM) may
1879 * have halted the PEGs to prevent internal bus
1880 * collisions when the BIOS re-reads the expansion ROM.
1881 */
1882 phantom_unhalt_pegs ( phantom );
1883 return 0;
1884 }
1885
1886 /* If this was a cold boot, check that the hardware came up ok */
1887 cold_boot = phantom_readl ( phantom, UNM_CAM_RAM_COLD_BOOT );
1888 if ( cold_boot == UNM_CAM_RAM_COLD_BOOT_MAGIC ) {
1889 DBGC ( phantom, "Phantom %p coming up from cold boot\n",
1890 phantom );
1891 sw_reset = phantom_readl ( phantom, UNM_ROMUSB_GLB_SW_RESET );
1892 if ( sw_reset != UNM_ROMUSB_GLB_SW_RESET_MAGIC ) {
1893 DBGC ( phantom, "Phantom %p reset failed: %08x\n",
1894 phantom, sw_reset );
1895 return -EIO;
1896 }
1897 } else {
1898 DBGC ( phantom, "Phantom %p coming up from warm boot "
1899 "(%08x)\n", phantom, cold_boot );
1900 }
1901 /* Clear cold-boot flag */
1902 phantom_writel ( phantom, 0, UNM_CAM_RAM_COLD_BOOT );
1903
1904 /* Set port modes */
1905 phantom_writel ( phantom, UNM_CAM_RAM_PORT_MODE_AUTO_NEG_1G,
1906 UNM_CAM_RAM_WOL_PORT_MODE );
1907
1908 /* Pass dummy DMA area to card */
1909 phantom_write_hilo ( phantom, 0,
1910 UNM_NIC_REG_DUMMY_BUF_ADDR_LO,
1911 UNM_NIC_REG_DUMMY_BUF_ADDR_HI );
1912 phantom_writel ( phantom, UNM_NIC_REG_DUMMY_BUF_INIT,
1913 UNM_NIC_REG_DUMMY_BUF );
1914
1915 /* Tell the hardware that tuning is complete */
1916 phantom_writel ( phantom, UNM_ROMUSB_GLB_PEGTUNE_DONE_MAGIC,
1917 UNM_ROMUSB_GLB_PEGTUNE_DONE );
1918
1919 /* Wait for command PEG to finish initialising */
1920 DBGC ( phantom, "Phantom %p initialising command PEG (will take up to "
1921 "%d seconds)...\n", phantom, PHN_CMDPEG_INIT_TIMEOUT_SEC );
1922 for ( retries = 0; retries < PHN_CMDPEG_INIT_TIMEOUT_SEC; retries++ ) {
1923 cmdpeg_state = phantom_readl ( phantom,
1924 UNM_NIC_REG_CMDPEG_STATE );
1925 if ( cmdpeg_state != last_cmdpeg_state ) {
1926 DBGC ( phantom, "Phantom %p command PEG state is "
1927 "%08x after %d seconds...\n",
1928 phantom, cmdpeg_state, retries );
1929 last_cmdpeg_state = cmdpeg_state;
1930 }
1931 if ( cmdpeg_state == UNM_NIC_REG_CMDPEG_STATE_INITIALIZED ) {
1932 /* Acknowledge the PEG initialisation */
1933 phantom_writel ( phantom,
1934 UNM_NIC_REG_CMDPEG_STATE_INITIALIZE_ACK,
1935 UNM_NIC_REG_CMDPEG_STATE );
1936 return 0;
1937 }
1938 mdelay ( 1000 );
1939 }
1940
1941 DBGC ( phantom, "Phantom %p timed out waiting for command PEG to "
1942 "initialise (status %08x)\n", phantom, cmdpeg_state );
1943 return -ETIMEDOUT;
1944 }
1945
1946 /**
1947 * Read Phantom MAC address
1948 *
1949 * @v phanton_port Phantom NIC
1950 * @v hw_addr Buffer to fill with MAC address
1951 */
1952 static void phantom_get_macaddr ( struct phantom_nic *phantom,
1953 uint8_t *hw_addr ) {
1954 union {
1955 uint8_t mac_addr[2][ETH_ALEN];
1956 uint32_t dwords[3];
1957 } u;
1958 unsigned long offset;
1959 int i;
1960
1961 /* Read the three dwords that include this MAC address and one other */
1962 offset = ( UNM_CAM_RAM_MAC_ADDRS +
1963 ( 12 * ( phantom->port / 2 ) ) );
1964 for ( i = 0 ; i < 3 ; i++, offset += 4 ) {
1965 u.dwords[i] = phantom_readl ( phantom, offset );
1966 }
1967
1968 /* Copy out the relevant MAC address */
1969 for ( i = 0 ; i < ETH_ALEN ; i++ ) {
1970 hw_addr[ ETH_ALEN - i - 1 ] =
1971 u.mac_addr[ phantom->port & 1 ][i];
1972 }
1973 DBGC ( phantom, "Phantom %p MAC address is %s\n",
1974 phantom, eth_ntoa ( hw_addr ) );
1975 }
1976
1977 /**
1978 * Check Phantom is enabled for boot
1979 *
1980 * @v phanton_port Phantom NIC
1981 * @ret rc Return status code
1982 *
1983 * This is something of an ugly hack to accommodate an OEM
1984 * requirement. The NIC has only one expansion ROM BAR, rather than
1985 * one per port. To allow individual ports to be selectively
1986 * enabled/disabled for PXE boot (as required), we must therefore
1987 * leave the expansion ROM always enabled, and place the per-port
1988 * enable/disable logic within the gPXE driver.
1989 */
1990 static int phantom_check_boot_enable ( struct phantom_nic *phantom ) {
1991 unsigned long boot_enable;
1992
1993 boot_enable = phantom_readl ( phantom, UNM_CAM_RAM_BOOT_ENABLE );
1994 if ( ! ( boot_enable & ( 1 << phantom->port ) ) ) {
1995 DBGC ( phantom, "Phantom %p PXE boot is disabled\n",
1996 phantom );
1997 return -ENOTSUP;
1998 }
1999
2000 return 0;
2001 }
2002
2003 /**
2004 * Initialise Phantom receive PEG
2005 *
2006 * @v phantom Phantom NIC
2007 * @ret rc Return status code
2008 */
2009 static int phantom_init_rcvpeg ( struct phantom_nic *phantom ) {
2010 unsigned int retries;
2011 uint32_t rcvpeg_state;
2012 uint32_t last_rcvpeg_state = 0;
2013
2014 DBGC ( phantom, "Phantom %p initialising receive PEG (will take up to "
2015 "%d seconds)...\n", phantom, PHN_RCVPEG_INIT_TIMEOUT_SEC );
2016 for ( retries = 0; retries < PHN_RCVPEG_INIT_TIMEOUT_SEC; retries++ ) {
2017 rcvpeg_state = phantom_readl ( phantom,
2018 UNM_NIC_REG_RCVPEG_STATE );
2019 if ( rcvpeg_state != last_rcvpeg_state ) {
2020 DBGC ( phantom, "Phantom %p receive PEG state is "
2021 "%08x after %d seconds...\n",
2022 phantom, rcvpeg_state, retries );
2023 last_rcvpeg_state = rcvpeg_state;
2024 }
2025 if ( rcvpeg_state == UNM_NIC_REG_RCVPEG_STATE_INITIALIZED )
2026 return 0;
2027 mdelay ( 1000 );
2028 }
2029
2030 DBGC ( phantom, "Phantom %p timed out waiting for receive PEG to "
2031 "initialise (status %08x)\n", phantom, rcvpeg_state );
2032 return -ETIMEDOUT;
2033 }
2034
2035 /**
2036 * Probe PCI device
2037 *
2038 * @v pci PCI device
2039 * @v id PCI ID
2040 * @ret rc Return status code
2041 */
2042 static int phantom_probe ( struct pci_device *pci,
2043 const struct pci_device_id *id __unused ) {
2044 struct net_device *netdev;
2045 struct phantom_nic *phantom;
2046 struct settings *parent_settings;
2047 int rc;
2048
2049 /* Allocate Phantom device */
2050 netdev = alloc_etherdev ( sizeof ( *phantom ) );
2051 if ( ! netdev ) {
2052 rc = -ENOMEM;
2053 goto err_alloc_etherdev;
2054 }
2055 netdev_init ( netdev, &phantom_operations );
2056 phantom = netdev_priv ( netdev );
2057 pci_set_drvdata ( pci, netdev );
2058 netdev->dev = &pci->dev;
2059 memset ( phantom, 0, sizeof ( *phantom ) );
2060 phantom->port = PCI_FUNC ( pci->devfn );
2061 assert ( phantom->port < PHN_MAX_NUM_PORTS );
2062 settings_init ( &phantom->settings,
2063 &phantom_settings_operations,
2064 &netdev->refcnt, "clp", PHN_CLP_TAG_MAGIC );
2065
2066 /* Fix up PCI device */
2067 adjust_pci_device ( pci );
2068
2069 /* Map CRB */
2070 if ( ( rc = phantom_map_crb ( phantom, pci ) ) != 0 )
2071 goto err_map_crb;
2072
2073 /* BUG5945 - need to hack PCI config space on P3 B1 silicon.
2074 * B2 will have this fixed; remove this hack when B1 is no
2075 * longer in use.
2076 */
2077 if ( PCI_FUNC ( pci->devfn ) == 0 ) {
2078 unsigned int i;
2079 for ( i = 0 ; i < 8 ; i++ ) {
2080 uint32_t temp;
2081 pci->devfn = PCI_DEVFN ( PCI_SLOT ( pci->devfn ), i );
2082 pci_read_config_dword ( pci, 0xc8, &temp );
2083 pci_read_config_dword ( pci, 0xc8, &temp );
2084 pci_write_config_dword ( pci, 0xc8, 0xf1000 );
2085 }
2086 pci->devfn = PCI_DEVFN ( PCI_SLOT ( pci->devfn ), 0 );
2087 }
2088
2089 /* Initialise the command PEG */
2090 if ( ( rc = phantom_init_cmdpeg ( phantom ) ) != 0 )
2091 goto err_init_cmdpeg;
2092
2093 /* Initialise the receive PEG */
2094 if ( ( rc = phantom_init_rcvpeg ( phantom ) ) != 0 )
2095 goto err_init_rcvpeg;
2096
2097 /* Read MAC addresses */
2098 phantom_get_macaddr ( phantom, netdev->hw_addr );
2099
2100 /* Skip if boot disabled on NIC */
2101 if ( ( rc = phantom_check_boot_enable ( phantom ) ) != 0 )
2102 goto err_check_boot_enable;
2103
2104 /* Register network devices */
2105 if ( ( rc = register_netdev ( netdev ) ) != 0 ) {
2106 DBGC ( phantom, "Phantom %p could not register net device: "
2107 "%s\n", phantom, strerror ( rc ) );
2108 goto err_register_netdev;
2109 }
2110
2111 /* Register settings blocks */
2112 parent_settings = netdev_settings ( netdev );
2113 if ( ( rc = register_settings ( &phantom->settings,
2114 parent_settings ) ) != 0 ) {
2115 DBGC ( phantom, "Phantom %p could not register settings: "
2116 "%s\n", phantom, strerror ( rc ) );
2117 goto err_register_settings;
2118 }
2119
2120 return 0;
2121
2122 unregister_settings ( &phantom->settings );
2123 err_register_settings:
2124 unregister_netdev ( netdev );
2125 err_register_netdev:
2126 err_check_boot_enable:
2127 err_init_rcvpeg:
2128 err_init_cmdpeg:
2129 err_map_crb:
2130 netdev_nullify ( netdev );
2131 netdev_put ( netdev );
2132 err_alloc_etherdev:
2133 return rc;
2134 }
2135
2136 /**
2137 * Remove PCI device
2138 *
2139 * @v pci PCI device
2140 */
2141 static void phantom_remove ( struct pci_device *pci ) {
2142 struct net_device *netdev = pci_get_drvdata ( pci );
2143 struct phantom_nic *phantom = netdev_priv ( netdev );
2144
2145 unregister_settings ( &phantom->settings );
2146 unregister_netdev ( netdev );
2147 netdev_nullify ( netdev );
2148 netdev_put ( netdev );
2149 }
2150
2151 /** Phantom PCI IDs */
2152 static struct pci_device_id phantom_nics[] = {
2153 PCI_ROM ( 0x4040, 0x0100, "nx", "NX", 0 ),
2154 };
2155
2156 /** Phantom PCI driver */
2157 struct pci_driver phantom_driver __pci_driver = {
2158 .ids = phantom_nics,
2159 .id_count = ( sizeof ( phantom_nics ) / sizeof ( phantom_nics[0] ) ),
2160 .probe = phantom_probe,
2161 .remove = phantom_remove,
2162 };
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