src/drivers/net/epic100.c

   1
   2 /* epic100.c: A SMC 83c170 EPIC/100 fast ethernet driver for Etherboot */
   3
   4 /* 05/06/2003   timlegge        Fixed relocation and implemented Multicast */
   5 #define LINUX_OUT_MACROS
   6
   7 #include "etherboot.h"
   8 #include <gpxe/pci.h>
   9 #include <gpxe/ethernet.h>
  10 #include "nic.h"
  11 #include "timer.h"
  12 #include "console.h"
  13 #include "epic100.h"
  14
  15 /* Condensed operations for readability */
  16 #define virt_to_le32desc(addr)  cpu_to_le32(virt_to_bus(addr))
  17 #define le32desc_to_virt(addr)  bus_to_virt(le32_to_cpu(addr))
  18
  19 #define TX_RING_SIZE    2       /* use at least 2 buffers for TX */
  20 #define RX_RING_SIZE    2
  21
  22 #define PKT_BUF_SZ      1536    /* Size of each temporary Tx/Rx buffer.*/
  23
  24 /*
  25 #define DEBUG_RX
  26 #define DEBUG_TX
  27 #define DEBUG_EEPROM
  28 */
  29
  30 #define EPIC_DEBUG 0    /* debug level */
  31
  32 /* The EPIC100 Rx and Tx buffer descriptors. */
  33 struct epic_rx_desc {
  34     unsigned long status;
  35     unsigned long bufaddr;
  36     unsigned long buflength;
  37     unsigned long next;
  38 };
  39 /* description of the tx descriptors control bits commonly used */
  40 #define TD_STDFLAGS     TD_LASTDESC
  41
  42 struct epic_tx_desc {
  43     unsigned long status;
  44     unsigned long bufaddr;
  45     unsigned long buflength;
  46     unsigned long  next;
  47 };
  48
  49 #define delay(nanosec)   do { int _i = 3; while (--_i > 0) \
  50                                      { __SLOW_DOWN_IO; }} while (0)
  51
  52 static void     epic100_open(void);
  53 static void     epic100_init_ring(void);
  54 static void     epic100_disable(struct nic *nic);
  55 static int      epic100_poll(struct nic *nic, int retrieve);
  56 static void     epic100_transmit(struct nic *nic, const char *destaddr,
  57                                  unsigned int type, unsigned int len, const char *data);
  58 #ifdef  DEBUG_EEPROM
  59 static int      read_eeprom(int location);
  60 #endif
  61 static int      mii_read(int phy_id, int location);
  62 static void     epic100_irq(struct nic *nic, irq_action_t action);
  63
  64 static struct nic_operations epic100_operations;
  65
  66 static int      ioaddr;
  67
  68 static int      command;
  69 static int      intstat;
  70 static int      intmask;
  71 static int      genctl ;
  72 static int      eectl  ;
  73 static int      test   ;
  74 static int      mmctl  ;
  75 static int      mmdata ;
  76 static int      lan0   ;
  77 static int      mc0    ;
  78 static int      rxcon  ;
  79 static int      txcon  ;
  80 static int      prcdar ;
  81 static int      ptcdar ;
  82 static int      eththr ;
  83
  84 static unsigned int     cur_rx, cur_tx;         /* The next free ring entry */
  85 #ifdef  DEBUG_EEPROM
  86 static unsigned short   eeprom[64];
  87 #endif
  88 static signed char      phys[4];                /* MII device addresses. */
  89 struct {
  90         struct epic_rx_desc     rx_ring[RX_RING_SIZE]
  91         __attribute__ ((aligned(4)));
  92         struct epic_tx_desc     tx_ring[TX_RING_SIZE]
  93         __attribute__ ((aligned(4)));
  94         unsigned char           rx_packet[PKT_BUF_SZ * RX_RING_SIZE];
  95         unsigned char           tx_packet[PKT_BUF_SZ * TX_RING_SIZE];
  96 } epic100_bufs __shared;
  97 #define rx_ring epic100_bufs.rx_ring
  98 #define tx_ring epic100_bufs.tx_ring
  99 #define rx_packet epic100_bufs.rx_packet
 100 #define tx_packet epic100_bufs.tx_packet
 101
 102 /***********************************************************************/
 103 /*                    Externally visible functions                     */
 104 /***********************************************************************/
 105
 106
 107 static int
 108 epic100_probe ( struct nic *nic, struct pci_device *pci ) {
 109
 110     int i;
 111     unsigned short* ap;
 112     unsigned int phy, phy_idx;
 113
 114     if (pci->ioaddr == 0)
 115         return 0;
 116
 117     /* Ideally we would detect all network cards in slot order.  That would
 118        be best done a central PCI probe dispatch, which wouldn't work
 119        well with the current structure.  So instead we detect just the
 120        Epic cards in slot order. */
 121
 122     ioaddr = pci->ioaddr;
 123     nic->irqno  = 0;
 124     pci_fill_nic ( nic, pci );
 125     nic->ioaddr = pci->ioaddr & ~3;
 126
 127     /* compute all used static epic100 registers address */
 128     command = ioaddr + COMMAND;         /* Control Register */
 129     intstat = ioaddr + INTSTAT;         /* Interrupt Status */
 130     intmask = ioaddr + INTMASK;         /* Interrupt Mask */
 131     genctl  = ioaddr + GENCTL;          /* General Control */
 132     eectl   = ioaddr + EECTL;           /* EEPROM Control  */
 133     test    = ioaddr + TEST;            /* Test register (clocks) */
 134     mmctl   = ioaddr + MMCTL;           /* MII Management Interface Control */
 135     mmdata  = ioaddr + MMDATA;          /* MII Management Interface Data */
 136     lan0    = ioaddr + LAN0;            /* MAC address. (0x40-0x48) */
 137     mc0     = ioaddr + MC0;             /* Multicast Control */
 138     rxcon   = ioaddr + RXCON;           /* Receive Control */
 139     txcon   = ioaddr + TXCON;           /* Transmit Control */
 140     prcdar  = ioaddr + PRCDAR;          /* PCI Receive Current Descr Address */
 141     ptcdar  = ioaddr + PTCDAR;          /* PCI Transmit Current Descr Address */
 142     eththr  = ioaddr + ETHTHR;          /* Early Transmit Threshold */
 143
 144     /* Reset the chip & bring it out of low-power mode. */
 145     outl(GC_SOFT_RESET, genctl);
 146
 147     /* Disable ALL interrupts by setting the interrupt mask. */
 148     outl(INTR_DISABLE, intmask);
 149
 150     /*
 151      * set the internal clocks:
 152      * Application Note 7.15 says:
 153      *    In order to set the CLOCK TEST bit in the TEST register,
 154      *    perform the following:
 155      *
 156      *        Write 0x0008 to the test register at least sixteen
 157      *        consecutive times.
 158      *
 159      * The CLOCK TEST bit is Write-Only. Writing it several times
 160      * consecutively insures a successful write to the bit...
 161      */
 162
 163     for (i = 0; i < 16; i++) {
 164         outl(0x00000008, test);
 165     }
 166
 167 #ifdef  DEBUG_EEPROM
 168 {
 169     unsigned short sum = 0;
 170     unsigned short value;
 171     for (i = 0; i < 64; i++) {
 172         value = read_eeprom(i);
 173         eeprom[i] = value;
 174         sum += value;
 175     }
 176 }
 177
 178 #if     (EPIC_DEBUG > 1)
 179     printf("EEPROM contents\n");
 180     for (i = 0; i < 64; i++) {
 181         printf(" %hhX%s", eeprom[i], i % 16 == 15 ? "\n" : "");
 182     }
 183 #endif
 184 #endif
 185
 186     /* This could also be read from the EEPROM. */
 187     ap = (unsigned short*)nic->node_addr;
 188     for (i = 0; i < 3; i++)
 189         *ap++ = inw(lan0 + i*4);
 190
 191     DBG ( " I/O %4.4x %s ", ioaddr, eth_ntoa ( nic->node_addr ) );
 192
 193     /* Find the connected MII xcvrs. */
 194     for (phy = 0, phy_idx = 0; phy < 32 && phy_idx < sizeof(phys); phy++) {
 195         int mii_status = mii_read(phy, 0);
 196
 197         if (mii_status != 0xffff  && mii_status != 0x0000) {
 198             phys[phy_idx++] = phy;
 199 #if     (EPIC_DEBUG > 1)
 200             printf("MII transceiver found at address %d.\n", phy);
 201 #endif
 202         }
 203     }
 204     if (phy_idx == 0) {
 205 #if     (EPIC_DEBUG > 1)
 206         printf("***WARNING***: No MII transceiver found!\n");
 207 #endif
 208         /* Use the known PHY address of the EPII. */
 209         phys[0] = 3;
 210     }
 211
 212     epic100_open();
 213     nic->nic_op = &epic100_operations;
 214
 215     return 1;
 216 }
 217
 218 static void set_rx_mode(void)
 219 {
 220         unsigned char mc_filter[8];
 221         int i;
 222         memset(mc_filter, 0xff, sizeof(mc_filter));
 223         outl(0x0C, rxcon);
 224         for(i = 0; i < 4; i++)
 225                 outw(((unsigned short *)mc_filter)[i], mc0 + i*4);
 226         return;
 227 }
 228
 229    static void
 230 epic100_open(void)
 231 {
 232     int mii_reg5;
 233     int full_duplex = 0;
 234     unsigned long tmp;
 235
 236     epic100_init_ring();
 237
 238     /* Pull the chip out of low-power mode, and set for PCI read multiple. */
 239     outl(GC_RX_FIFO_THR_64 | GC_MRC_READ_MULT | GC_ONE_COPY, genctl);
 240
 241     outl(TX_FIFO_THRESH, eththr);
 242
 243     tmp = TC_EARLY_TX_ENABLE | TX_SLOT_TIME;
 244
 245     mii_reg5 = mii_read(phys[0], 5);
 246     if (mii_reg5 != 0xffff && (mii_reg5 & 0x0100)) {
 247         full_duplex = 1;
 248         printf(" full-duplex mode");
 249         tmp |= TC_LM_FULL_DPX;
 250     } else
 251         tmp |= TC_LM_NORMAL;
 252
 253     outl(tmp, txcon);
 254
 255     /* Give adress of RX and TX ring to the chip */
 256     outl(virt_to_le32desc(&rx_ring), prcdar);
 257     outl(virt_to_le32desc(&tx_ring), ptcdar);
 258
 259     /* Start the chip's Rx process: receive unicast and broadcast */
 260     set_rx_mode();
 261     outl(CR_START_RX | CR_QUEUE_RX, command);
 262
 263     putchar('\n');
 264 }
 265
 266 /* Initialize the Rx and Tx rings. */
 267     static void
 268 epic100_init_ring(void)
 269 {
 270     int i;
 271
 272     cur_rx = cur_tx = 0;
 273
 274     for (i = 0; i < RX_RING_SIZE; i++) {
 275         rx_ring[i].status    = cpu_to_le32(RRING_OWN);  /* Owned by Epic chip */
 276         rx_ring[i].buflength = cpu_to_le32(PKT_BUF_SZ);
 277         rx_ring[i].bufaddr   = virt_to_bus(&rx_packet[i * PKT_BUF_SZ]);
 278         rx_ring[i].next      = virt_to_le32desc(&rx_ring[i + 1]) ;
 279     }
 280     /* Mark the last entry as wrapping the ring. */
 281     rx_ring[i-1].next = virt_to_le32desc(&rx_ring[0]);
 282
 283     /*
 284      *The Tx buffer descriptor is filled in as needed,
 285      * but we do need to clear the ownership bit.
 286      */
 287
 288     for (i = 0; i < TX_RING_SIZE; i++) {
 289         tx_ring[i].status  = 0x0000;                    /* Owned by CPU */
 290         tx_ring[i].buflength = 0x0000 | cpu_to_le32(TD_STDFLAGS << 16);
 291         tx_ring[i].bufaddr = virt_to_bus(&tx_packet[i * PKT_BUF_SZ]);
 292         tx_ring[i].next    = virt_to_le32desc(&tx_ring[i + 1]);
 293     }
 294         tx_ring[i-1].next    = virt_to_le32desc(&tx_ring[0]);
 295 }
 296
 297 /* function: epic100_transmit
 298  * This transmits a packet.
 299  *
 300  * Arguments: char d[6]:          destination ethernet address.
 301  *            unsigned short t:   ethernet protocol type.
 302  *            unsigned short s:   size of the data-part of the packet.
 303  *            char *p:            the data for the packet.
 304  * returns:   void.
 305  */
 306     static void
 307 epic100_transmit(struct nic *nic, const char *destaddr, unsigned int type,
 308                  unsigned int len, const char *data)
 309 {
 310     unsigned short nstype;
 311     unsigned char *txp;
 312     int entry;
 313
 314     /* Calculate the next Tx descriptor entry. */
 315     entry = cur_tx % TX_RING_SIZE;
 316
 317     if ((tx_ring[entry].status & TRING_OWN) == TRING_OWN) {
 318         printf("eth_transmit: Unable to transmit. status=%4.4lx. Resetting...\n",
 319                tx_ring[entry].status);
 320
 321         epic100_open();
 322         return;
 323     }
 324
 325     txp = tx_packet + (entry * PKT_BUF_SZ);
 326
 327     memcpy(txp, destaddr, ETH_ALEN);
 328     memcpy(txp + ETH_ALEN, nic->node_addr, ETH_ALEN);
 329     nstype = htons(type);
 330     memcpy(txp + 12, (char*)&nstype, 2);
 331     memcpy(txp + ETH_HLEN, data, len);
 332
 333     len += ETH_HLEN;
 334         len &= 0x0FFF;
 335         while(len < ETH_ZLEN)
 336                 txp[len++] = '\0';
 337     /*
 338      * Caution: the write order is important here,
 339      * set the base address with the "ownership"
 340      * bits last.
 341      */
 342
 343     tx_ring[entry].buflength |= cpu_to_le32(len);
 344     tx_ring[entry].status = cpu_to_le32(len << 16) |
 345             cpu_to_le32(TRING_OWN);     /* Pass ownership to the chip. */
 346
 347     cur_tx++;
 348
 349     /* Trigger an immediate transmit demand. */
 350     outl(CR_QUEUE_TX, command);
 351
 352     load_timer2(10*TICKS_PER_MS);         /* timeout 10 ms for transmit */
 353     while ((le32_to_cpu(tx_ring[entry].status) & (TRING_OWN)) && timer2_running())
 354         /* Wait */;
 355
 356     if ((le32_to_cpu(tx_ring[entry].status) & TRING_OWN) != 0)
 357         printf("Oops, transmitter timeout, status=%4.4lX\n",
 358             tx_ring[entry].status);
 359 }
 360
 361 /* function: epic100_poll / eth_poll
 362  * This receives a packet from the network.
 363  *
 364  * Arguments: none
 365  *
 366  * returns:   1 if a packet was received.
 367  *            0 if no pacet was received.
 368  * side effects:
 369  *            returns the packet in the array nic->packet.
 370  *            returns the length of the packet in nic->packetlen.
 371  */
 372
 373     static int
 374 epic100_poll(struct nic *nic, int retrieve)
 375 {
 376     int entry;
 377     int retcode;
 378     int status;
 379     entry = cur_rx % RX_RING_SIZE;
 380
 381     if ((rx_ring[entry].status & cpu_to_le32(RRING_OWN)) == RRING_OWN)
 382         return (0);
 383
 384     if ( ! retrieve ) return 1;
 385
 386     status = le32_to_cpu(rx_ring[entry].status);
 387     /* We own the next entry, it's a new packet. Send it up. */
 388
 389 #if     (EPIC_DEBUG > 4)
 390     printf("epic_poll: entry %d status %hX\n", entry, status);
 391 #endif
 392
 393     cur_rx++;
 394     if (status & 0x2000) {
 395         printf("epic_poll: Giant packet\n");
 396         retcode = 0;
 397     } else if (status & 0x0006) {
 398         /* Rx Frame errors are counted in hardware. */
 399         printf("epic_poll: Frame received with errors\n");
 400         retcode = 0;
 401     } else {
 402         /* Omit the four octet CRC from the length. */
 403         nic->packetlen = le32_to_cpu((rx_ring[entry].buflength))- 4;
 404         memcpy(nic->packet, &rx_packet[entry * PKT_BUF_SZ], nic->packetlen);
 405         retcode = 1;
 406     }
 407
 408     /* Clear all error sources. */
 409     outl(status & INTR_CLEARERRS, intstat);
 410
 411     /* Give the descriptor back to the chip */
 412     rx_ring[entry].status = RRING_OWN;
 413
 414     /* Restart Receiver */
 415     outl(CR_START_RX | CR_QUEUE_RX, command);
 416
 417     return retcode;
 418 }
 419
 420
 421 static void epic100_disable ( struct nic *nic __unused ) {
 422         /* Soft reset the chip. */
 423         outl(GC_SOFT_RESET, genctl);
 424 }
 425
 426 static void epic100_irq(struct nic *nic __unused, irq_action_t action __unused)
 427 {
 428   switch ( action ) {
 429   case DISABLE :
 430     break;
 431   case ENABLE :
 432     break;
 433   case FORCE :
 434     break;
 435   }
 436 }
 437
 438 #ifdef  DEBUG_EEPROM
 439 /* Serial EEPROM section. */
 440
 441 /*  EEPROM_Ctrl bits. */
 442 #define EE_SHIFT_CLK    0x04    /* EEPROM shift clock. */
 443 #define EE_CS           0x02    /* EEPROM chip select. */
 444 #define EE_DATA_WRITE   0x08    /* EEPROM chip data in. */
 445 #define EE_WRITE_0      0x01
 446 #define EE_WRITE_1      0x09
 447 #define EE_DATA_READ    0x10    /* EEPROM chip data out. */
 448 #define EE_ENB          (0x0001 | EE_CS)
 449
 450 /* The EEPROM commands include the alway-set leading bit. */
 451 #define EE_WRITE_CMD    (5 << 6)
 452 #define EE_READ_CMD     (6 << 6)
 453 #define EE_ERASE_CMD    (7 << 6)
 454
 455 #define eeprom_delay(n) delay(n)
 456
 457     static int
 458 read_eeprom(int location)
 459 {
 460     int i;
 461     int retval = 0;
 462     int read_cmd = location | EE_READ_CMD;
 463
 464     outl(EE_ENB & ~EE_CS, eectl);
 465     outl(EE_ENB, eectl);
 466
 467     /* Shift the read command bits out. */
 468     for (i = 10; i >= 0; i--) {
 469         short dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
 470         outl(EE_ENB | dataval, eectl);
 471         eeprom_delay(100);
 472         outl(EE_ENB | dataval | EE_SHIFT_CLK, eectl);
 473         eeprom_delay(150);
 474         outl(EE_ENB | dataval, eectl);  /* Finish EEPROM a clock tick. */
 475         eeprom_delay(250);
 476     }
 477     outl(EE_ENB, eectl);
 478
 479     for (i = 16; i > 0; i--) {
 480         outl(EE_ENB | EE_SHIFT_CLK, eectl);
 481         eeprom_delay(100);
 482         retval = (retval << 1) | ((inl(eectl) & EE_DATA_READ) ? 1 : 0);
 483         outl(EE_ENB, eectl);
 484         eeprom_delay(100);
 485     }
 486
 487     /* Terminate the EEPROM access. */
 488     outl(EE_ENB & ~EE_CS, eectl);
 489     return retval;
 490 }
 491 #endif
 492
 493
 494 #define MII_READOP      1
 495 #define MII_WRITEOP     2
 496
 497     static int
 498 mii_read(int phy_id, int location)
 499 {
 500     int i;
 501
 502     outl((phy_id << 9) | (location << 4) | MII_READOP, mmctl);
 503     /* Typical operation takes < 50 ticks. */
 504
 505     for (i = 4000; i > 0; i--)
 506         if ((inl(mmctl) & MII_READOP) == 0)
 507             break;
 508     return inw(mmdata);
 509 }
 510
 511 static struct nic_operations epic100_operations = {
 512         .connect        = dummy_connect,
 513         .poll           = epic100_poll,
 514         .transmit       = epic100_transmit,
 515         .irq            = epic100_irq,
 516
 517 };
 518
 519 static struct pci_device_id epic100_nics[] = {
 520 PCI_ROM(0x10b8, 0x0005, "epic100",    "SMC EtherPowerII"),              /* SMC 83c170 EPIC/100 */
 521 PCI_ROM(0x10b8, 0x0006, "smc-83c175", "SMC EPIC/C 83c175"),
 522 };
 523
 524 PCI_DRIVER ( epic100_driver, epic100_nics, PCI_NO_CLASS );
 525
 526 DRIVER ( "EPIC100", nic_driver, pci_driver, epic100_driver,
 527          epic100_probe, epic100_disable );